From 4edb1a19210b9b3118d7b0072e13a4363f81fb94 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Tue, 5 Sep 2023 22:19:28 -0400 Subject: [PATCH 001/240] sv: support assignments within expressions - Add support for assignments within expressions, e.g., `x[y++] = z;` or `x = (y *= 2) - 1;`. The logic is handled entirely within the parser by injecting statements into the current procedural block. - Add support for pre-increment/decrement statements, which are behaviorally equivalent to post-increment/decrement statements. - Fix non-standard attribute position used for post-increment/decrement statements. --- CHANGELOG | 4 + README.md | 2 + frontends/verilog/verilog_parser.y | 113 ++++++++++++++++++++------ tests/verilog/asgn_expr.sv | 60 ++++++++++++++ tests/verilog/asgn_expr.ys | 3 + tests/verilog/asgn_expr_not_proc_1.ys | 7 ++ tests/verilog/asgn_expr_not_proc_2.ys | 7 ++ tests/verilog/asgn_expr_not_proc_3.ys | 7 ++ tests/verilog/asgn_expr_not_proc_4.ys | 7 ++ tests/verilog/asgn_expr_not_proc_5.ys | 7 ++ tests/verilog/asgn_expr_not_sv_1.ys | 7 ++ tests/verilog/asgn_expr_not_sv_2.ys | 7 ++ tests/verilog/asgn_expr_not_sv_3.ys | 7 ++ tests/verilog/asgn_expr_not_sv_4.ys | 15 ++++ tests/verilog/task_attr.ys | 2 +- 15 files changed, 231 insertions(+), 24 deletions(-) create mode 100644 tests/verilog/asgn_expr.sv create mode 100644 tests/verilog/asgn_expr.ys create mode 100644 tests/verilog/asgn_expr_not_proc_1.ys create mode 100644 tests/verilog/asgn_expr_not_proc_2.ys create mode 100644 tests/verilog/asgn_expr_not_proc_3.ys create mode 100644 tests/verilog/asgn_expr_not_proc_4.ys create mode 100644 tests/verilog/asgn_expr_not_proc_5.ys create mode 100644 tests/verilog/asgn_expr_not_sv_1.ys create mode 100644 tests/verilog/asgn_expr_not_sv_2.ys create mode 100644 tests/verilog/asgn_expr_not_sv_3.ys create mode 100644 tests/verilog/asgn_expr_not_sv_4.ys diff --git a/CHANGELOG b/CHANGELOG index 465918a36d8..a662ba4dad3 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -5,6 +5,10 @@ List of major changes and improvements between releases Yosys 0.33 .. Yosys 0.34-dev -------------------------- + * SystemVerilog + - Added support for assignments within expressions, e.g., `x[y++] = z;` or + `x = (y *= 2) - 1;`. + Yosys 0.32 .. Yosys 0.33 -------------------------- * Various diff --git a/README.md b/README.md index 5e5a8ec3e12..69a227b7fb5 100644 --- a/README.md +++ b/README.md @@ -592,6 +592,8 @@ from SystemVerilog: - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether ports are inputs or outputs are supported. +- Assignments within expressions are supported. + Building the documentation ========================== diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 1e82940bbbd..d901b3b558d 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -292,6 +292,61 @@ static void rewriteGenForDeclInit(AstNode *loop) substitute(incr); } +static void ensureAsgnExprAllowed() +{ + if (!sv_mode) + frontend_verilog_yyerror("Assignments within expressions are only supported in SystemVerilog mode."); + if (ast_stack.back()->type != AST_BLOCK) + frontend_verilog_yyerror("Assignments within expressions are only permitted within procedures."); +} + +// add a pre/post-increment/decrement statement +static const AstNode *addIncOrDecStmt(AstNode *lhs, dict *attr, AST::AstNodeType op, YYLTYPE begin, YYLTYPE end) +{ + AstNode *one = AstNode::mkconst_int(1, true); + AstNode *rhs = new AstNode(op, lhs->clone(), one); + AstNode *stmt = new AstNode(AST_ASSIGN_EQ, lhs, rhs); + SET_AST_NODE_LOC(stmt, begin, end); + if (attr != nullptr) + append_attr(stmt, attr); + ast_stack.back()->children.push_back(stmt); + return stmt; +} + +// create a pre/post-increment/decrement expression, and add the corresponding statement +static AstNode *addIncOrDecExpr(AstNode *lhs, dict *attr, AST::AstNodeType op, YYLTYPE begin, YYLTYPE end, bool undo) +{ + ensureAsgnExprAllowed(); + const AstNode *stmt = addIncOrDecStmt(lhs, attr, op, begin, end); + log_assert(stmt->type == AST_ASSIGN_EQ); + AstNode *expr = stmt->children[0]->clone(); + if (undo) { + AstNode *minus_one = AstNode::mkconst_int(-1, true); + expr = new AstNode(op, expr, minus_one); + } + SET_AST_NODE_LOC(expr, begin, end); + return expr; +} + +// add a binary operator assignment statement, e.g., a += b +static const AstNode *addAsgnBinopStmt(dict *attr, AstNode *lhs, AST::AstNodeType op, AstNode *rhs, YYLTYPE begin, YYLTYPE end) +{ + SET_AST_NODE_LOC(rhs, end, end); + if (op == AST_SHIFT_LEFT || op == AST_SHIFT_RIGHT || + op == AST_SHIFT_SLEFT || op == AST_SHIFT_SRIGHT) { + rhs = new AstNode(AST_TO_UNSIGNED, rhs); + SET_AST_NODE_LOC(rhs, end, end); + } + rhs = new AstNode(op, lhs->clone(), rhs); + AstNode *stmt = new AstNode(AST_ASSIGN_EQ, lhs, rhs); + SET_AST_NODE_LOC(rhs, begin, end); + SET_AST_NODE_LOC(stmt, begin, end); + ast_stack.back()->children.push_back(stmt); + if (attr != nullptr) + append_attr(stmt, attr); + return lhs; +} + %} %define api.prefix {frontend_verilog_yy} @@ -358,7 +413,7 @@ static void rewriteGenForDeclInit(AstNode *loop) %type integer_atom_type integer_vector_type %type attr case_attr %type struct_union -%type asgn_binop +%type asgn_binop inc_or_dec_op %type genvar_identifier %type specify_target @@ -2610,17 +2665,15 @@ simple_behavioral_stmt: SET_AST_NODE_LOC(node, @2, @5); append_attr(node, $1); } | - attr lvalue TOK_INCREMENT { - AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true))); - ast_stack.back()->children.push_back(node); - SET_AST_NODE_LOC(node, @2, @3); - append_attr(node, $1); + attr lvalue attr inc_or_dec_op { + // The position 1 attr to avoid shift/reduce conflicts with the + // other productions. We reject attributes in that position. + if (!$1->empty()) + frontend_verilog_yyerror("Attributes are not allowed on this size of the lvalue in an inc_or_dec_expression!"); + addIncOrDecStmt($2, $3, $4, @1, @4); } | - attr lvalue TOK_DECREMENT { - AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_SUB, $2->clone(), AstNode::mkconst_int(1, true))); - ast_stack.back()->children.push_back(node); - SET_AST_NODE_LOC(node, @2, @3); - append_attr(node, $1); + inc_or_dec_op attr lvalue { + addIncOrDecStmt($3, $2, $1, @1, @3); } | attr lvalue OP_LE delay expr { AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5); @@ -2629,18 +2682,7 @@ simple_behavioral_stmt: append_attr(node, $1); } | attr lvalue asgn_binop delay expr { - AstNode *expr_node = $5; - if ($3 == AST_SHIFT_LEFT || $3 == AST_SHIFT_RIGHT || - $3 == AST_SHIFT_SLEFT || $3 == AST_SHIFT_SRIGHT) { - expr_node = new AstNode(AST_TO_UNSIGNED, expr_node); - SET_AST_NODE_LOC(expr_node, @5, @5); - } - AstNode *op_node = new AstNode($3, $2->clone(), expr_node); - AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, op_node); - SET_AST_NODE_LOC(op_node, @2, @5); - SET_AST_NODE_LOC(node, @2, @5); - ast_stack.back()->children.push_back(node); - append_attr(node, $1); + addAsgnBinopStmt($1, $2, $3, $5, @2, @5); }; asgn_binop: @@ -2657,6 +2699,12 @@ asgn_binop: TOK_SSHL_ASSIGN { $$ = AST_SHIFT_SLEFT; } | TOK_SSHR_ASSIGN { $$ = AST_SHIFT_SRIGHT; } ; +inc_or_dec_op: + // NOTE: These should only be permitted in SV mode, but Yosys has + // allowed them in all modes since support for them was added in 2017. + TOK_INCREMENT { $$ = AST_ADD; } | + TOK_DECREMENT { $$ = AST_SUB; } ; + for_initialization: TOK_ID '=' expr { AstNode *ident = new AstNode(AST_IDENTIFIER); @@ -3149,6 +3197,14 @@ expr: $$->children.push_back($6); SET_AST_NODE_LOC($$, @1, @$); append_attr($$, $3); + } | + inc_or_dec_op attr rvalue { + $$ = addIncOrDecExpr($3, $2, $1, @1, @3, false); + } | + // TODO: Attributes are allowed in the middle here, but they create some + // non-trivial conflicts that don't seem worth solving for now. + rvalue inc_or_dec_op { + $$ = addIncOrDecExpr($1, nullptr, $2, @1, @2, true); }; basic_expr: @@ -3436,6 +3492,17 @@ basic_expr: frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode."); $$ = new AstNode(AST_CAST_SIZE, $1, $4); SET_AST_NODE_LOC($$, @1, @4); + } | + '(' expr '=' expr ')' { + ensureAsgnExprAllowed(); + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $4); + ast_stack.back()->children.push_back(node); + SET_AST_NODE_LOC(node, @2, @4); + $$ = $2->clone(); + } | + '(' expr asgn_binop expr ')' { + ensureAsgnExprAllowed(); + $$ = addAsgnBinopStmt(nullptr, $2, $3, $4, @2, @4)-> clone(); }; concat_list: diff --git a/tests/verilog/asgn_expr.sv b/tests/verilog/asgn_expr.sv new file mode 100644 index 00000000000..567034d107d --- /dev/null +++ b/tests/verilog/asgn_expr.sv @@ -0,0 +1,60 @@ +module top; + integer x, y, z; + task check; + input integer a, b, c; + assert (x == a); + assert (y == b); + assert (z == c); + endtask + always_comb begin + x = 0; y = 0; z = 0; + check(0, 0, 0); + + // post-increment/decrement statements + x++; + check(1, 0, 0); + y (* foo *) ++; + check(1, 1, 0); + z--; + check(1, 1, -1); + z (* foo *) --; + check(1, 1, -2); + + // pre-increment/decrement statements are equivalent + ++z; + check(1, 1, -1); + ++ (* foo *) z; + check(1, 1, 0); + --x; + check(0, 1, 0); + -- (* foo *) y; + check(0, 0, 0); + + // procedural pre-increment/decrement expressions + z = ++x; + check(1, 0, 1); + z = ++ (* foo *) x; + check(2, 0, 2); + y = --x; + check(1, 1, 2); + y = -- (* foo *) x; + + // procedural post-increment/decrement expressions + // TODO: support attributes on post-increment/decrement + check(0, 0, 2); + y = x++; + check(1, 0, 2); + y = x--; + check(0, 1, 2); + + // procedural assignment expressions + x = (y = (z = 99) + 1) + 1; + check(101, 100, 99); + x = (y *= 2); + check(200, 200, 99); + x = (z >>= 2) * 4; + check(96, 200, 24); + y = (z >>= 1'sb1) * 2; // shift is implicitly cast to unsigned + check(96, 24, 12); + end +endmodule diff --git a/tests/verilog/asgn_expr.ys b/tests/verilog/asgn_expr.ys new file mode 100644 index 00000000000..18180c7854f --- /dev/null +++ b/tests/verilog/asgn_expr.ys @@ -0,0 +1,3 @@ +read_verilog -sv asgn_expr.sv +proc +sat -verify -prove-asserts -show-all diff --git a/tests/verilog/asgn_expr_not_proc_1.ys b/tests/verilog/asgn_expr_not_proc_1.ys new file mode 100644 index 00000000000..72ba0bd89dc --- /dev/null +++ b/tests/verilog/asgn_expr_not_proc_1.ys @@ -0,0 +1,7 @@ +logger -expect error "Assignments within expressions are only permitted within procedures." 1 +read_verilog -sv < Date: Wed, 6 Sep 2023 16:35:17 -0700 Subject: [PATCH 002/240] multpass -- create Booth Encoded multipliers for --- passes/techmap/Makefile.inc | 1 + passes/techmap/multpass.cc | 1541 +++++++++++++++++++++++++++++++++++ 2 files changed, 1542 insertions(+) create mode 100644 passes/techmap/multpass.cc diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 1b834fabc3b..8b0b2aa23b7 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -4,6 +4,7 @@ OBJS += passes/techmap/techmap.o OBJS += passes/techmap/simplemap.o OBJS += passes/techmap/dfflibmap.o OBJS += passes/techmap/maccmap.o +OBJS += passes/techmap/multpass.o OBJS += passes/techmap/libparse.o ifeq ($(ENABLE_ABC),1) diff --git a/passes/techmap/multpass.cc b/passes/techmap/multpass.cc new file mode 100644 index 00000000000..e55a0441448 --- /dev/null +++ b/passes/techmap/multpass.cc @@ -0,0 +1,1541 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + MultPass + -------- + + Replace $mul with booth encoded multipliers. Two different + architectures used for signed/unsigned. + + References: + Signed architecture: A Low Power Radix-4 Booth Multipliers with Pre-Encoded Mechanism, IEEE Access + https://ieeexplore.ieee.org/document/9121226 + + Unsigned architecture: Gary Bewick, Fast Multiplication algorithms and implementation. Stanford PhD: + http://i.stanford.edu/pub/cstr/reports/csl/tr/94/617/CSL-TR-94-617.pdf + + How to use: + Add multpass to your yosys script eg: + + read_verilog smultiply5_rtl.v + opt + wreduce + opt + multpass + alumacc + maccmap + opt + techmap -map ./techmap.v + dfflibmap -liberty NangateOpenCellLibrary_typical.lib + abc -liberty NangateOpenCellLibrary_typical.lib + stat -liberty NangateOpenCellLibrary_typical.lib + write_verilog -norename booth_final.v +*/ + +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct MultPassWorker { + + RTLIL::Module *module; + SigMap sigmap; + int booth_counter; + + MultPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; } + + // Helper routines for building architecture subcomponents + + void connect_sigSpecToWire(RTLIL::Wire *ip, const SigSpec &v) + { + auto g = module->addCell(NEW_ID, ID($pos)); + g->setParam(ID::A_WIDTH, 1); + g->setParam(ID::Y_WIDTH, 1); + g->setParam(ID::A_SIGNED, false); + g->setPort(ID::A, ip); + g->setPort(ID::Y, v); + } + + RTLIL::Wire *mk_wireFromSigSpec(const SigSpec &v) + { + + auto g = module->addCell(NEW_ID, ID($pos)); + Wire *ret = module->addWire(NEW_ID, 1); + g->setPort(ID::A, v); + g->setPort(ID::Y, ret); + g->setParam(ID::A_WIDTH, 1); + g->setParam(ID::Y_WIDTH, 1); + g->setParam(ID::A_SIGNED, false); + return ret; + } + + // fuse wires. + void join_wires_with_buffer(RTLIL::Wire *ip, RTLIL::Wire *op) + { + std::string wire_name = "join_"; + auto g = module->addCell(new_id(wire_name, __LINE__, ""), ID($pos)); + g->setParam(ID::A_WIDTH, 1); + g->setParam(ID::Y_WIDTH, 1); + g->setParam(ID::A_SIGNED, false); + g->setPort(ID::A, ip); + g->setPort(ID::Y, op); + } + + // Unary gate + RTLIL::Wire *mk_ugate1(const RTLIL::IdString &red_typ, std::string &name, RTLIL::Wire *ip1, std::string &op_name) + { + std::string op_wire_name; + if (op_name.empty()) + op_wire_name = name + "_o"; + else + op_wire_name = op_name; + RTLIL::Wire *ret = module->addWire(new_id(op_wire_name, __LINE__, ""), 1); + auto g = module->addCell(new_id(name, __LINE__, ""), red_typ); + g->setPort(ID::A, ip1); + g->setPort(ID::Y, ret); + g->setParam(ID::A_SIGNED, false); + g->setParam(ID::A_WIDTH, 1); + g->setParam(ID::Y_WIDTH, 1); + return ret; + } + + // Binary gate + RTLIL::Wire *mk_ugate2(const RTLIL::IdString &red_typ, std::string &name, RTLIL::Wire *ip1, RTLIL::Wire *ip2, std::string &op_name) + { + auto g = module->addCell(new_id(name, __LINE__, ""), red_typ); + std::string op_wire_name; + if (op_name.empty()) + op_wire_name = name + "_o"; + else + op_wire_name = op_name; + + auto ret = module->addWire(new_id(op_wire_name, __LINE__, ""), 1); + + g->setPort(ID::A, ip1); + g->setPort(ID::B, ip2); + g->setPort(ID::Y, ret); + g->setParam(ID::A_SIGNED, false); + g->setParam(ID::B_SIGNED, false); + g->setParam(ID::A_WIDTH, 1); + g->setParam(ID::B_WIDTH, 1); + g->setParam(ID::Y_WIDTH, 1); + return ret; + } + + // Booth unsigned decoder lsb + void BuildBur4d_lsb(std::string &name, RTLIL::Wire *lsb_i, RTLIL::Wire *one_i, RTLIL::Wire *s_i, RTLIL::Wire *&ppij_o, + std::string op_wire_name) + { + std::string empty; + auto and_op = mk_ugate2(ID($and), name, lsb_i, one_i, empty); + ppij_o = mk_ugate2(ID($xor), name, and_op, s_i, op_wire_name); + } + + // Booth unsigned radix4 decoder + void BuildBur4d_n(std::string &name, RTLIL::Wire *yn_i, RTLIL::Wire *ynm1_i, RTLIL::Wire *one_i, RTLIL::Wire *two_i, RTLIL::Wire *s_i, + RTLIL::Wire *&ppij_o) + { + // ppij = ((yn & one) | (ynm1 & two)) ^ s; + std::string empty; + auto an1 = mk_ugate2(ID($and), name, yn_i, one_i, empty); + auto an2 = mk_ugate2(ID($and), name, ynm1_i, two_i, empty); + auto or1 = mk_ugate2(ID($or), name, an1, an2, empty); + ppij_o = mk_ugate2(ID($xor), name, s_i, or1, empty); + } + + // Booth unsigned radix4 decoder + void BuildBur4d_msb(std::string &name, RTLIL::Wire *msb_i, RTLIL::Wire *two_i, RTLIL::Wire *s_i, RTLIL::Wire *&ppij_o) + { + // ppij = (msb & two) ^ s; + std::string empty; + auto an1 = mk_ugate2(ID($and), name, msb_i, two_i, empty); + ppij_o = mk_ugate2(ID($xor), name, s_i, an1, empty); + } + + // half adder, used in CPA + void BuildHa(std::string &name, RTLIL::Wire *a_i, RTLIL::Wire *b_i, RTLIL::Wire *&s_o, RTLIL::Wire *&c_o) + { + std::string empty; + s_o = mk_ugate2(ID($xor), name, a_i, b_i, empty); + c_o = mk_ugate2(ID($and), name, a_i, b_i, empty); + } + + // Booth unsigned radix 4 encoder + void BuildBur4e(std::string &name, RTLIL::Wire *y0_i, RTLIL::Wire *y1_i, RTLIL::Wire *y2_i, + + RTLIL::Wire *&one_o, RTLIL::Wire *&two_o, RTLIL::Wire *&s_o, RTLIL::Wire *&sb_o) + { + + std::string empty; + one_o = mk_ugate2(ID($xor), name, y0_i, y1_i, empty); + s_o = y2_i; + sb_o = mk_ugate1(ID($not), name, y2_i, empty); + auto inv_y1_xor_y2 = mk_ugate1(ID($not), name, mk_ugate2(ID($xor), name, y1_i, y2_i, empty), empty); + two_o = mk_ugate1(ID($not), name, mk_ugate2(ID($or), name, inv_y1_xor_y2, one_o, empty), empty); + } + + void BuildBr4e(std::string &name, RTLIL::Wire *y2_m1_i, + RTLIL::Wire *y2_i, // y2i + RTLIL::Wire *y2_p1_i, + + RTLIL::Wire *&negi_o, RTLIL::Wire *&twoi_n_o, RTLIL::Wire *&onei_n_o, RTLIL::Wire *&cori_o) + { + + std::string empty; + auto y2_p1_n = mk_ugate1(ID($not), name, y2_p1_i, empty); + auto y2_n = mk_ugate1(ID($not), name, y2_i, empty); + auto y2_m1_n = mk_ugate1(ID($not), name, y2_m1_i, empty); + + // negi_o = y2_p1_i + negi_o = mk_ugate1(ID($pos), name, y2_p1_i, empty); + // twoi_n = ~( + // (y2_p1_n & y2_i & y2_m1_i) | + // (y2_p1 & y2_n & y2_m1_n) + // ) + auto and3_1 = mk_ugate2(ID($and), name, y2_p1_n, mk_ugate2(ID($and), name, y2_i, y2_m1_i, empty), empty); + auto and3_2 = mk_ugate2(ID($and), name, y2_p1_i, mk_ugate2(ID($and), name, y2_n, y2_m1_n, empty), empty); + + twoi_n_o = mk_ugate1(ID($not), name, mk_ugate2(ID($or), name, and3_1, and3_2, empty), empty); + // onei_n = ~(y2_m1_i ^ y2_i); + onei_n_o = mk_ugate1(ID($not), name, mk_ugate2(ID($xor), name, y2_m1_i, y2_i, empty), empty); + // cori = (y2_m1_n | y2_n) & y2_p1_i; + cori_o = mk_ugate2(ID($and), name, y2_p1_i, mk_ugate2(ID($or), name, y2_m1_n, y2_n, empty), empty); + } + + // + // signed booth radix 4 decoder + // + void BuildBr4d(std::string &name, RTLIL::Wire *nxj_m1_i, RTLIL::Wire *twoi_n_i, RTLIL::Wire *xj_i, RTLIL::Wire *negi_i, RTLIL::Wire *onei_n_i, + + RTLIL::Wire *&ppij_o, RTLIL::Wire *&nxj_o) + { + + std::string empty; + // nxj_in = xnor(xj,negi) + // nxj_o = xnj_in, + // ppij = ~( (nxj_m1_i | twoi_n_i) & (nxj_int | onei_n_i)); + nxj_o = mk_ugate2(ID($xnor), name, xj_i, negi_i, empty); + RTLIL::Wire *or1 = mk_ugate2(ID($or), name, nxj_m1_i, twoi_n_i, empty); + RTLIL::Wire *or2 = mk_ugate2(ID($or), name, nxj_o, onei_n_i, empty); + ppij_o = mk_ugate1(ID($not), name, mk_ugate2(ID($and), name, or1, or2, empty), empty); + } + + /* + In signed case 1st two bits best realised + using non-booth encoded logic. We can save a booth + encoder for the first couple of bits. + */ + void BuildBoothQ1(std::string &name, RTLIL::Wire *negi_i, RTLIL::Wire *cori_i, RTLIL::Wire *x0_i, RTLIL::Wire *x1_i, RTLIL::Wire *y0_i, + RTLIL::Wire *y1_i, + + RTLIL::Wire *&nxj_o, RTLIL::Wire *&cor_o, RTLIL::Wire *&pp0_o, RTLIL::Wire *&pp1_o + + ) + { + /* + assign NXJO = ~(X1 ^ NEGI); + assign PP0 = (X0 & Y0); + //and terms for multiply + wire pp1_1_int = X1 & Y0; + wire pp1_2_int = X0 & Y1; + //sum generation for pp[1] + assign PP1 = pp1_1_int ^ pp1_2_int; + //correction propagation + assign CORO = (~PP1 & ~PP0)? CORI : 1'b0; + */ + std::string empty; + nxj_o = mk_ugate2(ID($xnor), name, x1_i, negi_i, empty); + pp0_o = mk_ugate2(ID($and), name, x0_i, y0_i, empty); + RTLIL::Wire *pp1_1_int = mk_ugate2(ID($and), name, x1_i, y0_i, empty); + RTLIL::Wire *pp1_2_int = mk_ugate2(ID($and), name, x0_i, y1_i, empty); + pp1_o = mk_ugate2(ID($xor), name, pp1_1_int, pp1_2_int, empty); + + RTLIL::Wire *pp1_nor_pp0 = mk_ugate1(ID($not), name, mk_ugate2(ID($or), name, pp1_o, pp0_o, empty), empty); + cor_o = mk_ugate2(ID($and), name, pp1_nor_pp0, cori_i, empty); + } + + void run() + { + log("Extracting $mul cells in module %s and generating Booth Realization:\n", log_id(module)); + for (auto cell : module->selected_cells()) { + if (cell->type.in(ID($mul))) { + RTLIL::SigSpec A = sigmap(cell->getPort(ID::A)); + RTLIL::SigSpec B = sigmap(cell->getPort(ID::B)); + RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y)); + if (GetSize(A) >= 4 && GetSize(B) >= 4 && GetSize(Y) >= 8 && + ((cell->getParam(ID::A_SIGNED).as_bool() && cell->getParam(ID::B_SIGNED).as_bool()) || + (!cell->getParam(ID::A_SIGNED).as_bool() && !cell->getParam(ID::B_SIGNED).as_bool()))) { + bool is_signed = false; + if (cell->getParam(ID::A_SIGNED).as_bool()) { + log(" By passing macc inferencing for signed multiplier -- generating booth\n"); + is_signed = true; + } else + log(" By passing macc inferencing for unsigned multiplier -- generating booth\n"); + + if (is_signed == false) /* unsigned multiplier */ { + int x_sz = GetSize(A); + int y_sz = GetSize(B); + int z_sz = GetSize(Y); + + // create a buffer for each ip + std::string buf_name = "u_mult_multiplicand_buf_"; + auto A_Buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + A_Buf->setParam(ID::A_WIDTH, x_sz); + A_Buf->setParam(ID::Y_WIDTH, x_sz); + A_Buf->setPort(ID::A, SigSpec(A)); + A_Buf->setParam(ID::A_SIGNED, false); + + std::string wire_name = "u_mult_A"; + auto A_Wire = module->addWire(new_id(wire_name, __LINE__, ""), x_sz); + + A_Buf->setPort(ID::Y, A_Wire); + + buf_name = "u_mult_multiplier_buf_"; + auto B_Buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + B_Buf->setParam(ID::A_WIDTH, y_sz); + B_Buf->setParam(ID::Y_WIDTH, y_sz); + B_Buf->setPort(ID::A, SigSpec(B)); + B_Buf->setParam(ID::A_SIGNED, false); + + wire_name = "u_mult_B"; + auto B_Wire = module->addWire(new_id(wire_name, __LINE__, ""), y_sz); + B_Buf->setPort(ID::Y, B_Wire); + + buf_name = "u_mult_result_buf_"; + auto Z_Buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + Z_Buf->setParam(ID::A_WIDTH, z_sz); + Z_Buf->setParam(ID::Y_WIDTH, z_sz); + Z_Buf->setPort(ID::Y, SigSpec(Y)); + Z_Buf->setParam(ID::A_SIGNED, false); + wire_name = "u_mult_Z"; + auto Z_Wire = module->addWire(new_id(wire_name, __LINE__, ""), z_sz); + Z_Buf->setPort(ID::A, Z_Wire); + + CreateBoothUMult(module, x_sz, y_sz, z_sz, + A_Wire, // multiplicand + B_Wire, // multiplier(scanned) + Z_Wire // result + ); + module->remove(cell); + booth_counter++; + continue; + } + + else /*signed multiplier */ { + int x_sz = GetSize(A); + int y_sz = GetSize(B); + int z_sz = GetSize(Y); + + // make wire of correct size to feed multiplier + Wire *expanded_A = module->addWire(NEW_ID, x_sz); + + Wire *expanded_B = module->addWire(NEW_ID, y_sz); + + std::string buf_name = "expand_a_buf_"; + auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + buf->setParam(ID::A_WIDTH, x_sz); + buf->setParam(ID::Y_WIDTH, x_sz); + buf->setPort(ID::A, SigSpec(A)); + buf->setParam(ID::A_SIGNED, is_signed ? true : false); + buf->setPort(ID::Y, SigSpec(expanded_A)); + + buf_name = "expand_b_buf_"; + buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + buf->setPort(ID::A, SigSpec(B)); + buf->setParam(ID::A_WIDTH, y_sz); + buf->setParam(ID::Y_WIDTH, y_sz); + + buf->setParam(ID::A_SIGNED, is_signed ? true : false); + buf->setPort(ID::Y, SigSpec(expanded_B)); + + // + // Make a wire to take the expanded output + // wires + // + + Wire *expanded_Y = module->addWire(NEW_ID, (is_signed == false ? z_sz + 2 : z_sz)); + CreateBoothSMult(module, x_sz, y_sz, (is_signed == false ? z_sz + 2 : z_sz), + expanded_A, // multiplicand + expanded_B, // multiplier(scanned) + expanded_Y // result + ); + // now connect the expanded_Y with a tap to fill out sig Spec Y + + buf_name = "reducer_buf_"; + buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + buf->setPort(ID::A, expanded_Y); + buf->setParam(ID::A_WIDTH, is_signed == false ? z_sz + 2 : z_sz); + buf->setParam(ID::Y_WIDTH, z_sz); + buf->setParam(ID::A_SIGNED, is_signed ? true : false); + // wire in output Y + buf->setPort(ID::Y, SigSpec(Y)); + + // kill original multiplier + module->remove(cell); + booth_counter++; + continue; + } + } + } + } + } + + /* + Build Unsigned Multiplier. + ------------------------- + Create a booth unsigned multiplier. + Uses a generic booth multiplier with + extra row of decoders and extended multiplier + */ + + void CreateBoothUMult(RTLIL::Module *module, int x_sz, int y_sz, int z_sz, + RTLIL::Wire *X, // multiplicand + RTLIL::Wire *Y, // multiplier + RTLIL::Wire *Z) + { // result + + std::vector one_int; + std::vector two_int; + std::vector s_int; + std::vector sb_int; + int encoder_count = 0; + + BuildBoothUMultEncoders(Y, y_sz, one_int, two_int, s_int, sb_int, module, encoder_count); + + // Build the decoder rows + // format of each Partial product to be passed to CSA + // tree builder: + // + // Bits to be added + // Shift + // Sign bit to be added + // + std::vector, int, RTLIL::Wire *>> ppij_int; + + static int constant_ix; + constant_ix++; + std::string buf_name = "constant_buf_" + std::to_string(constant_ix); + auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + RTLIL::Wire *constant_one = module->addWire(new_id(buf_name, __LINE__, ""), 1); + buf->setPort(ID::A, State::S1); + buf->setParam(ID::A_WIDTH, 1); + buf->setParam(ID::Y_WIDTH, 1); + buf->setParam(ID::A_SIGNED, true); + buf->setPort(ID::Y, constant_one); + + constant_ix++; + buf_name = "constant_buf_" + std::to_string(constant_ix); + buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + RTLIL::Wire *constant_zero = module->addWire(new_id(buf_name, __LINE__, ""), 1); + buf->setPort(ID::A, State::S0); + buf->setParam(ID::A_WIDTH, 1); + buf->setParam(ID::Y_WIDTH, 1); + buf->setParam(ID::A_SIGNED, true); + buf->setPort(ID::Y, constant_zero); + + // Row 0: special case 1. Format S/.S.S.C.Data + std::vector ppij_row_0; + BuildBoothUMultDecoderRow0(module, X, s_int, sb_int, one_int, two_int, ppij_row_0); + + // data, shift, sign + ppij_int.push_back(std::make_tuple(ppij_row_0, 0, s_int[0])); + + for (int i = 1; i < encoder_count - 2; i++) { + // format 1,S.Data.shift = encoder_ix*2,sign = sb_int[i] + std::vector ppij_row_n; + + BuildBoothUMultDecoderRowN(module, + X, // multiplicand + one_int[i], two_int[i], s_int[i], sb_int[i], ppij_row_n, constant_one, i, + false, // include sign + false // include constant + ); + // data, shift, sign + ppij_int.push_back(std::make_tuple(ppij_row_n, i * 2, s_int[i])); + } + + // Build second to last row + // format S/,Data + sign bit + std::vector ppij_row_em1; + BuildBoothUMultDecoderRowN(module, X, one_int[encoder_count - 2], two_int[encoder_count - 2], s_int[encoder_count - 2], + sb_int[encoder_count - 2], ppij_row_em1, constant_one, encoder_count - 2, + false, // include sign + true // no constant + ); + ppij_int.push_back(std::make_tuple(ppij_row_em1, (encoder_count - 2) * 2, s_int[encoder_count - 2])); + // Build last row + // format Data + sign bit + std::vector ppij_row_e; + BuildBoothUMultDecoderRowN(module, X, one_int[encoder_count - 1], two_int[encoder_count - 1], s_int[encoder_count - 1], + sb_int[encoder_count - 1], ppij_row_e, constant_one, encoder_count - 1, + true, // no sign + true // no constant + ); + ppij_int.push_back(std::make_tuple(ppij_row_e, (encoder_count - 1) * 2, s_int[encoder_count - 1])); + + // Debug dump out partial products + // DebugDumpPP(ppij_int); + + // Summation of Partial Products (Wallace Tree) + std::vector> aligned_pp; + aligned_pp.resize(encoder_count + 1); // make an entirely redundant row + // just for sign bit in lsb. (We then filter this out). + + // resize all to be same size as z + for (int i = 0; i < encoder_count + 1; i++) + aligned_pp[i].resize(z_sz); + + AlignPP(x_sz, z_sz, ppij_int, aligned_pp); + + // Debug: dump out aligned partial products. + // Later on yosys will clean up unused constants + // DebugDumpAlignPP(aligned_pp); + + std::vector s_vec; + std::vector c_vec; + std::vector> debug_csa_trees; + + debug_csa_trees.resize(z_sz); + + BuildCSATree(module, aligned_pp, s_vec, c_vec, debug_csa_trees); + + // Debug code: Dump out the csa trees + // DumpCSATrees(debug_csa_trees); + // Build the CPA to do the final accumulation. + BuildCPA(module, s_vec, c_vec, Z); + } + + /* + Build Row 0 of decoders + */ + + void BuildBoothUMultDecoderRow0(RTLIL::Module *module, + RTLIL::Wire *X, // multiplicand + std::vector &s_int, std::vector &sb_int, std::vector &one_int, + std::vector &two_int, std::vector &ppij_vec) + { + (void)module; + int x_sz = GetSize(X); + + // lsb + std::string dec_name = "row0_lsb_dec"; + + RTLIL::Wire *ppij; + std::string ppij_name = "ppij_0_0"; + BuildBur4d_lsb(dec_name, mk_wireFromSigSpec(SigSpec(X, 0, 1)), one_int[0], s_int[0], ppij, ppij_name); + ppij_vec.push_back(ppij); + + // 1..xsize -1 + for (int i = 1; i < x_sz; i++) { + dec_name = "row0_dec_" + std::to_string(i); + RTLIL::Wire *ppij; + BuildBur4d_n(dec_name, mk_wireFromSigSpec(SigSpec(X, i, 1)), mk_wireFromSigSpec(SigSpec(X, i - 1, 1)), one_int[0], two_int[0], + s_int[0], ppij); + ppij_vec.push_back(ppij); + } + + // The redundant bit. Duplicate decoding of last bit. + dec_name = "row0_dec_msb"; + BuildBur4d_msb(dec_name, mk_wireFromSigSpec(SigSpec(X, x_sz - 1, 1)), two_int[0], s_int[0], ppij); + ppij_vec.push_back(ppij); + + // append the sign bits + ppij_vec.push_back(s_int[0]); + ppij_vec.push_back(s_int[0]); + ppij_vec.push_back(sb_int[0]); + } + + // Build a generic row of decoders. + + void BuildBoothUMultDecoderRowN(RTLIL::Module *module, + RTLIL::Wire *X, // multiplicand + RTLIL::Wire *one_int, RTLIL::Wire *two_int, RTLIL::Wire *s_int, RTLIL::Wire *sb_int, + std::vector &ppij_vec, RTLIL::Wire *constant_one, int row_ix, bool no_sign, bool no_constant) + { + (void)module; + int x_sz = GetSize(X); + + // lsb + std::string ppij_name = "ppij_" + std::to_string(row_ix) + "_0"; + RTLIL::Wire *ppij = nullptr; + std::string empty; + std::string dec_name = "row" + std::to_string(row_ix) + "_lsb_dec"; + BuildBur4d_lsb(dec_name, mk_wireFromSigSpec(SigSpec(X, 0, 1)), one_int, s_int, ppij, empty); + + ppij_vec.push_back(ppij); + + // core bits + for (int i = 1; i < x_sz; i++) { + + dec_name = "row_" + std::to_string(row_ix) + "_dec_" + std::to_string(i); + RTLIL::Wire *ppij = nullptr; + BuildBur4d_n(dec_name, mk_wireFromSigSpec(SigSpec(X, i, 1)), mk_wireFromSigSpec(SigSpec(X, i - 1, 1)), one_int, two_int, + s_int, ppij); + ppij_vec.push_back(ppij); + } + + // redundant bit + + dec_name = "row_dec_red"; + BuildBur4d_msb(dec_name, mk_wireFromSigSpec(SigSpec(X, x_sz - 1, 1)), two_int, s_int, ppij); + ppij_vec.push_back(ppij); + + // sign bit + if (no_sign == false) // if no sign is false then make a sign bit + ppij_vec.push_back(sb_int); + + // constant bit + if (no_constant == false) { // if non constant is false make a constant bit + ppij_vec.push_back(constant_one); + } + } + + void DebugDumpAlignPP(std::vector> &aligned_pp) + { + printf("Aligned & Padded Partial products\n"); + int pp_ix = 0; + for (auto pp_row : aligned_pp) { + printf("PP_%d \t", pp_ix); + for (unsigned i = 0; i < pp_row.size(); i++) + printf("[%d] %s ", i, pp_row[i] == nullptr ? " 0 " : pp_row[i]->name.c_str()); + printf("\n"); + pp_ix++; + } + } + + // Debug routines to inspect intermediate results + void DebugDumpPP(std::vector, int, RTLIL::Wire *>> &ppij_int) + { + printf("Debug dump of partial products\n"); + int pp_ix = 0; + + for (auto pp : ppij_int) { + int shift = get<1>(pp); + RTLIL::Wire *sign_bit = get<2>(pp); + + printf("PP %d\n", pp_ix); + printf("\tShift %d\n", shift); + printf("\tData (0 lsb)\n\t"); + int ix = 0; + + for (auto pp_wire : get<0>(pp)) { + RTLIL::IdString wire_name = pp_wire->name; + + printf(" [%d]:%s ", ix, wire_name.c_str()); + ix++; + } + printf("\n"); + printf("\tSign bit to add in: %s\n", sign_bit->name.c_str()); + + pp_ix++; + } + } + + void DumpCSATrees(std::vector> &debug_csa_trees) + { + int i = 0; + for (auto csa_tree : debug_csa_trees) { + printf("CSA Tree column %d\n", i); + int ix = 0; + for (auto csa_elem : csa_tree) { + printf("\tCell %d %s type %s\n", ix, csa_elem->name.c_str(), csa_elem->type.c_str()); + if (csa_elem->getPort(ID::A) == State::S0) + printf("\tA set to constant 0\n"); + else if (csa_elem->getPort(ID::A) == State::S1) + printf("\tA set to constant 1\n"); + else + printf("\tA driven by %s\n", csa_elem->getPort(ID::A).as_wire()->name.c_str()); + + if (csa_elem->getPort(ID::B) == State::S0) + printf("\tB set to constant 0\n"); + else if (csa_elem->getPort(ID::B) == State::S1) + printf("\tB set to constant 1\n"); + else + printf("\tB driven by %s\n", csa_elem->getPort(ID::B).as_wire()->name.c_str()); + + if (csa_elem->getPort(ID::C) == State::S0) + printf("\tC set to constant 0\n"); + else if (csa_elem->getPort(ID::C) == State::S1) + printf("\tC set to constant 1\n"); + else + printf("\tC driven by %s\n", csa_elem->getPort(ID::C).as_wire()->name.c_str()); + + printf("Carry out: %s\n", csa_elem->getPort(ID::X).as_wire()->name.c_str()); + printf("Sum out: %s\n", csa_elem->getPort(ID::Y).as_wire()->name.c_str()); + + ix++; + } + i++; + } + } + + void BuildCSATree(RTLIL::Module *module, std::vector> &bits_to_reduce, std::vector &s_vec, + std::vector &c_vec, std::vector> &debug_csa_trees) + { + + if (!(bits_to_reduce.size() > 0)) + return; + + int column_size = bits_to_reduce[0].size(); + int row_size = bits_to_reduce.size(); + std::vector carry_bits_to_add_to_next_column; + + for (int column_ix = 0; column_ix < column_size; column_ix++) { + + // get the bits in this column. + std::vector column_bits; + for (int row_ix = 0; row_ix < row_size; row_ix++) { + if (bits_to_reduce[row_ix].at(column_ix)) + column_bits.push_back(bits_to_reduce[row_ix].at(column_ix)); + } + for (auto c : carry_bits_to_add_to_next_column) { +#ifdef DEBUG_CSA + printf("\t Propagating column bit %s to column %d from column %d\n", c->name.c_str(), column_ix, column_ix - 1); +#endif + column_bits.push_back(c); + } + + carry_bits_to_add_to_next_column.resize(0); + +#ifdef DEBUG_CSA + printf("Column %d Reducing %d bits\n", column_ix, column_bits.size()); + for (auto b : column_bits) { + printf("\t %s\n", b->name.c_str()); + } + printf("\n"); +#endif + + RTLIL::Wire *s = nullptr; + RTLIL::Wire *c = nullptr; +#ifdef DEBUG_CSA + int csa_count_before = debug_csa_trees[column_ix].size(); +#endif + + ReduceBits(module, column_ix, column_bits, s, c, carry_bits_to_add_to_next_column, debug_csa_trees); + + s_vec.push_back(s); + c_vec.push_back(c); + +#ifdef DEBUG_CSA + int csa_count_after = debug_csa_trees[column_ix].size(); + + printf("Column %d Created %d csa tree elements\n", column_ix, csa_count_after - csa_count_before); +#endif + } + } + + /* + Alignment: + --------- + + Concept traverse from last row. + Pad row by shift + Add sign bit from prior row to 2 bits right of end of data. + + Example + + SCDDDDDDD- +S + DDDDDDDD_ + + ==> + SCDDDDDDD- + DDDDDDDD_S <-- prior rows sign bit added 2 columns to right on next row. + + Pad out rows with zeros and left the opt pass clean them up. + + */ + void AlignPP(int x_sz, int z_sz, std::vector, int, RTLIL::Wire *>> &ppij_int, + std::vector> &aligned_pp) + { + unsigned aligned_pp_ix = aligned_pp.size() - 1; + + // default is zero for everything (so don't have to think to hard + // about padding). + + for (unsigned i = 0; i < aligned_pp.size(); i++) { + for (int j = 0; j < z_sz; j++) { + aligned_pp[i][j] = nullptr; + } + } + + // for very last row we just have the sign bit + // Note that the aligned_pp is one row bigger + // than the ppij_int. We put the sign bit + // in first column of the last partial product + // which is at index corresponding to size of multiplicand + { + RTLIL::Wire *prior_row_sign = nullptr; + prior_row_sign = get<2>(ppij_int[aligned_pp_ix - 1]); + if (prior_row_sign) { + log_assert(aligned_pp_ix < aligned_pp.size()); + log_assert(x_sz - 1 < (int)(aligned_pp[aligned_pp_ix].size())); + aligned_pp[aligned_pp_ix][x_sz - 1] = prior_row_sign; + } + } + + for (int row_ix = aligned_pp_ix - 1; row_ix >= 0; row_ix--) { + int shift_amount = get<1>(ppij_int[row_ix]); + RTLIL::Wire *prior_row_sign = nullptr; + + // copy in data + unsigned copy_ix = shift_amount; + for (auto w : get<0>(ppij_int[row_ix])) { + if (copy_ix < aligned_pp[row_ix].size()) { + aligned_pp[row_ix][copy_ix] = w; + } + copy_ix++; + } + + // copy in the sign bit from the prior row + if (row_ix > 0) { + // if sign bit on prior row, copy in + // the destination of the sign bit is the (row_ix -1)*2 + // eg destination for sign bit for row 0 is 0. + // eg destination for sign bit for row 1 is 1 + prior_row_sign = get<2>(ppij_int[row_ix - 1]); + copy_ix = (row_ix - 1) * 2; + aligned_pp[row_ix][copy_ix] = prior_row_sign; + } + } + } + + /* + Build a Carry Propagate Adder + ----------------------------- + First build the sum and carry vectors to be added. + Axioms: + c_vec.size() == s_vec.size() + result.size() == s_vec.size() + 2; (assume result is reserved to hold correct size) + */ + void BuildCPA(RTLIL::Module *module, std::vector &s_vec, std::vector &c_vec, RTLIL::Wire *result) + { + + static int cpa_id; + cpa_id++; + + RTLIL::Wire *carry = nullptr; + + log_assert(s_vec.size() == c_vec.size()); + + for (unsigned n = 0; n < s_vec.size(); n++) { + std::string carry_name; + + // Base Case: Bit 0 is sum 0 + if (n == 0) { + std::string buf_name = "base_buf_" + std::to_string(cpa_id) + "_" + std::to_string(n); + auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + buf->setPort(ID::A, s_vec[0]); + buf->setParam(ID::A_WIDTH, 1); + buf->setParam(ID::Y_WIDTH, 1); + buf->setParam(ID::A_SIGNED, false); + buf->setPort(ID::Y, SigSpec(result, 0, 1)); + +#ifdef DEBUG_CPA + printf("CPA bit [%d] Cell %s IP 0 %s \n", n, buf->name.c_str(), s_vec[0]->name.c_str()); +#endif + } + + // + // Base Case + // c,s = ha(s_vec[1],c_vec[0]) + // + else if (n == 1) { + std::string ha_name = "cpa_" + std::to_string(cpa_id) + "_ha_" + std::to_string(n); + RTLIL::Wire *ha_op; + BuildHa(ha_name, s_vec[n], c_vec[n - 1], ha_op, carry); + + connect_sigSpecToWire(ha_op, SigSpec(result, n, 1)); + +#ifdef DEBUG_CPA + printf("CPA bit [%d] Cell %s IPs [%s] [%s] \n", n, ha_cell->name.c_str(), s_vec[n]->name.c_str(), + c_vec[n - 1]->name.c_str()); +#endif + + } + // End Case + else if (n == (unsigned)((s_vec.size() - 1))) { + // Make the carry results.. Two extra bits after fa. + std::string fa_name = "cpa_" + std::to_string(cpa_id) + "_fa_" + std::to_string(n); + auto fa_cell = module->addCell(new_id(fa_name, __LINE__, ""), ID($fa)); + fa_cell->setParam(ID::WIDTH, 1); + carry_name = "cpa_" + std::to_string(cpa_id) + "carry_" + std::to_string(n); + fa_cell->setPort(ID::A, s_vec[n]); + fa_cell->setPort(ID::B, c_vec[n - 1]); + fa_cell->setPort(ID::C, carry); + // wire in result and carry out + fa_cell->setPort(ID::Y, SigSpec(result, n, 1)); + + // make a new carry bit for carry out... + carry = module->addWire(new_id(carry_name, __LINE__, ""), 1); + fa_cell->setPort(ID::X, carry); + +#ifdef DEBUG_CPA + printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.c_str(), s_vec[n]->name.c_str(), + c_vec[n - 1]->name.c_str(), carry->name.c_str()); +#endif + if (n + 1 < (unsigned)(GetSize(result))) { + // Now make a half adder: c_vec[n] = carry + std::string ha_name = "cpa_" + std::to_string(cpa_id) + "_ha_" + std::to_string(n); + RTLIL::Wire *ha_sum; + RTLIL::Wire *ha_carry; + BuildHa(ha_name, c_vec[n], carry, ha_sum, ha_carry); + + if (n + 1 < (unsigned)GetSize(result)) + connect_sigSpecToWire(ha_sum, SigSpec(result, n + 1, 1)); + if (n + 2 < (unsigned)GetSize(result)) + connect_sigSpecToWire(ha_carry, SigSpec(result, n + 2, 1)); + } + } + // Step case + else { + std::string fa_name = "cpa_" + std::to_string(cpa_id) + "_fa_" + std::to_string(n); + auto fa_cell = module->addCell(new_id(fa_name, __LINE__, ""), ID($fa)); + fa_cell->setParam(ID::WIDTH, 1); + + carry_name = "cpa_" + std::to_string(cpa_id) + "carry_" + std::to_string(n); + fa_cell->setPort(ID::A, s_vec[n]); + fa_cell->setPort(ID::B, c_vec[n - 1]); + fa_cell->setPort(ID::C, carry); + // wire in result and carry out + fa_cell->setPort(ID::Y, SigSpec(result, n, 1)); + // make a new carry bit for carry out... + carry = module->addWire(new_id(carry_name, __LINE__, ""), 1); + fa_cell->setPort(ID::X, carry); + +#ifdef DEBUG_CPA + printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.c_str(), s_vec[n]->name.c_str(), + c_vec[n - 1]->name.c_str(), carry->name.c_str()); +#endif + } + } + } + + // Sum the bits in the current column + // Pass the carry bits from each csa to the next + // column for summation. + + void ReduceBits(RTLIL::Module *module, int column_ix, std::vector &column_bits, RTLIL::Wire *&s_result, RTLIL::Wire *&c_result, + std::vector &carry_bits_to_sum, std::vector> &debug_csa_trees) + { + + int csa_ix = 0; + int column_size = column_bits.size(); + static int unique_id = 0; + + unique_id++; + + if (column_size > 0) { + unsigned var_ix = 0; + std::vector first_csa_ips; + // get the first 3 inputs, if possible + for (var_ix = 0; var_ix < column_bits.size() && first_csa_ips.size() != 3; var_ix++) { + if (column_bits[var_ix]) + first_csa_ips.push_back(column_bits[var_ix]); + } + + if (first_csa_ips.size() > 0) { + // build the first csa + std::string csa_name = + "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix) + "_" + std::to_string(unique_id) + "_"; + auto csa = module->addCell(NEW_ID, + // new_id(csa_name, + // __LINE__, + // ""), + ID($fa)); + csa->setParam(ID::WIDTH, 1); + debug_csa_trees[column_ix].push_back(csa); + csa_ix++; + + csa->setPort(ID::A, first_csa_ips[0]); + + if (first_csa_ips.size() > 1) + csa->setPort(ID::B, first_csa_ips[1]); + else + csa->setPort(ID::B, State::S0); + + if (first_csa_ips.size() > 2) + csa->setPort(ID::C, first_csa_ips[2]); + else + csa->setPort(ID::C, State::S0); + + std::string sum_wire_name = "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix) + "_s"; + auto s_wire = module->addWire(new_id(sum_wire_name, __LINE__, ""), 1); + csa->setPort(ID::Y, s_wire); + s_result = s_wire; + std::string carry_wire_name = "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix) + "_c"; + auto c_wire = module->addWire(new_id(carry_wire_name, __LINE__, ""), 1); + csa->setPort(ID::X, c_wire); + c_result = c_wire; + + if (var_ix <= column_bits.size() - 1) + carry_bits_to_sum.push_back(c_wire); + + // Now build the rest of the tree if we can + while (var_ix <= column_bits.size() - 1) { + std::vector csa_ips; + // get the next two variables to sum + for (; var_ix <= column_bits.size() - 1 && csa_ips.size() < 2;) { + // skip any empty bits + if (column_bits[var_ix] != nullptr) + csa_ips.push_back(column_bits[var_ix]); + var_ix++; + } + + if (csa_ips.size() > 0) { + csa_name = "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix); + auto csa = module->addCell(new_id(csa_name, __LINE__, ""), ID($fa)); + csa->setParam(ID::WIDTH, 1); + debug_csa_trees[column_ix].push_back(csa); + + csa_ix++; + // prior level + csa->setPort(ID::A, s_wire); + csa->setPort(ID::B, csa_ips[0]); + if (csa_ips.size() > 1) + csa->setPort(ID::C, csa_ips[1]); + else + csa->setPort(ID::C, State::S0); + + carry_wire_name = "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix) + "_c"; + c_wire = module->addWire(new_id(carry_wire_name, __LINE__, ""), 1); + + if (var_ix <= column_bits.size() - 1) + carry_bits_to_sum.push_back(c_wire); + + sum_wire_name = "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix) + "_s"; + s_wire = module->addWire(new_id(sum_wire_name, __LINE__, ""), 1); + + csa->setPort(ID::X, c_wire); + csa->setPort(ID::Y, s_wire); + + s_result = s_wire; + c_result = c_wire; + } + } + } + } + } + + void BuildBoothUMultEncoders(RTLIL::Wire *Y, int y_sz, std::vector &one_int, std::vector &two_int, + std::vector &s_int, std::vector &sb_int, RTLIL::Module *module, int &encoder_ix) + { + for (int y_ix = 0; y_ix < y_sz;) { + std::string enc_name = "bur_enc_" + std::to_string(encoder_ix) + "_"; + log("Created booth encoder %s\n", enc_name.c_str()); + + std::string two_name = "two_int" + std::to_string(encoder_ix); + two_int.push_back(module->addWire(new_id(two_name, __LINE__, ""), 1)); + + std::string one_name = "one_int" + std::to_string(encoder_ix); + one_int.push_back(module->addWire(new_id(one_name, __LINE__, ""), 1)); + + std::string s_name = "s_int" + std::to_string(encoder_ix); + s_int.push_back(module->addWire(new_id(s_name, __LINE__, ""), 1)); + + std::string sb_name = "sb_int" + std::to_string(encoder_ix); + sb_int.push_back(module->addWire(new_id(sb_name, __LINE__, ""), 1)); + + if (y_ix == 0) { + + BuildBur4e(enc_name, mk_wireFromSigSpec(State::S0), mk_wireFromSigSpec(SigSpec(Y, y_ix, 1)), + mk_wireFromSigSpec(SigSpec(Y, y_ix + 1, 1)), one_int[encoder_ix], two_int[encoder_ix], s_int[encoder_ix], + sb_int[encoder_ix]); + + y_ix = y_ix + 1; + encoder_ix++; + } else { + // + // step case. If multiplier ends on a boundary + // then add an extra booth encoder bounded by + // zeroes to ensure unsigned works. + // + RTLIL::Wire *y0_wire; + RTLIL::Wire *y1_wire; + RTLIL::Wire *y2_wire; + + bool need_padded_cell = false; + + if (y_ix > y_sz - 1) { + y0_wire = mk_wireFromSigSpec(SigSpec(Y, State::S0)); + need_padded_cell = false; + } else { + y0_wire = mk_wireFromSigSpec(SigSpec(Y, y_ix, 1)); + y_ix++; + } + + if (y_ix > y_sz - 1) { + need_padded_cell = false; + y1_wire = mk_wireFromSigSpec(SigSpec(Y, State::S0)); + } else { + y1_wire = mk_wireFromSigSpec(SigSpec(Y, y_ix, 1)); + y_ix++; + } + + if (y_ix > y_sz - 1) { + need_padded_cell = false; + y2_wire = mk_wireFromSigSpec(SigSpec(Y, State::S0)); + } else { + if (y_ix == y_sz - 1) + need_padded_cell = true; + else + need_padded_cell = false; + y2_wire = mk_wireFromSigSpec(SigSpec(Y, y_ix, 1)); + + BuildBur4e(enc_name, y0_wire, y1_wire, y2_wire, one_int[encoder_ix], two_int[encoder_ix], s_int[encoder_ix], + sb_int[encoder_ix]); + } + + encoder_ix++; + + if (need_padded_cell == true) { + + log(" Creating padded encoder for unsigned\n"); + + // make extra encoder cell + // y_ix at y0, rest 0 + + std::string enc_name = "br_enc_pad" + std::to_string(encoder_ix) + "_"; + log("Created (padded) booth encoder %s\n", enc_name.c_str()); + + std::string two_name = "two_int" + std::to_string(encoder_ix); + two_int.push_back(module->addWire(new_id(two_name, __LINE__, ""), 1)); + + std::string one_name = "one_int" + std::to_string(encoder_ix); + one_int.push_back(module->addWire(new_id(two_name, __LINE__, ""), 1)); + + std::string s_name = "s_int" + std::to_string(encoder_ix); + s_int.push_back(module->addWire(new_id(s_name, __LINE__, ""), 1)); + + std::string sb_name = "sb_int" + std::to_string(encoder_ix); + sb_int.push_back(module->addWire(new_id(sb_name, __LINE__, ""), 1)); + + RTLIL::Wire *one_o_int, *two_o_int, *s_o_int, *sb_o_int; + BuildBur4e(enc_name, mk_wireFromSigSpec(SigSpec(Y, y_ix, 1)), mk_wireFromSigSpec(State::S0), + mk_wireFromSigSpec(State::S0), one_o_int, two_o_int, s_o_int, sb_o_int); + + join_wires_with_buffer(one_o_int, one_int[encoder_ix]); + join_wires_with_buffer(two_o_int, two_int[encoder_ix]); + join_wires_with_buffer(s_o_int, s_int[encoder_ix]); + join_wires_with_buffer(sb_o_int, sb_int[encoder_ix]); + y_ix++; + encoder_ix++; + } + } + } + } + + /* + Signed Multiplier + */ + + void CreateBoothSMult(RTLIL::Module *module, int x_sz, int y_sz, int z_sz, RTLIL::Wire *X, RTLIL::Wire *Y, RTLIL::Wire *Z) + { // product + unsigned enc_count = (y_sz / 2) + (((y_sz % 2) != 0) ? 1 : 0); + int dec_count = x_sz + 1; + + int fa_count = x_sz + 4; + int fa_row_count = enc_count - 1; + + log("Signed multiplier generator using low Power Negative First Booth Algorithm. Multiplicand of size %d Multiplier of size %d. " + "Result of size %d. %d encoders %d decoders\n", + x_sz, y_sz, z_sz, enc_count, dec_count); + + RTLIL::Wire *negi_n_int[enc_count]; + RTLIL::Wire *twoi_n_int[enc_count]; + RTLIL::Wire *onei_n_int[enc_count]; + RTLIL::Wire *cori_n_int[enc_count]; + + for (unsigned encoder_ix = 1; encoder_ix <= enc_count; encoder_ix++) { + std::string enc_name = "enc_" + std::to_string(encoder_ix) + "_"; + std::string negi_name = "negi_n_int" + std::to_string(encoder_ix) + "_"; + negi_n_int[encoder_ix - 1] = module->addWire(new_id(negi_name, __LINE__, ""), 1); + std::string twoi_name = "twoi_n_int_" + std::to_string(encoder_ix) + "_"; + twoi_n_int[encoder_ix - 1] = module->addWire(new_id(twoi_name, __LINE__, ""), 1); + std::string onei_name = "onei_n_int_" + std::to_string(encoder_ix) + "_"; + onei_n_int[encoder_ix - 1] = module->addWire(new_id(onei_name, __LINE__, ""), 1); + std::string cori_name = "cori_n_int_" + std::to_string(encoder_ix) + "_"; + cori_n_int[encoder_ix - 1] = module->addWire(new_id(cori_name, __LINE__, ""), 1); + + if (encoder_ix == 1) { + + BuildBr4e(enc_name, mk_wireFromSigSpec(SigSpec(State::S0)), mk_wireFromSigSpec(SigSpec(Y, 0, 1)), + mk_wireFromSigSpec(SigSpec(Y, 1, 1)), + + negi_n_int[encoder_ix - 1], twoi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], + cori_n_int[encoder_ix - 1]); + + } else { + RTLIL::Wire *y1_wire; + RTLIL::Wire *y2_wire; + RTLIL::Wire *y3_wire; + + y1_wire = mk_wireFromSigSpec(SigSpec(Y, ((encoder_ix - 1) * 2 - 1), 1)); //-1 + if ((encoder_ix - 1) * 2 >= (unsigned)y_sz) + y2_wire = mk_wireFromSigSpec(SigSpec(State::S0)); // constant 0 + else + y2_wire = mk_wireFromSigSpec(SigSpec(Y, ((encoder_ix - 1) * 2), 1)); // 0 + + if (((encoder_ix - 1) * 2 + 1) >= (unsigned)y_sz) + y3_wire = mk_wireFromSigSpec(SigSpec(State::S0)); // constant 0 + else + y3_wire = mk_wireFromSigSpec(SigSpec(Y, ((encoder_ix - 1) * 2 + 1), 1)); //+1 + + BuildBr4e(enc_name, y1_wire, y2_wire, y3_wire, + + negi_n_int[encoder_ix - 1], twoi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], + cori_n_int[encoder_ix - 1]); + } + } + // Decoders and PP generation + RTLIL::Wire *PPij[enc_count][dec_count]; + RTLIL::Wire *nxj[enc_count][dec_count]; + for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) { + for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) { + std::string ppij_name = "ppij_" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; + PPij[encoder_ix - 1][decoder_ix - 1] = module->addWire(new_id(ppij_name, __LINE__, ""), 1); + std::string nxj_name; + if (decoder_ix == 1) + nxj_name = "nxj_pre_dec" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; + else + nxj_name = "nxj_" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; + + nxj[encoder_ix - 1][decoder_ix - 1] = module->addWire(new_id(nxj_name, __LINE__, ""), 1); + } + } + + // + // build decoder array + // + + for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) { + // pre-decoder + std::string pre_dec_name = "pre_dec_" + std::to_string(encoder_ix) + "_"; + + if (encoder_ix == 1) { + // quadrant 1 optimization + } else { + auto cell = module->addCell(new_id(pre_dec_name, __LINE__, ""), ID($_NOT_)); + cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + cell->setPort(ID::A, negi_n_int[encoder_ix - 1]); + cell->setPort(ID::Y, nxj[encoder_ix - 1][0]); + } + + for (int decoder_ix = 1; decoder_ix < dec_count; decoder_ix++) { + // range 1..8 + + // quadrant 1 optimization. + if ((decoder_ix == 1 || decoder_ix == 2) && encoder_ix == 1) + continue; + + std::string dec_name = "dec_" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; + + BuildBr4d(dec_name, nxj[encoder_ix - 1][decoder_ix - 1], twoi_n_int[encoder_ix - 1], + mk_wireFromSigSpec(SigSpec(X, decoder_ix - 1, 1)), negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], + PPij[encoder_ix - 1][decoder_ix - 1], nxj[encoder_ix - 1][decoder_ix]); + } + + // duplicate end for sign fix + // applies to 9th decoder (xsz+1 decoder). + std::string dec_name = "dec_" + std::to_string(encoder_ix) + "_" + std::to_string(x_sz + 1) + "_"; + RTLIL::Wire *unused_op = nullptr; + BuildBr4d(dec_name, nxj[encoder_ix - 1][dec_count - 1], twoi_n_int[encoder_ix - 1], + mk_wireFromSigSpec(SigSpec(X, dec_count - 2, 1)), negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], + PPij[encoder_ix - 1][dec_count - 1], unused_op); + } + + // + // sum up the partial products + // + int fa_el_ix = 0; + int fa_row_ix = 0; + RTLIL::Wire *fa_sum_n[fa_row_count][fa_count]; + RTLIL::Wire *fa_carry_n[fa_row_count][fa_count]; + + for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) { + for (fa_el_ix = 0; fa_el_ix < fa_count; fa_el_ix++) { + + std::string fa_sum_name = "fa_sum_n_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_"; + fa_sum_n[fa_row_ix][fa_el_ix] = module->addWire(new_id(fa_sum_name, __LINE__, ""), 1); + std::string fa_carry_name = "fa_carry_n" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_"; + fa_carry_n[fa_row_ix][fa_el_ix] = module->addWire(new_id(fa_carry_name, __LINE__, ""), 1); + } + } + + // full adder creation + std::string bfa_name; + std::string exc_inv_name; + for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) { + for (fa_el_ix = 0; fa_el_ix < fa_count; fa_el_ix++) { + // base case: 1st row. Inputs from decoders + // Note in rest of tree inputs from prior addition and a decoder + if (fa_row_ix == 0) { + // beginning + // base case: + // first two cells: have B input hooked to 0. + if (fa_el_ix == 0) { + // quadrant 1: we hard code these using non-booth + fa_el_ix++; + + } + // step case + else if (fa_el_ix >= 2 && fa_el_ix <= x_sz) { + // middle (2...x_sz cells) + bfa_name = "bfa_0_step_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; + auto cell = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); + cell->setParam(ID::WIDTH, 1); + cell->setPort(ID::A, PPij[0][fa_el_ix]); + cell->setPort(ID::B, PPij[1][fa_el_ix - 2]); + cell->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); + cell->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); + cell->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + } + // end 3 cells: x_sz+1.2.3 + // + else { + // fa_el_ix = x_sz+1 + bfa_name = "bfa_0_se_0" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; + auto cell1 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); + cell1->setParam(ID::WIDTH, 1); + cell1->setPort(ID::A, PPij[0][x_sz]); + cell1->setPort(ID::B, PPij[1][fa_el_ix - 2]); + cell1->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); + cell1->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); + cell1->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + + // exception:invert ppi + fa_el_ix++; + exc_inv_name = "bfa_0_exc_inv1_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; + auto cellinv1 = module->addCell(new_id(exc_inv_name, __LINE__, ""), ID($_NOT_)); + cellinv1->add_strpool_attribute(ID::src, cellinv1->get_strpool_attribute(ID::src)); + + RTLIL::Wire *d08_inv = module->addWire(NEW_ID, 1); + + cellinv1->setPort(ID::A, PPij[0][dec_count - 1]); + cellinv1->setPort(ID::Y, d08_inv); + + exc_inv_name = "bfa_0_exc_inv2_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; + + auto cellinv2 = module->addCell(new_id(exc_inv_name, __LINE__, ""), ID($_NOT_)); + cellinv2->add_strpool_attribute(ID::src, cellinv2->get_strpool_attribute(ID::src)); + RTLIL::Wire *d18_inv = module->addWire(NEW_ID, 1); + cellinv2->setPort(ID::A, PPij[1][dec_count - 1]); + cellinv2->setPort(ID::Y, d18_inv); + + bfa_name = "bfa_0_se_1_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; + + auto cell2 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); + cell2->setParam(ID::WIDTH, 1); + cell2->setPort(ID::A, d08_inv); + cell2->setPort(ID::B, d18_inv); + cell2->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); + cell2->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); + cell2->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + + // sign extension + fa_el_ix++; + bfa_name = "bfa_0_se_2_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; + auto cell3 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); + cell3->setParam(ID::WIDTH, 1); + cell3->setPort(ID::A, State::S0); + cell3->setPort(ID::B, State::S1); + cell3->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); + cell3->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); + cell3->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + } + } + + // step case: 2nd and rest of rows. (fa_row_ix == 1...n) + // special because these are driven by a decoder and prior fa. + else { + // beginning + if (fa_el_ix == 0) { + // first two cells: have B input hooked to 0. + // column is offset by row_ix*2 + bfa_name = "bfa_" + std::to_string(fa_row_ix) + "_base_" + std::to_string(fa_row_ix) + "_" + + std::to_string(fa_el_ix) + "_L"; + auto cell1 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); + cell1->setParam(ID::WIDTH, 1); + cell1->setPort(ID::A, fa_sum_n[fa_row_ix - 1][2]); // from prior full adder row + cell1->setPort(ID::B, State::S0); + cell1->setPort(ID::C, cori_n_int[fa_row_ix]); + cell1->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); + cell1->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + fa_el_ix++; + + bfa_name = "bfa_" + std::to_string(fa_row_ix) + "_base_" + std::to_string(fa_row_ix) + "_" + + std::to_string(fa_el_ix) + "_L"; + auto cell2 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); + cell2->setParam(ID::WIDTH, 1); + cell2->setPort(ID::A, fa_sum_n[fa_row_ix - 1][3]); // from prior full adder row + cell2->setPort(ID::B, State::S0); + cell2->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); + cell2->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); + cell2->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + } + + else if (fa_el_ix >= 2 && fa_el_ix <= x_sz + 1) { + // middle (2...x_sz+1 cells) + bfa_name = "bfa_" + std::to_string(fa_row_ix) + "_step_" + std::to_string(fa_row_ix) + "_" + + std::to_string(fa_el_ix) + "_L"; + auto cell = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); + cell->setParam(ID::WIDTH, 1); + cell->setPort(ID::A, fa_sum_n[fa_row_ix - 1][fa_el_ix + 2]); + cell->setPort(ID::B, PPij[fa_row_ix + 1][fa_el_ix - 2]); + cell->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); + cell->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); + cell->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + } + + else if (fa_el_ix > x_sz + 1) { + // end two bits: sign extension + std::string se_inv_name; + se_inv_name = "bfa_" + std::to_string(fa_row_ix) + "_se_inv_" + std::to_string(fa_row_ix) + "_" + + std::to_string(fa_el_ix) + "_L"; + auto cellinv = module->addCell(new_id(se_inv_name, __LINE__, ""), ID($_NOT_)); + cellinv->add_strpool_attribute(ID::src, cellinv->get_strpool_attribute(ID::src)); + RTLIL::Wire *d_inv = module->addWire(NEW_ID, 1); + cellinv->setPort(ID::A, PPij[fa_row_ix + 1][dec_count - 1]); + cellinv->setPort(ID::Y, d_inv); + + bfa_name = "bfa_" + std::to_string(fa_row_ix) + "_se_" + std::to_string(fa_row_ix) + "_" + + std::to_string(fa_el_ix) + "_L"; + auto cell1 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); + cell1->setParam(ID::WIDTH, 1); + cell1->setPort(ID::A, fa_carry_n[fa_row_ix - 1][fa_count - 1]); + cell1->setPort(ID::B, d_inv); + cell1->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); + cell1->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); + cell1->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + fa_el_ix++; + + // sign extension + bfa_name = "bfa_" + std::to_string(fa_row_ix) + "_se_" + std::to_string(fa_row_ix) + "_" + + std::to_string(fa_el_ix) + "_L"; + auto cell2 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); + cell2->setParam(ID::WIDTH, 1); + cell2->setPort(ID::A, State::S0); + cell2->setPort(ID::B, State::S1); + cell2->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); + cell2->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); + cell2->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + } + } + } + } + + // instantiate the cpa + RTLIL::Wire *cpa_carry[z_sz]; + + if (x_sz + y_sz != z_sz) + log("Result of multiplier is incomplete with respect to domain of inputs\n"); + + for (int cix = 0; cix < z_sz; cix++) { + std::string cpa_cix_name = "cpa_carry_" + std::to_string(cix) + "_"; + cpa_carry[cix] = module->addWire(new_id(cpa_cix_name, __LINE__, ""), 1); + } + log(" Building cpa array for booth\n"); + for (int cpa_ix = 0; cpa_ix < z_sz; cpa_ix++) { + + // The end case where we pass the last two summands + // from prior row directly to product output + // without using a cpa cell. This is always + // 0,1 index of prior fa row + if (cpa_ix <= fa_row_count * 2 - 1) { + int fa_row_ix = cpa_ix / 2; + + std::string buf_name = + "pp_buf_" + std::to_string(cpa_ix) + "_" + "driven_by_fa_row_" + std::to_string(fa_row_ix) + "_"; + auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + buf->setPort(ID::A, fa_sum_n[fa_row_ix][0]); + buf->setParam(ID::A_WIDTH, 1); + buf->setParam(ID::Y_WIDTH, 1); + buf->setParam(ID::A_SIGNED, true); + buf->setPort(ID::Y, SigSpec(Z, cpa_ix, 1)); + + cpa_ix++; + buf_name = "pp_buf_" + std::to_string(cpa_ix) + "_" + "driven_by_fa_row_" + std::to_string(fa_row_ix) + "_"; + buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + buf->setPort(ID::A, fa_sum_n[fa_row_ix][1]); + buf->setParam(ID::A_WIDTH, 1); + buf->setParam(ID::Y_WIDTH, 1); + buf->setParam(ID::A_SIGNED, true); + buf->setPort(ID::Y, SigSpec(Z, cpa_ix, 1)); + } else { + int offset = fa_row_count * 2; + bool base_case = cpa_ix - offset == 0 ? true : false; + std::string cpa_name = "cpa_" + std::to_string(cpa_ix - offset) + "_"; + + RTLIL::Wire *ci_wire; + if (base_case) + ci_wire = cori_n_int[enc_count - 1]; + else + ci_wire = cpa_carry[cpa_ix - offset - 1]; + + RTLIL::Wire *op_wire = module->addWire(NEW_ID, 1); + BuildHa(cpa_name, fa_sum_n[fa_row_count - 1][cpa_ix - offset + 2], ci_wire, op_wire, cpa_carry[cpa_ix - offset]); + connect_sigSpecToWire(op_wire, SigSpec(Z, cpa_ix, 1)); + } + } + + // + // instantiate the quadrant 1 cell. This is the upper right + // quadrant which can be realized using non-booth encoded logic. + // + std::string q1_name = "icb_booth_q1_"; + + RTLIL::Wire *pp0_o_int; + RTLIL::Wire *pp1_o_int; + RTLIL::Wire *nxj_o_int; + RTLIL::Wire *cor_o_int; + + BuildBoothQ1(q1_name, + negi_n_int[0], // negi + cori_n_int[0], // cori + + mk_wireFromSigSpec(SigSpec(X, 0, 1)), // x0 + mk_wireFromSigSpec(SigSpec(X, 1, 1)), // x1 + mk_wireFromSigSpec(SigSpec(Y, 0, 1)), // y0 + mk_wireFromSigSpec(SigSpec(Y, 1, 1)), // y1 + + nxj_o_int, cor_o_int, pp0_o_int, pp1_o_int); + + join_wires_with_buffer(pp0_o_int, fa_sum_n[0][0]); + join_wires_with_buffer(pp1_o_int, fa_sum_n[0][1]); + join_wires_with_buffer(cor_o_int, fa_carry_n[0][1]); + join_wires_with_buffer(nxj_o_int, nxj[0][2]); + } +}; + +struct MultPass : public Pass { + MultPass() : Pass("multpass") {} + void execute(vector args, RTLIL::Design *design) override + { + (void)args; + log("Multiplier Pass. Generating Booth Multiplier structures for signed/unsigned multipliers of 4 bits or more\n"); + for (auto mod : design->selected_modules()) + if (!mod->has_processes_warn()) { + MultPassWorker worker(mod); + worker.run(); + } + } +} MultPass; + +PRIVATE_NAMESPACE_END From 0c2a99ca475dfc912ccc211afb1264a7e8fb8247 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 7 Sep 2023 14:46:59 +0200 Subject: [PATCH 003/240] techmap: Test the Booth multiplier --- tests/techmap/booth.ys | 1 + tests/techmap/booth_map_script.ys_ | 1 + 2 files changed, 2 insertions(+) create mode 100644 tests/techmap/booth.ys create mode 100644 tests/techmap/booth_map_script.ys_ diff --git a/tests/techmap/booth.ys b/tests/techmap/booth.ys new file mode 100644 index 00000000000..17e20245693 --- /dev/null +++ b/tests/techmap/booth.ys @@ -0,0 +1 @@ +test_cell -script booth_map_script.ys_ $mul diff --git a/tests/techmap/booth_map_script.ys_ b/tests/techmap/booth_map_script.ys_ new file mode 100644 index 00000000000..0f323bdd863 --- /dev/null +++ b/tests/techmap/booth_map_script.ys_ @@ -0,0 +1 @@ +multpass From 25a33d408280ba496366ef282506521a4caef305 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 7 Sep 2023 14:56:56 +0200 Subject: [PATCH 004/240] techmap: Make the Booth test deterministic --- tests/techmap/booth.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/techmap/booth.ys b/tests/techmap/booth.ys index 17e20245693..f1dce1f3b27 100644 --- a/tests/techmap/booth.ys +++ b/tests/techmap/booth.ys @@ -1 +1 @@ -test_cell -script booth_map_script.ys_ $mul +test_cell -s 1694091355 -n 1000 -script booth_map_script.ys_ $mul From 411acc4a0a27a6b3cb198faa63f6e501a1b8df19 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Fri, 8 Sep 2023 13:41:31 -0700 Subject: [PATCH 005/240] Fixed edge size cases for signed/unsigned booth generator --- passes/techmap/multpass.cc | 195 +++++++++++++++++++++++++------------ 1 file changed, 135 insertions(+), 60 deletions(-) diff --git a/passes/techmap/multpass.cc b/passes/techmap/multpass.cc index e55a0441448..9981250ae08 100644 --- a/passes/techmap/multpass.cc +++ b/passes/techmap/multpass.cc @@ -295,45 +295,85 @@ struct MultPassWorker { int y_sz = GetSize(B); int z_sz = GetSize(Y); - // create a buffer for each ip - std::string buf_name = "u_mult_multiplicand_buf_"; - auto A_Buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - A_Buf->setParam(ID::A_WIDTH, x_sz); - A_Buf->setParam(ID::Y_WIDTH, x_sz); - A_Buf->setPort(ID::A, SigSpec(A)); - A_Buf->setParam(ID::A_SIGNED, false); - - std::string wire_name = "u_mult_A"; - auto A_Wire = module->addWire(new_id(wire_name, __LINE__, ""), x_sz); - - A_Buf->setPort(ID::Y, A_Wire); - - buf_name = "u_mult_multiplier_buf_"; - auto B_Buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - B_Buf->setParam(ID::A_WIDTH, y_sz); - B_Buf->setParam(ID::Y_WIDTH, y_sz); - B_Buf->setPort(ID::A, SigSpec(B)); - B_Buf->setParam(ID::A_SIGNED, false); - - wire_name = "u_mult_B"; - auto B_Wire = module->addWire(new_id(wire_name, __LINE__, ""), y_sz); - B_Buf->setPort(ID::Y, B_Wire); - - buf_name = "u_mult_result_buf_"; - auto Z_Buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - Z_Buf->setParam(ID::A_WIDTH, z_sz); - Z_Buf->setParam(ID::Y_WIDTH, z_sz); - Z_Buf->setPort(ID::Y, SigSpec(Y)); - Z_Buf->setParam(ID::A_SIGNED, false); - wire_name = "u_mult_Z"; - auto Z_Wire = module->addWire(new_id(wire_name, __LINE__, ""), z_sz); - Z_Buf->setPort(ID::A, Z_Wire); - - CreateBoothUMult(module, x_sz, y_sz, z_sz, - A_Wire, // multiplicand - B_Wire, // multiplier(scanned) - Z_Wire // result + // To simplify the generator size the arguments + // to be the same. Then allow logic synthesis to + // clean things up. Size to biggest + + int x_sz_revised = x_sz; + int y_sz_revised = y_sz; + + if (x_sz != y_sz) { + if (x_sz < y_sz) { + if (y_sz % 2 != 0) { + x_sz_revised = y_sz + 1; + y_sz_revised = y_sz + 1; + } else + x_sz_revised = y_sz; + + log("Resized x to %d ", x_sz_revised); + } else { + if (x_sz % 2 != 0) { + y_sz_revised = x_sz + 1; + x_sz_revised = x_sz + 1; + } else + y_sz_revised = x_sz; + log("Resized y to %d ", y_sz_revised); + } + } else { + if (x_sz % 2 != 0) { + y_sz_revised = y_sz + 1; + x_sz_revised = x_sz + 1; + } + } + + log_assert((x_sz_revised == y_sz_revised) && (x_sz_revised % 2 == 0) && (y_sz_revised % 2 == 0)); + + Wire *expanded_A = module->addWire(NEW_ID, x_sz_revised); + Wire *expanded_B = module->addWire(NEW_ID, y_sz_revised); + + std::string buf_name = "expand_a_buf_"; + auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + buf->setParam(ID::A_WIDTH, x_sz); + buf->setParam(ID::Y_WIDTH, x_sz_revised); + buf->setPort(ID::A, SigSpec(A)); + buf->setParam(ID::A_SIGNED, false); + buf->setPort(ID::Y, SigSpec(expanded_A)); + + buf_name = "expand_b_buf_"; + buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + buf->setPort(ID::A, SigSpec(B)); + buf->setParam(ID::A_WIDTH, y_sz); + buf->setParam(ID::Y_WIDTH, y_sz_revised); + buf->setParam(ID::A_SIGNED, false); + buf->setPort(ID::Y, SigSpec(expanded_B)); + + // Make sure output domain is big enough to take + // all combinations. + // Later logic synthesis will kill unused + // portions of the output domain. + + unsigned required_op_size = x_sz_revised + y_sz_revised; + + Wire *expanded_Y = module->addWire(NEW_ID, required_op_size); + + CreateBoothUMult(module, x_sz_revised, y_sz_revised, required_op_size, + expanded_A, // multiplicand + expanded_B, // multiplier(scanned) + expanded_Y // result ); + + // now connect the expanded_Y with a tap to fill out sig Spec Y + + log("Adding reducer on output from %u to %u ", required_op_size, z_sz); + buf_name = "reducer_buf_"; + buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + buf->setPort(ID::A, expanded_Y); + buf->setParam(ID::A_WIDTH, required_op_size); + buf->setParam(ID::Y_WIDTH, z_sz); // The real user width + buf->setParam(ID::A_SIGNED, false); + // wire in output Y + buf->setPort(ID::Y, SigSpec(Y)); + module->remove(cell); booth_counter++; continue; @@ -344,47 +384,81 @@ struct MultPassWorker { int y_sz = GetSize(B); int z_sz = GetSize(Y); - // make wire of correct size to feed multiplier - Wire *expanded_A = module->addWire(NEW_ID, x_sz); - - Wire *expanded_B = module->addWire(NEW_ID, y_sz); + // To simplify the generator size the arguments + // to be the same. Then allow logic synthesis to + // clean things up. Size to biggest + + int x_sz_revised = x_sz; + int y_sz_revised = y_sz; + + if (x_sz != y_sz) { + if (x_sz < y_sz) { + if (y_sz % 2 != 0) { + x_sz_revised = y_sz + 1; + y_sz_revised = y_sz + 1; + } else + x_sz_revised = y_sz; + + log("Resized x to %d ", x_sz_revised); + } else { + if (x_sz % 2 != 0) { + y_sz_revised = x_sz + 1; + x_sz_revised = x_sz + 1; + } else + y_sz_revised = x_sz; + log("Resized y to %d ", y_sz_revised); + } + } else { + if (x_sz % 2 != 0) { + y_sz_revised = y_sz + 1; + x_sz_revised = x_sz + 1; + } + } + + log_assert((x_sz_revised == y_sz_revised) && (x_sz_revised % 2 == 0) && (y_sz_revised % 2 == 0)); + + Wire *expanded_A = module->addWire(NEW_ID, x_sz_revised); + Wire *expanded_B = module->addWire(NEW_ID, y_sz_revised); std::string buf_name = "expand_a_buf_"; auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); buf->setParam(ID::A_WIDTH, x_sz); - buf->setParam(ID::Y_WIDTH, x_sz); + buf->setParam(ID::Y_WIDTH, x_sz_revised); buf->setPort(ID::A, SigSpec(A)); - buf->setParam(ID::A_SIGNED, is_signed ? true : false); + buf->setParam(ID::A_SIGNED, true); buf->setPort(ID::Y, SigSpec(expanded_A)); buf_name = "expand_b_buf_"; buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); buf->setPort(ID::A, SigSpec(B)); buf->setParam(ID::A_WIDTH, y_sz); - buf->setParam(ID::Y_WIDTH, y_sz); - - buf->setParam(ID::A_SIGNED, is_signed ? true : false); + buf->setParam(ID::Y_WIDTH, y_sz_revised); + buf->setParam(ID::A_SIGNED, true); buf->setPort(ID::Y, SigSpec(expanded_B)); - // - // Make a wire to take the expanded output - // wires - // + // Make sure output domain is big enough to take + // all combinations. + // Later logic synthesis will kill unused + // portions of the output domain. + + unsigned required_op_size = x_sz_revised + y_sz_revised; - Wire *expanded_Y = module->addWire(NEW_ID, (is_signed == false ? z_sz + 2 : z_sz)); - CreateBoothSMult(module, x_sz, y_sz, (is_signed == false ? z_sz + 2 : z_sz), + Wire *expanded_Y = module->addWire(NEW_ID, required_op_size); + + CreateBoothSMult(module, x_sz_revised, y_sz_revised, required_op_size, expanded_A, // multiplicand expanded_B, // multiplier(scanned) - expanded_Y // result + expanded_Y // result (sized) ); // now connect the expanded_Y with a tap to fill out sig Spec Y + log("Adding reducer on output from %u to %u ", required_op_size, z_sz); buf_name = "reducer_buf_"; buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); buf->setPort(ID::A, expanded_Y); - buf->setParam(ID::A_WIDTH, is_signed == false ? z_sz + 2 : z_sz); - buf->setParam(ID::Y_WIDTH, z_sz); - buf->setParam(ID::A_SIGNED, is_signed ? true : false); + buf->setParam(ID::A_WIDTH, required_op_size); + buf->setParam(ID::Y_WIDTH, z_sz); // The real user width + buf->setParam(ID::A_SIGNED, true); // wire in output Y buf->setPort(ID::Y, SigSpec(Y)); @@ -1451,7 +1525,7 @@ struct MultPassWorker { std::string cpa_cix_name = "cpa_carry_" + std::to_string(cix) + "_"; cpa_carry[cix] = module->addWire(new_id(cpa_cix_name, __LINE__, ""), 1); } - log(" Building cpa array for booth\n"); + log(" Building cpa array for booth for output size %u\n", z_sz); for (int cpa_ix = 0; cpa_ix < z_sz; cpa_ix++) { // The end case where we pass the last two summands @@ -1525,15 +1599,16 @@ struct MultPassWorker { }; struct MultPass : public Pass { - MultPass() : Pass("multpass") {} + MultPass() : Pass("multpass", "Map $mul to booth multipliers") {} void execute(vector args, RTLIL::Design *design) override { (void)args; - log("Multiplier Pass. Generating Booth Multiplier structures for signed/unsigned multipliers of 4 bits or more\n"); + log_header(design, "Executing multpass. Generating Booth Multiplier structures for signed/unsigned multipliers of 4 bits or more\n"); for (auto mod : design->selected_modules()) if (!mod->has_processes_warn()) { MultPassWorker worker(mod); worker.run(); + log_header(design, "Created %d booth multipliers.\n", worker.booth_counter); } } } MultPass; From 6d29dc659b19a016d33f75561c6f2dd96b42ca8f Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Fri, 8 Sep 2023 15:34:56 -0700 Subject: [PATCH 006/240] renamed passname to booth, replaced connect_sigSpecToWire with connect, updated test script --- passes/techmap/multpass.cc | 264 +++++++++-------------------- tests/techmap/booth_map_script.ys_ | 2 +- 2 files changed, 78 insertions(+), 188 deletions(-) diff --git a/passes/techmap/multpass.cc b/passes/techmap/multpass.cc index 9981250ae08..c0e56f2ad61 100644 --- a/passes/techmap/multpass.cc +++ b/passes/techmap/multpass.cc @@ -64,16 +64,6 @@ struct MultPassWorker { // Helper routines for building architecture subcomponents - void connect_sigSpecToWire(RTLIL::Wire *ip, const SigSpec &v) - { - auto g = module->addCell(NEW_ID, ID($pos)); - g->setParam(ID::A_WIDTH, 1); - g->setParam(ID::Y_WIDTH, 1); - g->setParam(ID::A_SIGNED, false); - g->setPort(ID::A, ip); - g->setPort(ID::Y, v); - } - RTLIL::Wire *mk_wireFromSigSpec(const SigSpec &v) { @@ -274,7 +264,6 @@ struct MultPassWorker { void run() { - log("Extracting $mul cells in module %s and generating Booth Realization:\n", log_id(module)); for (auto cell : module->selected_cells()) { if (cell->type.in(ID($mul))) { RTLIL::SigSpec A = sigmap(cell->getPort(ID::A)); @@ -290,183 +279,92 @@ struct MultPassWorker { } else log(" By passing macc inferencing for unsigned multiplier -- generating booth\n"); - if (is_signed == false) /* unsigned multiplier */ { - int x_sz = GetSize(A); - int y_sz = GetSize(B); - int z_sz = GetSize(Y); - - // To simplify the generator size the arguments - // to be the same. Then allow logic synthesis to - // clean things up. Size to biggest - - int x_sz_revised = x_sz; - int y_sz_revised = y_sz; - - if (x_sz != y_sz) { - if (x_sz < y_sz) { - if (y_sz % 2 != 0) { - x_sz_revised = y_sz + 1; - y_sz_revised = y_sz + 1; - } else - x_sz_revised = y_sz; - - log("Resized x to %d ", x_sz_revised); - } else { - if (x_sz % 2 != 0) { - y_sz_revised = x_sz + 1; - x_sz_revised = x_sz + 1; - } else - y_sz_revised = x_sz; - log("Resized y to %d ", y_sz_revised); - } - } else { - if (x_sz % 2 != 0) { - y_sz_revised = y_sz + 1; - x_sz_revised = x_sz + 1; - } - } - - log_assert((x_sz_revised == y_sz_revised) && (x_sz_revised % 2 == 0) && (y_sz_revised % 2 == 0)); - - Wire *expanded_A = module->addWire(NEW_ID, x_sz_revised); - Wire *expanded_B = module->addWire(NEW_ID, y_sz_revised); + int x_sz = GetSize(A); + int y_sz = GetSize(B); + int z_sz = GetSize(Y); - std::string buf_name = "expand_a_buf_"; - auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setParam(ID::A_WIDTH, x_sz); - buf->setParam(ID::Y_WIDTH, x_sz_revised); - buf->setPort(ID::A, SigSpec(A)); - buf->setParam(ID::A_SIGNED, false); - buf->setPort(ID::Y, SigSpec(expanded_A)); + // To simplify the generator size the arguments + // to be the same. Then allow logic synthesis to + // clean things up. Size to biggest - buf_name = "expand_b_buf_"; - buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setPort(ID::A, SigSpec(B)); - buf->setParam(ID::A_WIDTH, y_sz); - buf->setParam(ID::Y_WIDTH, y_sz_revised); - buf->setParam(ID::A_SIGNED, false); - buf->setPort(ID::Y, SigSpec(expanded_B)); + int x_sz_revised = x_sz; + int y_sz_revised = y_sz; - // Make sure output domain is big enough to take - // all combinations. - // Later logic synthesis will kill unused - // portions of the output domain. - - unsigned required_op_size = x_sz_revised + y_sz_revised; + if (x_sz != y_sz) { + if (x_sz < y_sz) { + if (y_sz % 2 != 0) { + x_sz_revised = y_sz + 1; + y_sz_revised = y_sz + 1; + } else + x_sz_revised = y_sz; - Wire *expanded_Y = module->addWire(NEW_ID, required_op_size); + } else { + if (x_sz % 2 != 0) { + y_sz_revised = x_sz + 1; + x_sz_revised = x_sz + 1; + } else + y_sz_revised = x_sz; + } + } else { + if (x_sz % 2 != 0) { + y_sz_revised = y_sz + 1; + x_sz_revised = x_sz + 1; + } + } + log_assert((x_sz_revised == y_sz_revised) && (x_sz_revised % 2 == 0) && (y_sz_revised % 2 == 0)); + + Wire *expanded_A = module->addWire(NEW_ID, x_sz_revised); + Wire *expanded_B = module->addWire(NEW_ID, y_sz_revised); + + std::string buf_name = "expand_a_buf_"; + auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + buf->setParam(ID::A_WIDTH, x_sz); + buf->setParam(ID::Y_WIDTH, x_sz_revised); + buf->setPort(ID::A, SigSpec(A)); + buf->setParam(ID::A_SIGNED, is_signed ? true : false); + buf->setPort(ID::Y, SigSpec(expanded_A)); + + buf_name = "expand_b_buf_"; + buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + buf->setPort(ID::A, SigSpec(B)); + buf->setParam(ID::A_WIDTH, y_sz); + buf->setParam(ID::Y_WIDTH, y_sz_revised); + buf->setParam(ID::A_SIGNED, is_signed ? true : false); + buf->setPort(ID::Y, SigSpec(expanded_B)); + + // Make sure output domain is big enough to take + // all combinations. + // Later logic synthesis will kill unused + // portions of the output domain. + + unsigned required_op_size = x_sz_revised + y_sz_revised; + Wire *expanded_Y = module->addWire(NEW_ID, required_op_size); + // now connect the expanded_Y with a tap to fill out sig Spec Y + buf_name = "reducer_buf_"; + buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); + buf->setPort(ID::A, expanded_Y); + buf->setParam(ID::A_WIDTH, required_op_size); + buf->setParam(ID::Y_WIDTH, z_sz); // The real user width + buf->setParam(ID::A_SIGNED, is_signed ? true : false); + // wire in output Y + buf->setPort(ID::Y, SigSpec(Y)); + + if (is_signed == false) /* unsigned multiplier */ CreateBoothUMult(module, x_sz_revised, y_sz_revised, required_op_size, expanded_A, // multiplicand expanded_B, // multiplier(scanned) expanded_Y // result ); - - // now connect the expanded_Y with a tap to fill out sig Spec Y - - log("Adding reducer on output from %u to %u ", required_op_size, z_sz); - buf_name = "reducer_buf_"; - buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setPort(ID::A, expanded_Y); - buf->setParam(ID::A_WIDTH, required_op_size); - buf->setParam(ID::Y_WIDTH, z_sz); // The real user width - buf->setParam(ID::A_SIGNED, false); - // wire in output Y - buf->setPort(ID::Y, SigSpec(Y)); - - module->remove(cell); - booth_counter++; - continue; - } - - else /*signed multiplier */ { - int x_sz = GetSize(A); - int y_sz = GetSize(B); - int z_sz = GetSize(Y); - - // To simplify the generator size the arguments - // to be the same. Then allow logic synthesis to - // clean things up. Size to biggest - - int x_sz_revised = x_sz; - int y_sz_revised = y_sz; - - if (x_sz != y_sz) { - if (x_sz < y_sz) { - if (y_sz % 2 != 0) { - x_sz_revised = y_sz + 1; - y_sz_revised = y_sz + 1; - } else - x_sz_revised = y_sz; - - log("Resized x to %d ", x_sz_revised); - } else { - if (x_sz % 2 != 0) { - y_sz_revised = x_sz + 1; - x_sz_revised = x_sz + 1; - } else - y_sz_revised = x_sz; - log("Resized y to %d ", y_sz_revised); - } - } else { - if (x_sz % 2 != 0) { - y_sz_revised = y_sz + 1; - x_sz_revised = x_sz + 1; - } - } - - log_assert((x_sz_revised == y_sz_revised) && (x_sz_revised % 2 == 0) && (y_sz_revised % 2 == 0)); - - Wire *expanded_A = module->addWire(NEW_ID, x_sz_revised); - Wire *expanded_B = module->addWire(NEW_ID, y_sz_revised); - - std::string buf_name = "expand_a_buf_"; - auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setParam(ID::A_WIDTH, x_sz); - buf->setParam(ID::Y_WIDTH, x_sz_revised); - buf->setPort(ID::A, SigSpec(A)); - buf->setParam(ID::A_SIGNED, true); - buf->setPort(ID::Y, SigSpec(expanded_A)); - - buf_name = "expand_b_buf_"; - buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setPort(ID::A, SigSpec(B)); - buf->setParam(ID::A_WIDTH, y_sz); - buf->setParam(ID::Y_WIDTH, y_sz_revised); - buf->setParam(ID::A_SIGNED, true); - buf->setPort(ID::Y, SigSpec(expanded_B)); - - // Make sure output domain is big enough to take - // all combinations. - // Later logic synthesis will kill unused - // portions of the output domain. - - unsigned required_op_size = x_sz_revised + y_sz_revised; - - Wire *expanded_Y = module->addWire(NEW_ID, required_op_size); - + else /*signed multiplier */ CreateBoothSMult(module, x_sz_revised, y_sz_revised, required_op_size, expanded_A, // multiplicand expanded_B, // multiplier(scanned) expanded_Y // result (sized) ); - // now connect the expanded_Y with a tap to fill out sig Spec Y - - log("Adding reducer on output from %u to %u ", required_op_size, z_sz); - buf_name = "reducer_buf_"; - buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setPort(ID::A, expanded_Y); - buf->setParam(ID::A_WIDTH, required_op_size); - buf->setParam(ID::Y_WIDTH, z_sz); // The real user width - buf->setParam(ID::A_SIGNED, true); - // wire in output Y - buf->setPort(ID::Y, SigSpec(Y)); - - // kill original multiplier - module->remove(cell); - booth_counter++; - continue; - } + module->remove(cell); + booth_counter++; + continue; } } } @@ -936,7 +834,7 @@ struct MultPassWorker { RTLIL::Wire *ha_op; BuildHa(ha_name, s_vec[n], c_vec[n - 1], ha_op, carry); - connect_sigSpecToWire(ha_op, SigSpec(result, n, 1)); + module->connect(ha_op, SigSpec(result, n, 1)); #ifdef DEBUG_CPA printf("CPA bit [%d] Cell %s IPs [%s] [%s] \n", n, ha_cell->name.c_str(), s_vec[n]->name.c_str(), @@ -971,11 +869,10 @@ struct MultPassWorker { RTLIL::Wire *ha_sum; RTLIL::Wire *ha_carry; BuildHa(ha_name, c_vec[n], carry, ha_sum, ha_carry); - if (n + 1 < (unsigned)GetSize(result)) - connect_sigSpecToWire(ha_sum, SigSpec(result, n + 1, 1)); + module->connect(ha_sum, SigSpec(result, n + 1, 1)); if (n + 2 < (unsigned)GetSize(result)) - connect_sigSpecToWire(ha_carry, SigSpec(result, n + 2, 1)); + module->connect(ha_carry, SigSpec(result, n + 2, 1)); } } // Step case @@ -1113,7 +1010,6 @@ struct MultPassWorker { { for (int y_ix = 0; y_ix < y_sz;) { std::string enc_name = "bur_enc_" + std::to_string(encoder_ix) + "_"; - log("Created booth encoder %s\n", enc_name.c_str()); std::string two_name = "two_int" + std::to_string(encoder_ix); two_int.push_back(module->addWire(new_id(two_name, __LINE__, ""), 1)); @@ -1181,13 +1077,10 @@ struct MultPassWorker { if (need_padded_cell == true) { - log(" Creating padded encoder for unsigned\n"); - // make extra encoder cell // y_ix at y0, rest 0 std::string enc_name = "br_enc_pad" + std::to_string(encoder_ix) + "_"; - log("Created (padded) booth encoder %s\n", enc_name.c_str()); std::string two_name = "two_int" + std::to_string(encoder_ix); two_int.push_back(module->addWire(new_id(two_name, __LINE__, ""), 1)); @@ -1518,14 +1411,11 @@ struct MultPassWorker { // instantiate the cpa RTLIL::Wire *cpa_carry[z_sz]; - if (x_sz + y_sz != z_sz) - log("Result of multiplier is incomplete with respect to domain of inputs\n"); - for (int cix = 0; cix < z_sz; cix++) { std::string cpa_cix_name = "cpa_carry_" + std::to_string(cix) + "_"; cpa_carry[cix] = module->addWire(new_id(cpa_cix_name, __LINE__, ""), 1); } - log(" Building cpa array for booth for output size %u\n", z_sz); + for (int cpa_ix = 0; cpa_ix < z_sz; cpa_ix++) { // The end case where we pass the last two summands @@ -1565,7 +1455,7 @@ struct MultPassWorker { RTLIL::Wire *op_wire = module->addWire(NEW_ID, 1); BuildHa(cpa_name, fa_sum_n[fa_row_count - 1][cpa_ix - offset + 2], ci_wire, op_wire, cpa_carry[cpa_ix - offset]); - connect_sigSpecToWire(op_wire, SigSpec(Z, cpa_ix, 1)); + module->connect(op_wire, SigSpec(Z, cpa_ix, 1)); } } @@ -1599,7 +1489,7 @@ struct MultPassWorker { }; struct MultPass : public Pass { - MultPass() : Pass("multpass", "Map $mul to booth multipliers") {} + MultPass() : Pass("booth", "Map $mul to booth multipliers") {} void execute(vector args, RTLIL::Design *design) override { (void)args; diff --git a/tests/techmap/booth_map_script.ys_ b/tests/techmap/booth_map_script.ys_ index 0f323bdd863..d2fe5d3f0a3 100644 --- a/tests/techmap/booth_map_script.ys_ +++ b/tests/techmap/booth_map_script.ys_ @@ -1 +1 @@ -multpass +booth From 1d92ea8001d7fde5aca8d8fe27c3c4839a97453a Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Fri, 8 Sep 2023 16:16:24 -0700 Subject: [PATCH 007/240] Support for turning on mult pass from generic synth command --- techlibs/common/synth.cc | 70 +++++++++++++++++++--------------------- 1 file changed, 34 insertions(+), 36 deletions(-) diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 63395c36802..01dadae7163 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -17,17 +17,16 @@ * */ -#include "kernel/register.h" #include "kernel/celltypes.h" -#include "kernel/rtlil.h" #include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct SynthPass : public ScriptPass -{ - SynthPass() : ScriptPass("synth", "generic synthesis script") { } +struct SynthPass : public ScriptPass { + SynthPass() : ScriptPass("synth", "generic synthesis script") {} void help() override { @@ -60,6 +59,9 @@ struct SynthPass : public ScriptPass log(" -noabc\n"); log(" do not run abc (as if yosys was compiled without ABC support)\n"); log("\n"); + log(" -booth\n"); + log(" run the booth pass to convert $mul to Booth encoded multipliers"); + log("\n"); log(" -noalumacc\n"); log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n"); log(" their direct form ($add, $sub, etc.).\n"); @@ -93,7 +95,8 @@ struct SynthPass : public ScriptPass } string top_module, fsm_opts, memory_opts, abc; - bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap; + bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, mult; + int lut; void clear_flags() override @@ -110,6 +113,7 @@ struct SynthPass : public ScriptPass noabc = false; noshare = false; flowmap = false; + mult = false; abc = "abc"; } @@ -119,24 +123,23 @@ struct SynthPass : public ScriptPass clear_flags(); size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - if (args[argidx] == "-top" && argidx+1 < args.size()) { + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-top" && argidx + 1 < args.size()) { top_module = args[++argidx]; continue; } - if (args[argidx] == "-encfile" && argidx+1 < args.size()) { + if (args[argidx] == "-encfile" && argidx + 1 < args.size()) { fsm_opts = " -encfile " + args[++argidx]; continue; } - if (args[argidx] == "-run" && argidx+1 < args.size()) { - size_t pos = args[argidx+1].find(':'); + if (args[argidx] == "-run" && argidx + 1 < args.size()) { + size_t pos = args[argidx + 1].find(':'); if (pos == std::string::npos) { run_from = args[++argidx]; run_to = args[argidx]; } else { run_from = args[++argidx].substr(0, pos); - run_to = args[argidx].substr(pos+1); + run_to = args[argidx].substr(pos + 1); } continue; } @@ -164,6 +167,11 @@ struct SynthPass : public ScriptPass noalumacc = true; continue; } + if (args[argidx] == "-mult") { + mult = true; + continue; + } + if (args[argidx] == "-nordff") { memory_opts += " -nordff"; continue; @@ -206,8 +214,7 @@ struct SynthPass : public ScriptPass void script() override { - if (check_label("begin")) - { + if (check_label("begin")) { if (help_mode) { run("hierarchy -check [-top | -auto-top]"); } else { @@ -221,8 +228,7 @@ struct SynthPass : public ScriptPass } } - if (check_label("coarse")) - { + if (check_label("coarse")) { run("proc"); if (help_mode || flatten) run("flatten", " (if -flatten)"); @@ -240,6 +246,8 @@ struct SynthPass : public ScriptPass run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); else if (lut) run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut)); + if (mult) + run("booth"); if (!noalumacc) run("alumacc", " (unless -noalumacc)"); if (!noshare) @@ -249,50 +257,40 @@ struct SynthPass : public ScriptPass run("opt_clean"); } - if (check_label("fine")) - { + if (check_label("fine")) { run("opt -fast -full"); run("memory_map"); run("opt -full"); run("techmap"); - if (help_mode) - { + if (help_mode) { run("techmap -map +/gate2lut.v", "(if -noabc and -lut)"); run("clean; opt_lut", " (if -noabc and -lut)"); run("flowmap -maxlut K", " (if -flowmap and -lut)"); - } - else if (noabc && lut) - { + } else if (noabc && lut) { run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut)); run("clean; opt_lut"); - } - else if (flowmap) - { + } else if (flowmap) { run(stringf("flowmap -maxlut %d", lut)); } run("opt -fast"); if (!noabc && !flowmap) { - #ifdef YOSYS_ENABLE_ABC - if (help_mode) - { +#ifdef YOSYS_ENABLE_ABC + if (help_mode) { run(abc + " -fast", " (unless -noabc, unless -lut)"); run(abc + " -fast -lut k", "(unless -noabc, if -lut)"); - } - else - { + } else { if (lut) run(stringf("%s -fast -lut %d", abc.c_str(), lut)); else run(abc + " -fast"); } run("opt -fast", " (unless -noabc)"); - #endif +#endif } } - if (check_label("check")) - { + if (check_label("check")) { run("hierarchy -check"); run("stat"); run("check"); From 0fa412502cd19deef2d2972391e9b0e7c1726074 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Fri, 8 Sep 2023 16:44:59 -0700 Subject: [PATCH 008/240] mult -> booth in synth.cc, to turn on use synth -booth --- techlibs/common/synth.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 01dadae7163..006a3c8dd84 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -95,7 +95,7 @@ struct SynthPass : public ScriptPass { } string top_module, fsm_opts, memory_opts, abc; - bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, mult; + bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth; int lut; @@ -113,7 +113,7 @@ struct SynthPass : public ScriptPass { noabc = false; noshare = false; flowmap = false; - mult = false; + booth = false; abc = "abc"; } @@ -167,8 +167,8 @@ struct SynthPass : public ScriptPass { noalumacc = true; continue; } - if (args[argidx] == "-mult") { - mult = true; + if (args[argidx] == "-booth") { + booth = true; continue; } @@ -246,7 +246,7 @@ struct SynthPass : public ScriptPass { run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); else if (lut) run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut)); - if (mult) + if (booth) run("booth"); if (!noalumacc) run("alumacc", " (unless -noalumacc)"); From d77fb8150708f2e86bd6caa62424970cb3b71757 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sun, 10 Sep 2023 12:45:36 -0700 Subject: [PATCH 009/240] 2d array -> 1d array in module generator --- passes/techmap/multpass.cc | 122 +++++++++++++++++++------------------ 1 file changed, 63 insertions(+), 59 deletions(-) diff --git a/passes/techmap/multpass.cc b/passes/techmap/multpass.cc index c0e56f2ad61..5e8dcbc3bd8 100644 --- a/passes/techmap/multpass.cc +++ b/passes/techmap/multpass.cc @@ -1112,7 +1112,6 @@ struct MultPassWorker { /* Signed Multiplier */ - void CreateBoothSMult(RTLIL::Module *module, int x_sz, int y_sz, int z_sz, RTLIL::Wire *X, RTLIL::Wire *Y, RTLIL::Wire *Z) { // product unsigned enc_count = (y_sz / 2) + (((y_sz % 2) != 0) ? 1 : 0); @@ -1171,20 +1170,22 @@ struct MultPassWorker { cori_n_int[encoder_ix - 1]); } } + // Decoders and PP generation - RTLIL::Wire *PPij[enc_count][dec_count]; - RTLIL::Wire *nxj[enc_count][dec_count]; + RTLIL::Wire *PPij[enc_count * dec_count]; + RTLIL::Wire *nxj[enc_count * dec_count]; + for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) { for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) { std::string ppij_name = "ppij_" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; - PPij[encoder_ix - 1][decoder_ix - 1] = module->addWire(new_id(ppij_name, __LINE__, ""), 1); + PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1] = module->addWire(new_id(ppij_name, __LINE__, ""), 1); std::string nxj_name; if (decoder_ix == 1) nxj_name = "nxj_pre_dec" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; else nxj_name = "nxj_" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; - nxj[encoder_ix - 1][decoder_ix - 1] = module->addWire(new_id(nxj_name, __LINE__, ""), 1); + nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1] = module->addWire(new_id(nxj_name, __LINE__, ""), 1); } } @@ -1202,7 +1203,7 @@ struct MultPassWorker { auto cell = module->addCell(new_id(pre_dec_name, __LINE__, ""), ID($_NOT_)); cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); cell->setPort(ID::A, negi_n_int[encoder_ix - 1]); - cell->setPort(ID::Y, nxj[encoder_ix - 1][0]); + cell->setPort(ID::Y, nxj[(encoder_ix - 1) * dec_count]); } for (int decoder_ix = 1; decoder_ix < dec_count; decoder_ix++) { @@ -1214,18 +1215,18 @@ struct MultPassWorker { std::string dec_name = "dec_" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; - BuildBr4d(dec_name, nxj[encoder_ix - 1][decoder_ix - 1], twoi_n_int[encoder_ix - 1], + BuildBr4d(dec_name, nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1], twoi_n_int[encoder_ix - 1], mk_wireFromSigSpec(SigSpec(X, decoder_ix - 1, 1)), negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], - PPij[encoder_ix - 1][decoder_ix - 1], nxj[encoder_ix - 1][decoder_ix]); + PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1], nxj[((encoder_ix - 1) * dec_count) + decoder_ix]); } // duplicate end for sign fix // applies to 9th decoder (xsz+1 decoder). std::string dec_name = "dec_" + std::to_string(encoder_ix) + "_" + std::to_string(x_sz + 1) + "_"; RTLIL::Wire *unused_op = nullptr; - BuildBr4d(dec_name, nxj[encoder_ix - 1][dec_count - 1], twoi_n_int[encoder_ix - 1], + BuildBr4d(dec_name, nxj[((encoder_ix - 1) * dec_count) + dec_count - 1], twoi_n_int[encoder_ix - 1], mk_wireFromSigSpec(SigSpec(X, dec_count - 2, 1)), negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], - PPij[encoder_ix - 1][dec_count - 1], unused_op); + PPij[((encoder_ix - 1) * dec_count) + dec_count - 1], unused_op); } // @@ -1233,16 +1234,17 @@ struct MultPassWorker { // int fa_el_ix = 0; int fa_row_ix = 0; - RTLIL::Wire *fa_sum_n[fa_row_count][fa_count]; - RTLIL::Wire *fa_carry_n[fa_row_count][fa_count]; + // use 1 d arrays (2d cannot have variable sized indices) + RTLIL::Wire *fa_sum_n[fa_row_count * fa_count]; + RTLIL::Wire *fa_carry_n[fa_row_count * fa_count]; for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) { for (fa_el_ix = 0; fa_el_ix < fa_count; fa_el_ix++) { std::string fa_sum_name = "fa_sum_n_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_"; - fa_sum_n[fa_row_ix][fa_el_ix] = module->addWire(new_id(fa_sum_name, __LINE__, ""), 1); + fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] = module->addWire(new_id(fa_sum_name, __LINE__, ""), 1); std::string fa_carry_name = "fa_carry_n" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_"; - fa_carry_n[fa_row_ix][fa_el_ix] = module->addWire(new_id(fa_carry_name, __LINE__, ""), 1); + fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix] = module->addWire(new_id(fa_carry_name, __LINE__, ""), 1); } } @@ -1268,11 +1270,11 @@ struct MultPassWorker { bfa_name = "bfa_0_step_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; auto cell = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); cell->setParam(ID::WIDTH, 1); - cell->setPort(ID::A, PPij[0][fa_el_ix]); - cell->setPort(ID::B, PPij[1][fa_el_ix - 2]); - cell->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); - cell->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); - cell->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + cell->setPort(ID::A, PPij[(0 * dec_count) + fa_el_ix]); + cell->setPort(ID::B, PPij[(1 * dec_count) + fa_el_ix - 2]); + cell->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); + cell->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); + cell->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); } // end 3 cells: x_sz+1.2.3 // @@ -1281,11 +1283,11 @@ struct MultPassWorker { bfa_name = "bfa_0_se_0" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; auto cell1 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); cell1->setParam(ID::WIDTH, 1); - cell1->setPort(ID::A, PPij[0][x_sz]); - cell1->setPort(ID::B, PPij[1][fa_el_ix - 2]); - cell1->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); - cell1->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); - cell1->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + cell1->setPort(ID::A, PPij[(0 * dec_count) + x_sz]); + cell1->setPort(ID::B, PPij[(1 * dec_count) + fa_el_ix - 2]); + cell1->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); + cell1->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); + cell1->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); // exception:invert ppi fa_el_ix++; @@ -1295,7 +1297,7 @@ struct MultPassWorker { RTLIL::Wire *d08_inv = module->addWire(NEW_ID, 1); - cellinv1->setPort(ID::A, PPij[0][dec_count - 1]); + cellinv1->setPort(ID::A, PPij[(0 * dec_count) + dec_count - 1]); cellinv1->setPort(ID::Y, d08_inv); exc_inv_name = "bfa_0_exc_inv2_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; @@ -1303,7 +1305,7 @@ struct MultPassWorker { auto cellinv2 = module->addCell(new_id(exc_inv_name, __LINE__, ""), ID($_NOT_)); cellinv2->add_strpool_attribute(ID::src, cellinv2->get_strpool_attribute(ID::src)); RTLIL::Wire *d18_inv = module->addWire(NEW_ID, 1); - cellinv2->setPort(ID::A, PPij[1][dec_count - 1]); + cellinv2->setPort(ID::A, PPij[(1 * dec_count) + dec_count - 1]); cellinv2->setPort(ID::Y, d18_inv); bfa_name = "bfa_0_se_1_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; @@ -1312,9 +1314,9 @@ struct MultPassWorker { cell2->setParam(ID::WIDTH, 1); cell2->setPort(ID::A, d08_inv); cell2->setPort(ID::B, d18_inv); - cell2->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); - cell2->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); - cell2->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + cell2->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); + cell2->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); + cell2->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); // sign extension fa_el_ix++; @@ -1323,9 +1325,9 @@ struct MultPassWorker { cell3->setParam(ID::WIDTH, 1); cell3->setPort(ID::A, State::S0); cell3->setPort(ID::B, State::S1); - cell3->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); - cell3->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); - cell3->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + cell3->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); + cell3->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); + cell3->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); } } @@ -1340,22 +1342,23 @@ struct MultPassWorker { std::to_string(fa_el_ix) + "_L"; auto cell1 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); cell1->setParam(ID::WIDTH, 1); - cell1->setPort(ID::A, fa_sum_n[fa_row_ix - 1][2]); // from prior full adder row + cell1->setPort(ID::A, fa_sum_n[(fa_row_ix - 1) * fa_count + 2]); // from prior full adder row cell1->setPort(ID::B, State::S0); cell1->setPort(ID::C, cori_n_int[fa_row_ix]); - cell1->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); - cell1->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + cell1->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); + cell1->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); fa_el_ix++; bfa_name = "bfa_" + std::to_string(fa_row_ix) + "_base_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; auto cell2 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); cell2->setParam(ID::WIDTH, 1); - cell2->setPort(ID::A, fa_sum_n[fa_row_ix - 1][3]); // from prior full adder row + cell2->setPort(ID::A, + fa_sum_n[(fa_row_ix - 1) * fa_count + 3]); // from prior full adder row cell2->setPort(ID::B, State::S0); - cell2->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); - cell2->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); - cell2->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + cell2->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); + cell2->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); + cell2->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); } else if (fa_el_ix >= 2 && fa_el_ix <= x_sz + 1) { @@ -1364,11 +1367,11 @@ struct MultPassWorker { std::to_string(fa_el_ix) + "_L"; auto cell = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); cell->setParam(ID::WIDTH, 1); - cell->setPort(ID::A, fa_sum_n[fa_row_ix - 1][fa_el_ix + 2]); - cell->setPort(ID::B, PPij[fa_row_ix + 1][fa_el_ix - 2]); - cell->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); - cell->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); - cell->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + cell->setPort(ID::A, fa_sum_n[(fa_row_ix - 1) * fa_count + fa_el_ix + 2]); + cell->setPort(ID::B, PPij[(fa_row_ix + 1) * dec_count + fa_el_ix - 2]); + cell->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); + cell->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); + cell->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); } else if (fa_el_ix > x_sz + 1) { @@ -1379,18 +1382,18 @@ struct MultPassWorker { auto cellinv = module->addCell(new_id(se_inv_name, __LINE__, ""), ID($_NOT_)); cellinv->add_strpool_attribute(ID::src, cellinv->get_strpool_attribute(ID::src)); RTLIL::Wire *d_inv = module->addWire(NEW_ID, 1); - cellinv->setPort(ID::A, PPij[fa_row_ix + 1][dec_count - 1]); + cellinv->setPort(ID::A, PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]); cellinv->setPort(ID::Y, d_inv); bfa_name = "bfa_" + std::to_string(fa_row_ix) + "_se_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; auto cell1 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); cell1->setParam(ID::WIDTH, 1); - cell1->setPort(ID::A, fa_carry_n[fa_row_ix - 1][fa_count - 1]); + cell1->setPort(ID::A, fa_carry_n[((fa_row_ix - 1) * fa_count) + fa_count - 1]); cell1->setPort(ID::B, d_inv); - cell1->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); - cell1->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); - cell1->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + cell1->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); + cell1->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); + cell1->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); fa_el_ix++; // sign extension @@ -1400,9 +1403,9 @@ struct MultPassWorker { cell2->setParam(ID::WIDTH, 1); cell2->setPort(ID::A, State::S0); cell2->setPort(ID::B, State::S1); - cell2->setPort(ID::C, fa_carry_n[fa_row_ix][fa_el_ix - 1]); - cell2->setPort(ID::X, fa_carry_n[fa_row_ix][fa_el_ix]); - cell2->setPort(ID::Y, fa_sum_n[fa_row_ix][fa_el_ix]); + cell2->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); + cell2->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); + cell2->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); } } } @@ -1428,7 +1431,7 @@ struct MultPassWorker { std::string buf_name = "pp_buf_" + std::to_string(cpa_ix) + "_" + "driven_by_fa_row_" + std::to_string(fa_row_ix) + "_"; auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setPort(ID::A, fa_sum_n[fa_row_ix][0]); + buf->setPort(ID::A, fa_sum_n[(fa_row_ix * fa_count) + 0]); buf->setParam(ID::A_WIDTH, 1); buf->setParam(ID::Y_WIDTH, 1); buf->setParam(ID::A_SIGNED, true); @@ -1437,7 +1440,7 @@ struct MultPassWorker { cpa_ix++; buf_name = "pp_buf_" + std::to_string(cpa_ix) + "_" + "driven_by_fa_row_" + std::to_string(fa_row_ix) + "_"; buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setPort(ID::A, fa_sum_n[fa_row_ix][1]); + buf->setPort(ID::A, fa_sum_n[(fa_row_ix * fa_count) + 1]); buf->setParam(ID::A_WIDTH, 1); buf->setParam(ID::Y_WIDTH, 1); buf->setParam(ID::A_SIGNED, true); @@ -1454,7 +1457,8 @@ struct MultPassWorker { ci_wire = cpa_carry[cpa_ix - offset - 1]; RTLIL::Wire *op_wire = module->addWire(NEW_ID, 1); - BuildHa(cpa_name, fa_sum_n[fa_row_count - 1][cpa_ix - offset + 2], ci_wire, op_wire, cpa_carry[cpa_ix - offset]); + BuildHa(cpa_name, fa_sum_n[(fa_row_count - 1) * fa_count + cpa_ix - offset + 2], ci_wire, op_wire, + cpa_carry[cpa_ix - offset]); module->connect(op_wire, SigSpec(Z, cpa_ix, 1)); } } @@ -1481,10 +1485,10 @@ struct MultPassWorker { nxj_o_int, cor_o_int, pp0_o_int, pp1_o_int); - join_wires_with_buffer(pp0_o_int, fa_sum_n[0][0]); - join_wires_with_buffer(pp1_o_int, fa_sum_n[0][1]); - join_wires_with_buffer(cor_o_int, fa_carry_n[0][1]); - join_wires_with_buffer(nxj_o_int, nxj[0][2]); + join_wires_with_buffer(pp0_o_int, fa_sum_n[(0 * fa_count) + 0]); + join_wires_with_buffer(pp1_o_int, fa_sum_n[(0 * fa_count) + 1]); + join_wires_with_buffer(cor_o_int, fa_carry_n[(0 * fa_count) + 1]); + join_wires_with_buffer(nxj_o_int, nxj[(0 * dec_count) + 2]); } }; From 8d4b6c2f69b5f6b2fb09289a535b74a20e7a7735 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sun, 10 Sep 2023 13:31:47 -0700 Subject: [PATCH 010/240] Switched arrays for signed multiplier construction to heap --- passes/techmap/multpass.cc | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/passes/techmap/multpass.cc b/passes/techmap/multpass.cc index 5e8dcbc3bd8..00dcc6e2740 100644 --- a/passes/techmap/multpass.cc +++ b/passes/techmap/multpass.cc @@ -1124,10 +1124,10 @@ struct MultPassWorker { "Result of size %d. %d encoders %d decoders\n", x_sz, y_sz, z_sz, enc_count, dec_count); - RTLIL::Wire *negi_n_int[enc_count]; - RTLIL::Wire *twoi_n_int[enc_count]; - RTLIL::Wire *onei_n_int[enc_count]; - RTLIL::Wire *cori_n_int[enc_count]; + RTLIL::Wire **negi_n_int = new RTLIL::Wire *[enc_count]; + RTLIL::Wire **twoi_n_int = new RTLIL::Wire *[enc_count]; + RTLIL::Wire **onei_n_int = new RTLIL::Wire *[enc_count]; + RTLIL::Wire **cori_n_int = new RTLIL::Wire *[enc_count]; for (unsigned encoder_ix = 1; encoder_ix <= enc_count; encoder_ix++) { std::string enc_name = "enc_" + std::to_string(encoder_ix) + "_"; @@ -1172,8 +1172,8 @@ struct MultPassWorker { } // Decoders and PP generation - RTLIL::Wire *PPij[enc_count * dec_count]; - RTLIL::Wire *nxj[enc_count * dec_count]; + RTLIL::Wire **PPij = new RTLIL::Wire *[enc_count * dec_count]; + RTLIL::Wire **nxj = new RTLIL::Wire *[enc_count * dec_count]; for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) { for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) { @@ -1235,8 +1235,8 @@ struct MultPassWorker { int fa_el_ix = 0; int fa_row_ix = 0; // use 1 d arrays (2d cannot have variable sized indices) - RTLIL::Wire *fa_sum_n[fa_row_count * fa_count]; - RTLIL::Wire *fa_carry_n[fa_row_count * fa_count]; + RTLIL::Wire **fa_sum_n = new RTLIL::Wire *[fa_row_count * fa_count]; + RTLIL::Wire **fa_carry_n = new RTLIL::Wire *[fa_row_count * fa_count]; for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) { for (fa_el_ix = 0; fa_el_ix < fa_count; fa_el_ix++) { @@ -1489,6 +1489,14 @@ struct MultPassWorker { join_wires_with_buffer(pp1_o_int, fa_sum_n[(0 * fa_count) + 1]); join_wires_with_buffer(cor_o_int, fa_carry_n[(0 * fa_count) + 1]); join_wires_with_buffer(nxj_o_int, nxj[(0 * dec_count) + 2]); + + delete[] negi_n_int; + delete[] twoi_n_int; + delete[] onei_n_int; + delete[] cori_n_int; + + delete[] fa_sum_n; + delete[] fa_carry_n; } }; From 1b5287af5908e71edd07d9de2d6872f3c2a389ed Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sun, 10 Sep 2023 14:20:30 -0700 Subject: [PATCH 011/240] cpa_carry array added to heap --- passes/techmap/multpass.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/passes/techmap/multpass.cc b/passes/techmap/multpass.cc index 00dcc6e2740..9e97fc6741e 100644 --- a/passes/techmap/multpass.cc +++ b/passes/techmap/multpass.cc @@ -1412,7 +1412,7 @@ struct MultPassWorker { } // instantiate the cpa - RTLIL::Wire *cpa_carry[z_sz]; + RTLIL::Wire **cpa_carry = new RTLIL::Wire *[z_sz]; for (int cix = 0; cix < z_sz; cix++) { std::string cpa_cix_name = "cpa_carry_" + std::to_string(cix) + "_"; @@ -1497,6 +1497,7 @@ struct MultPassWorker { delete[] fa_sum_n; delete[] fa_carry_n; + delete[] cpa_carry; } }; From a2c8e47295dbb93faeb2f949ce354c4faa919fc9 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Mon, 11 Sep 2023 11:39:13 -0700 Subject: [PATCH 012/240] multpass.cc -> booth.cc, added author/support contact info --- passes/techmap/Makefile.inc | 5 +---- passes/techmap/{multpass.cc => booth.cc} | 12 ++++++++---- 2 files changed, 9 insertions(+), 8 deletions(-) rename passes/techmap/{multpass.cc => booth.cc} (99%) diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 8b0b2aa23b7..fb003103d28 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -4,7 +4,7 @@ OBJS += passes/techmap/techmap.o OBJS += passes/techmap/simplemap.o OBJS += passes/techmap/dfflibmap.o OBJS += passes/techmap/maccmap.o -OBJS += passes/techmap/multpass.o +OBJS += passes/techmap/booth.o OBJS += passes/techmap/libparse.o ifeq ($(ENABLE_ABC),1) @@ -30,9 +30,6 @@ OBJS += passes/techmap/extract_reduce.o OBJS += passes/techmap/alumacc.o OBJS += passes/techmap/dffinit.o OBJS += passes/techmap/pmuxtree.o -OBJS += passes/techmap/bmuxmap.o -OBJS += passes/techmap/demuxmap.o -OBJS += passes/techmap/bwmuxmap.o OBJS += passes/techmap/muxcover.o OBJS += passes/techmap/aigmap.o OBJS += passes/techmap/tribuf.o diff --git a/passes/techmap/multpass.cc b/passes/techmap/booth.cc similarity index 99% rename from passes/techmap/multpass.cc rename to passes/techmap/booth.cc index 9e97fc6741e..21f16aec7a8 100644 --- a/passes/techmap/multpass.cc +++ b/passes/techmap/booth.cc @@ -1,6 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * + * Copyright (C) 2023 Andy Fox https://www.linkedin.com/in/awfox/ * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -17,8 +18,8 @@ */ /* - MultPass - -------- + Booth Pass + ---------- Replace $mul with booth encoded multipliers. Two different architectures used for signed/unsigned. @@ -31,13 +32,13 @@ http://i.stanford.edu/pub/cstr/reports/csl/tr/94/617/CSL-TR-94-617.pdf How to use: - Add multpass to your yosys script eg: + Add booth pass to your yosys script eg: read_verilog smultiply5_rtl.v opt wreduce opt - multpass + booth alumacc maccmap opt @@ -46,6 +47,9 @@ abc -liberty NangateOpenCellLibrary_typical.lib stat -liberty NangateOpenCellLibrary_typical.lib write_verilog -norename booth_final.v + +or in generic synthesis call with -booth argument: +synth -top my_design -booth */ #include "kernel/sigtools.h" From eccc0ae6db50effc7f42d69038918483d6888089 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Mon, 11 Sep 2023 12:14:12 -0700 Subject: [PATCH 013/240] Based passes/techmap/Makefile.inc changes on latest in yosys --- passes/techmap/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index fb003103d28..97d8b76f3b8 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -30,6 +30,9 @@ OBJS += passes/techmap/extract_reduce.o OBJS += passes/techmap/alumacc.o OBJS += passes/techmap/dffinit.o OBJS += passes/techmap/pmuxtree.o +OBJS += passes/techmap/bmuxmap.o +OBJS += passes/techmap/demuxmap.o +OBJS += passes/techmap/bwmuxmap.o OBJS += passes/techmap/muxcover.o OBJS += passes/techmap/aigmap.o OBJS += passes/techmap/tribuf.o From e4fe522767c3ddfeb90c2f4091890cb45584e0e9 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Mon, 11 Sep 2023 13:00:11 -0700 Subject: [PATCH 014/240] MultPassWorker -> BoothPassWorker --- passes/techmap/booth.cc | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 21f16aec7a8..e749168522d 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -58,13 +58,13 @@ synth -top my_design -booth USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct MultPassWorker { +struct BoothPassWorker { RTLIL::Module *module; SigMap sigmap; int booth_counter; - MultPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; } + BoothPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; } // Helper routines for building architecture subcomponents @@ -1505,15 +1505,16 @@ struct MultPassWorker { } }; -struct MultPass : public Pass { - MultPass() : Pass("booth", "Map $mul to booth multipliers") {} +struct BoothPass : public Pass { + BoothPass() : Pass("booth", "Map $mul to booth multipliers") {} void execute(vector args, RTLIL::Design *design) override { (void)args; - log_header(design, "Executing multpass. Generating Booth Multiplier structures for signed/unsigned multipliers of 4 bits or more\n"); + log_header(design, + "Executing booth pass. Generating Booth Multiplier structures for signed/unsigned multipliers of 4 bits or more\n"); for (auto mod : design->selected_modules()) if (!mod->has_processes_warn()) { - MultPassWorker worker(mod); + BoothPassWorker worker(mod); worker.run(); log_header(design, "Created %d booth multipliers.\n", worker.booth_counter); } From 08f79d111e9be151e9ede91491a6e2c2080ad847 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 9 Sep 2023 22:32:51 +0200 Subject: [PATCH 015/240] ci: Enable extra libstdc++ assertions --- .github/workflows/test-linux.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml index eee556794af..a16481726d3 100644 --- a/.github/workflows/test-linux.yml +++ b/.github/workflows/test-linux.yml @@ -43,6 +43,7 @@ jobs: sudo apt-get install $CC $CXX echo "CC=$CC" >> $GITHUB_ENV echo "CXX=$CXX" >> $GITHUB_ENV + echo "CXXFLAGS=-Wp,-D_GLIBCXX_ASSERTIONS" >> $GITHUB_ENV env: CC: ${{ matrix.compiler }} From 9042124ba7ab746b466a1450f18462d1741afa79 Mon Sep 17 00:00:00 2001 From: Tim Paine <3105306+timkpaine@users.noreply.github.com> Date: Fri, 15 Sep 2023 14:24:45 -0400 Subject: [PATCH 016/240] Alphabetize headers to be installed, include some missing required ones for plugins, fixes https://github.com/chipsalliance/synlig/pull/1972 https://github.com/dau-dev/tools/issues/6 --- Makefile | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/Makefile b/Makefile index d7ecff99921..a93930be0c9 100644 --- a/Makefile +++ b/Makefile @@ -606,31 +606,35 @@ Q = S = endif -$(eval $(call add_include_file,kernel/yosys.h)) -$(eval $(call add_include_file,kernel/hashlib.h)) -$(eval $(call add_include_file,kernel/log.h)) -$(eval $(call add_include_file,kernel/rtlil.h)) $(eval $(call add_include_file,kernel/binding.h)) -$(eval $(call add_include_file,kernel/register.h)) $(eval $(call add_include_file,kernel/cellaigs.h)) -$(eval $(call add_include_file,kernel/celltypes.h)) $(eval $(call add_include_file,kernel/celledges.h)) +$(eval $(call add_include_file,kernel/celltypes.h)) $(eval $(call add_include_file,kernel/consteval.h)) $(eval $(call add_include_file,kernel/constids.inc)) -$(eval $(call add_include_file,kernel/sigtools.h)) -$(eval $(call add_include_file,kernel/modtools.h)) -$(eval $(call add_include_file,kernel/macc.h)) -$(eval $(call add_include_file,kernel/utils.h)) -$(eval $(call add_include_file,kernel/satgen.h)) -$(eval $(call add_include_file,kernel/qcsat.h)) +$(eval $(call add_include_file,kernel/cost.h)) $(eval $(call add_include_file,kernel/ff.h)) $(eval $(call add_include_file,kernel/ffinit.h)) +$(eval $(call add_include_file,kernel/ffmerge.h)) +$(eval $(call add_include_file,kernel/fmt.h)) ifeq ($(ENABLE_ZLIB),1) $(eval $(call add_include_file,kernel/fstdata.h)) endif +$(eval $(call add_include_file,kernel/hashlib.h)) +$(eval $(call add_include_file,kernel/json.h)) +$(eval $(call add_include_file,kernel/log.h)) +$(eval $(call add_include_file,kernel/macc.h)) +$(eval $(call add_include_file,kernel/modtools.h)) $(eval $(call add_include_file,kernel/mem.h)) +$(eval $(call add_include_file,kernel/qcsat.h)) +$(eval $(call add_include_file,kernel/register.h)) +$(eval $(call add_include_file,kernel/rtlil.h)) +$(eval $(call add_include_file,kernel/satgen.h)) +$(eval $(call add_include_file,kernel/sigtools.h)) +$(eval $(call add_include_file,kernel/timinginfo.h)) +$(eval $(call add_include_file,kernel/utils.h)) +$(eval $(call add_include_file,kernel/yosys.h)) $(eval $(call add_include_file,kernel/yw.h)) -$(eval $(call add_include_file,kernel/json.h)) $(eval $(call add_include_file,libs/ezsat/ezsat.h)) $(eval $(call add_include_file,libs/ezsat/ezminisat.h)) ifeq ($(ENABLE_ZLIB),1) From 82221211642fdd23ecf90e853dffa05411bb62de Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 13 Sep 2023 12:47:18 +0200 Subject: [PATCH 017/240] verific: Add test of accurate semantics in memory inference --- tests/verific/memory_semantics.ys | 94 +++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 tests/verific/memory_semantics.ys diff --git a/tests/verific/memory_semantics.ys b/tests/verific/memory_semantics.ys new file mode 100644 index 00000000000..92f4fd2dc44 --- /dev/null +++ b/tests/verific/memory_semantics.ys @@ -0,0 +1,94 @@ +verific -sv < Date: Tue, 19 Sep 2023 00:23:00 +0000 Subject: [PATCH 018/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a93930be0c9..ab7ea18c060 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.33+34 +YOSYS_VER := 0.33+53 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 7d07615dee4d245dd97e6f4f643dde73f41a2c81 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Mon, 18 Sep 2023 23:26:35 -0400 Subject: [PATCH 019/240] allow attributes in front of ++/-- statements --- frontends/verilog/verilog_parser.y | 24 ++++++++++++------------ tests/verilog/asgn_expr.sv | 8 ++++---- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index d901b3b558d..04bf2c87e50 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -301,14 +301,18 @@ static void ensureAsgnExprAllowed() } // add a pre/post-increment/decrement statement -static const AstNode *addIncOrDecStmt(AstNode *lhs, dict *attr, AST::AstNodeType op, YYLTYPE begin, YYLTYPE end) +static const AstNode *addIncOrDecStmt(dict *stmt_attr, AstNode *lhs, + dict *op_attr, AST::AstNodeType op, + YYLTYPE begin, YYLTYPE end) { AstNode *one = AstNode::mkconst_int(1, true); AstNode *rhs = new AstNode(op, lhs->clone(), one); + if (op_attr != nullptr) + append_attr(rhs, op_attr); AstNode *stmt = new AstNode(AST_ASSIGN_EQ, lhs, rhs); SET_AST_NODE_LOC(stmt, begin, end); - if (attr != nullptr) - append_attr(stmt, attr); + if (stmt_attr != nullptr) + append_attr(stmt, stmt_attr); ast_stack.back()->children.push_back(stmt); return stmt; } @@ -317,7 +321,7 @@ static const AstNode *addIncOrDecStmt(AstNode *lhs, dict *at static AstNode *addIncOrDecExpr(AstNode *lhs, dict *attr, AST::AstNodeType op, YYLTYPE begin, YYLTYPE end, bool undo) { ensureAsgnExprAllowed(); - const AstNode *stmt = addIncOrDecStmt(lhs, attr, op, begin, end); + const AstNode *stmt = addIncOrDecStmt(nullptr, lhs, attr, op, begin, end); log_assert(stmt->type == AST_ASSIGN_EQ); AstNode *expr = stmt->children[0]->clone(); if (undo) { @@ -2666,14 +2670,10 @@ simple_behavioral_stmt: append_attr(node, $1); } | attr lvalue attr inc_or_dec_op { - // The position 1 attr to avoid shift/reduce conflicts with the - // other productions. We reject attributes in that position. - if (!$1->empty()) - frontend_verilog_yyerror("Attributes are not allowed on this size of the lvalue in an inc_or_dec_expression!"); - addIncOrDecStmt($2, $3, $4, @1, @4); - } | - inc_or_dec_op attr lvalue { - addIncOrDecStmt($3, $2, $1, @1, @3); + addIncOrDecStmt($1, $2, $3, $4, @1, @4); + } | + attr inc_or_dec_op attr lvalue { + addIncOrDecStmt($1, $4, $3, $2, @1, @4); } | attr lvalue OP_LE delay expr { AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5); diff --git a/tests/verilog/asgn_expr.sv b/tests/verilog/asgn_expr.sv index 567034d107d..9b874ede33b 100644 --- a/tests/verilog/asgn_expr.sv +++ b/tests/verilog/asgn_expr.sv @@ -13,21 +13,21 @@ module top; // post-increment/decrement statements x++; check(1, 0, 0); - y (* foo *) ++; + (* bar *) y (* foo *) ++; check(1, 1, 0); z--; check(1, 1, -1); - z (* foo *) --; + (* bar *) z (* foo *) --; check(1, 1, -2); // pre-increment/decrement statements are equivalent ++z; check(1, 1, -1); - ++ (* foo *) z; + (* bar *) ++ (* foo *) z; check(1, 1, 0); --x; check(0, 1, 0); - -- (* foo *) y; + (* bar *) -- (* foo *) y; check(0, 0, 0); // procedural pre-increment/decrement expressions From 28e99f2b8c50557e0376fbded1c77236a987ecec Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Mon, 18 Sep 2023 23:35:18 -0400 Subject: [PATCH 020/240] fix width of post-increment/decrement expressions --- frontends/verilog/verilog_parser.y | 2 +- tests/verilog/asgn_expr.sv | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 04bf2c87e50..cb8c453c087 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -325,7 +325,7 @@ static AstNode *addIncOrDecExpr(AstNode *lhs, dict *attr, AS log_assert(stmt->type == AST_ASSIGN_EQ); AstNode *expr = stmt->children[0]->clone(); if (undo) { - AstNode *minus_one = AstNode::mkconst_int(-1, true); + AstNode *minus_one = AstNode::mkconst_int(-1, true, 1); expr = new AstNode(op, expr, minus_one); } SET_AST_NODE_LOC(expr, begin, end); diff --git a/tests/verilog/asgn_expr.sv b/tests/verilog/asgn_expr.sv index 9b874ede33b..25f9caa33d1 100644 --- a/tests/verilog/asgn_expr.sv +++ b/tests/verilog/asgn_expr.sv @@ -56,5 +56,18 @@ module top; check(96, 200, 24); y = (z >>= 1'sb1) * 2; // shift is implicitly cast to unsigned check(96, 24, 12); + + // check width of post-increment expressions + z = (y = 0); + begin + byte w; + w = 0; + x = {1'b1, ++w}; + check(257, 0, 0); + assert (w == 1); + x = {2'b10, w++}; + check(513, 0, 0); + assert (w == 2); + end end endmodule From 18855f23ce866c014e8be3e4dc652b80deca121f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 19 Sep 2023 12:00:10 +0200 Subject: [PATCH 021/240] Set src attribute for verific with full info --- frontends/verific/verific.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index a67244d7ab3..cd844dceeee 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -265,7 +265,7 @@ void VerificImporter::import_attributes(dict &att Att *attr; if (obj->Linefile()) - attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile())); + attributes[ID::src] = stringf("%s:%d.%d-%d.%d", LineFile::GetFileName(obj->Linefile()), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol()); FOREACH_ATTRIBUTE(obj, mi, attr) { if (attr->Key()[0] == ' ' || attr->Value() == nullptr) From 35a05686c4e9987441ac298f5d631f1785e272fd Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 20 Sep 2023 00:15:04 +0000 Subject: [PATCH 022/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index ab7ea18c060..a75af96b555 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.33+53 +YOSYS_VER := 0.33+56 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From e0042bdff74a6895bff04d9fbd42ad4c4713369b Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Wed, 20 Sep 2023 15:49:05 -0700 Subject: [PATCH 023/240] Speed up TopoSort. The main sorting algorithm implementation in TopoSort::sort_worker is 11-12x faster. Overall, the complete sequence of building the graph and sorting is about 2.5-3x faster. The overall impact in e.g. the replace_const_cells optimization pass is a ~25% speedup. End-to-end impact on our synthesis flow is about 3%. --- kernel/utils.h | 182 +++++++++++++++++++++++--------------- passes/cmds/glift.cc | 2 +- passes/opt/opt_expr.cc | 15 ++-- passes/opt/share.cc | 2 +- passes/techmap/flatten.cc | 2 +- 5 files changed, 125 insertions(+), 78 deletions(-) diff --git a/kernel/utils.h b/kernel/utils.h index d37f045ff7c..e452f380e63 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -31,35 +31,31 @@ YOSYS_NAMESPACE_BEGIN // A map-like container, but you can save and restore the state // ------------------------------------------------ -template> -struct stackmap -{ -private: - std::vector> backup_state; +template > struct stackmap { + private: + std::vector> backup_state; dict current_state; static T empty_tuple; -public: - stackmap() { } - stackmap(const dict &other) : current_state(other) { } + public: + stackmap() {} + stackmap(const dict &other) : current_state(other) {} - template - void operator=(const Other &other) + template stackmap &operator=(const Other &other) { - for (auto &it : current_state) + for (const auto &it : current_state) if (!backup_state.empty() && backup_state.back().count(it.first) == 0) backup_state.back()[it.first] = new T(it.second); current_state.clear(); - for (auto &it : other) + for (const auto &it : other) set(it.first, it.second); - } - bool has(const Key &k) - { - return current_state.count(k) != 0; + return *this; } + bool has(const Key &k) { return current_state.count(k) != 0; } + void set(const Key &k, const T &v) { if (!backup_state.empty() && backup_state.back().count(k) == 0) @@ -83,7 +79,7 @@ struct stackmap void reset(const Key &k) { - for (int i = GetSize(backup_state)-1; i >= 0; i--) + for (int i = GetSize(backup_state) - 1; i >= 0; i--) if (backup_state[i].count(k) != 0) { if (backup_state[i].at(k) == nullptr) current_state.erase(k); @@ -94,20 +90,14 @@ struct stackmap current_state.erase(k); } - const dict &stdmap() - { - return current_state; - } + const dict &stdmap() { return current_state; } - void save() - { - backup_state.resize(backup_state.size()+1); - } + void save() { backup_state.resize(backup_state.size() + 1); } void restore() { log_assert(!backup_state.empty()); - for (auto &it : backup_state.back()) + for (const auto &it : backup_state.back()) if (it.second != nullptr) { current_state[it.first] = *it.second; delete it.second; @@ -123,46 +113,116 @@ struct stackmap } }; - // ------------------------------------------------ // A simple class for topological sorting // ------------------------------------------------ -template> -struct TopoSort +template , typename OPS = hash_ops> class TopoSort { - bool analyze_loops, found_loops; - std::map, C> database; - std::set> loops; + public: + // We use this ordering of the edges in the adjacency matrix for + // exact compatibility with an older implementation. + struct IndirectCmp { + IndirectCmp(const std::vector &nodes) : nodes_(nodes) {} + bool operator()(int a, int b) const + { + log_assert(static_cast(a) < nodes_.size()); + log_assert(static_cast(b) < nodes_.size()); + return node_cmp_(nodes_[a], nodes_[b]); + } + const C node_cmp_; + const std::vector &nodes_; + }; + + bool analyze_loops; + std::map node_to_index; + std::vector> edges; std::vector sorted; + std::set> loops; - TopoSort() + public: + TopoSort() : indirect_cmp(nodes) { analyze_loops = true; found_loops = false; } - void node(T n) + int node(T n) + { + auto it = node_to_index.find(n); + if (it == node_to_index.end()) { + int index = static_cast(nodes.size()); + node_to_index[n] = index; + nodes.push_back(n); + edges.push_back(std::set(indirect_cmp)); + return index; + } + return it->second; + } + + void edge(int l_index, int r_index) { edges[r_index].insert(l_index); } + + void edge(T left, T right) { edge(node(left), node(right)); } + + bool has_edges(const T &node) + { + auto it = node_to_index.find(node); + return it == node_to_index.end() || !edges[it->second].empty(); + } + + bool sort() { - if (database.count(n) == 0) - database[n] = std::set(); + log_assert(GetSize(node_to_index) == GetSize(edges)); + log_assert(GetSize(nodes) == GetSize(edges)); + + loops.clear(); + sorted.clear(); + found_loops = false; + + std::vector marked_cells(edges.size(), false); + std::vector active_cells(edges.size(), false); + std::vector active_stack; + + marked_cells.reserve(edges.size()); + sorted.reserve(edges.size()); + + for (const auto &it : node_to_index) + sort_worker(it.second, marked_cells, active_cells, active_stack); + + log_assert(GetSize(sorted) == GetSize(nodes)); + + return !found_loops; } - void edge(T left, T right) + // Build the more expensive representation of edges for + // a few passes that use it directly. + std::map, C> get_database() { - node(left); - database[right].insert(left); + std::map, C> database; + for (size_t i = 0; i < nodes.size(); ++i) { + std::set converted_edge_set; + for (int other_node : edges[i]) { + converted_edge_set.insert(nodes[other_node]); + } + database.emplace(nodes[i], converted_edge_set); + } + return database; } - void sort_worker(const T &n, std::set &marked_cells, std::set &active_cells, std::vector &active_stack) + private: + bool found_loops; + std::vector nodes; + const IndirectCmp indirect_cmp; + void sort_worker(const int root_index, std::vector &marked_cells, std::vector &active_cells, std::vector &active_stack) { - if (active_cells.count(n)) { + if (active_cells[root_index]) { found_loops = true; if (analyze_loops) { std::set loop; - for (int i = GetSize(active_stack)-1; i >= 0; i--) { - loop.insert(active_stack[i]); - if (active_stack[i] == n) + for (int i = GetSize(active_stack) - 1; i >= 0; i--) { + const int index = active_stack[i]; + loop.insert(nodes[index]); + if (index == root_index) break; } loops.insert(loop); @@ -170,42 +230,24 @@ struct TopoSort return; } - if (marked_cells.count(n)) + if (marked_cells[root_index]) return; - if (!database.at(n).empty()) - { + if (!edges[root_index].empty()) { if (analyze_loops) - active_stack.push_back(n); - active_cells.insert(n); + active_stack.push_back(root_index); + active_cells[root_index] = true; - for (auto &left_n : database.at(n)) + for (int left_n : edges[root_index]) sort_worker(left_n, marked_cells, active_cells, active_stack); if (analyze_loops) active_stack.pop_back(); - active_cells.erase(n); + active_cells[root_index] = false; } - marked_cells.insert(n); - sorted.push_back(n); - } - - bool sort() - { - loops.clear(); - sorted.clear(); - found_loops = false; - - std::set marked_cells; - std::set active_cells; - std::vector active_stack; - - for (auto &it : database) - sort_worker(it.first, marked_cells, active_cells, active_stack); - - log_assert(GetSize(sorted) == GetSize(database)); - return !found_loops; + marked_cells[root_index] = true; + sorted.push_back(nodes[root_index]); } }; diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index 439ded07685..faa4289e3a9 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -582,7 +582,7 @@ struct GliftPass : public Pass { for (auto cell : module->selected_cells()) { RTLIL::Module *tpl = design->module(cell->type); if (tpl != nullptr) { - if (topo_modules.database.count(tpl) == 0) + if (!topo_modules.has_edges(tpl)) worklist.push_back(tpl); topo_modules.edge(tpl, module); non_top_modules.insert(cell->type); diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 46773a344b1..7331d72a6fd 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -424,13 +424,18 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons for (auto &bit : sig) outbit_to_cell[bit].insert(cell); } - cells.node(cell); } - for (auto &it_right : cell_to_inbit) - for (auto &it_sigbit : it_right.second) - for (auto &it_left : outbit_to_cell[it_sigbit]) - cells.edge(it_left, it_right.first); + // Build the graph for the topological sort. + for (auto &it_right : cell_to_inbit) { + const int r_index = cells.node(it_right.first); + for (auto &it_sigbit : it_right.second) { + for (auto &it_left : outbit_to_cell[it_sigbit]) { + const int l_index = cells.node(it_left); + cells.edge(l_index, r_index); + } + } + } cells.sort(); diff --git a/passes/opt/share.cc b/passes/opt/share.cc index abef719370b..586bd9dfe9d 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -1032,7 +1032,7 @@ struct ShareWorker } bool found_scc = !toposort.sort(); - topo_cell_drivers = std::move(toposort.database); + topo_cell_drivers = toposort.get_database(); if (found_scc && toposort.analyze_loops) for (auto &loop : toposort.loops) { diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 7e6df5d2c1f..f49589b826c 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -312,7 +312,7 @@ struct FlattenPass : public Pass { for (auto cell : module->selected_cells()) { RTLIL::Module *tpl = design->module(cell->type); if (tpl != nullptr) { - if (topo_modules.database.count(tpl) == 0) + if (!topo_modules.has_edges(tpl)) worklist.insert(tpl); topo_modules.edge(tpl, module); } From b9745f638b0a2ee4fd97096af7bce0198aedd8be Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Wed, 20 Sep 2023 16:20:08 -0700 Subject: [PATCH 024/240] Remove extraneous "public:". --- kernel/utils.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/utils.h b/kernel/utils.h index e452f380e63..4679a23f2b9 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -140,7 +140,6 @@ template , typename OPS = hash_ops> cla std::vector sorted; std::set> loops; - public: TopoSort() : indirect_cmp(nodes) { analyze_loops = true; @@ -213,6 +212,7 @@ template , typename OPS = hash_ops> cla bool found_loops; std::vector nodes; const IndirectCmp indirect_cmp; + void sort_worker(const int root_index, std::vector &marked_cells, std::vector &active_cells, std::vector &active_stack) { if (active_cells[root_index]) { From aa06809d6483abe98ab270f093968cab5838d51b Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Mon, 18 Sep 2023 21:38:50 +0000 Subject: [PATCH 025/240] rtlil: Speeds up Yosys by 17% This PR speeds up by roughly 17% across a wide spectrum of designs tested at Google. Particularly for the mux generation pass. Co-authored-by: Rasmus Larsen Signed-off-by: Ethan Mahintorabi --- kernel/rtlil.cc | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 51d02091308..1b57af60acb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -4031,16 +4031,20 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec unpack(); other->unpack(); + dict pattern_to_with; for (int i = 0; i < GetSize(pattern.bits_); i++) { if (pattern.bits_[i].wire != NULL) { - for (int j = 0; j < GetSize(bits_); j++) { - if (bits_[j] == pattern.bits_[i]) { - other->bits_[j] = with.bits_[i]; - } - } + pattern_to_with.emplace(pattern.bits_[i], i); } } + for (int j = 0; j < GetSize(bits_); j++) { + auto it = pattern_to_with.find(bits_[j]); + if (it != pattern_to_with.end()) { + other->bits_[j] = with.bits_[it->second]; + } + } + other->check(); } From 9ed38bf9b662b36852271671f2a73ed659b00331 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Thu, 21 Sep 2023 02:46:49 -0700 Subject: [PATCH 026/240] Speed up the autoname pass by 3x. (#3945) * Speed up the autoname pass by 2x. This is accomplished by only constructing IdString objects for plain strings that have a higher score. * Defer creating IdStrings even further. This increases the speedup to 3x. --- passes/cmds/autoname.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc index 6019c61534f..737bd3e58be 100644 --- a/passes/cmds/autoname.cc +++ b/passes/cmds/autoname.cc @@ -24,8 +24,8 @@ PRIVATE_NAMESPACE_BEGIN int autoname_worker(Module *module, const dict& wire_score) { - dict> proposed_cell_names; - dict> proposed_wire_names; + dict> proposed_cell_names; + dict> proposed_wire_names; int best_score = -1; for (auto cell : module->selected_cells()) { @@ -36,7 +36,7 @@ int autoname_worker(Module *module, const dict& wire_score) if (bit.wire != nullptr && bit.wire->name[0] != '$') { if (suffix.empty()) suffix = stringf("_%s_%s", log_id(cell->type), log_id(conn.first)); - IdString new_name(bit.wire->name.str() + suffix); + string new_name(bit.wire->name.str() + suffix); int score = wire_score.at(bit.wire); if (cell->output(conn.first)) score = 0; score = 10000*score + new_name.size(); @@ -54,7 +54,7 @@ int autoname_worker(Module *module, const dict& wire_score) if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) { if (suffix.empty()) suffix = stringf("_%s", log_id(conn.first)); - IdString new_name(cell->name.str() + suffix); + string new_name(cell->name.str() + suffix); int score = wire_score.at(bit.wire); if (cell->output(conn.first)) score = 0; score = 10000*score + new_name.size(); @@ -71,7 +71,7 @@ int autoname_worker(Module *module, const dict& wire_score) for (auto &it : proposed_cell_names) { if (best_score*2 < it.second.first) continue; - IdString n = module->uniquify(it.second.second); + IdString n = module->uniquify(IdString(it.second.second)); log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); } @@ -79,7 +79,7 @@ int autoname_worker(Module *module, const dict& wire_score) for (auto &it : proposed_wire_names) { if (best_score*2 < it.second.first) continue; - IdString n = module->uniquify(it.second.second); + IdString n = module->uniquify(IdString(it.second.second)); log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); } From 934c82254d8abd33ee8827b200ff005868737f74 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 22 Sep 2023 00:14:51 +0000 Subject: [PATCH 027/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a75af96b555..77f7b80fadf 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.33+56 +YOSYS_VER := 0.33+65 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From fedd12261fc6e3828baf6025a0d3af1931495eda Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 18 Sep 2023 18:56:30 +0200 Subject: [PATCH 028/240] booth: Move away from explicit `Wire` pointers To represent intermediate signals use the `SigBit`/`SigSpec` classes as is customary in the Yosys codebase. Do not pass around `Wire` pointers unless we have special reason to. --- passes/techmap/booth.cc | 442 ++++++++++++++++++---------------------- 1 file changed, 194 insertions(+), 248 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index e749168522d..fe9c1cec6c0 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -94,7 +94,7 @@ struct BoothPassWorker { } // Unary gate - RTLIL::Wire *mk_ugate1(const RTLIL::IdString &red_typ, std::string &name, RTLIL::Wire *ip1, std::string &op_name) + RTLIL::Wire *mk_ugate1(const RTLIL::IdString &red_typ, std::string &name, SigBit ip1, std::string &op_name) { std::string op_wire_name; if (op_name.empty()) @@ -112,7 +112,7 @@ struct BoothPassWorker { } // Binary gate - RTLIL::Wire *mk_ugate2(const RTLIL::IdString &red_typ, std::string &name, RTLIL::Wire *ip1, RTLIL::Wire *ip2, std::string &op_name) + RTLIL::Wire *mk_ugate2(const RTLIL::IdString &red_typ, std::string &name, SigBit ip1, SigBit ip2, std::string &op_name) { auto g = module->addCell(new_id(name, __LINE__, ""), red_typ); std::string op_wire_name; @@ -135,7 +135,7 @@ struct BoothPassWorker { } // Booth unsigned decoder lsb - void BuildBur4d_lsb(std::string &name, RTLIL::Wire *lsb_i, RTLIL::Wire *one_i, RTLIL::Wire *s_i, RTLIL::Wire *&ppij_o, + void BuildBur4d_lsb(std::string &name, SigBit lsb_i, SigBit one_i, SigBit s_i, SigBit &ppij_o, std::string op_wire_name) { std::string empty; @@ -144,8 +144,8 @@ struct BoothPassWorker { } // Booth unsigned radix4 decoder - void BuildBur4d_n(std::string &name, RTLIL::Wire *yn_i, RTLIL::Wire *ynm1_i, RTLIL::Wire *one_i, RTLIL::Wire *two_i, RTLIL::Wire *s_i, - RTLIL::Wire *&ppij_o) + void BuildBur4d_n(std::string &name, SigBit yn_i, SigBit ynm1_i, SigBit one_i, SigBit two_i, SigBit s_i, + SigBit &ppij_o) { // ppij = ((yn & one) | (ynm1 & two)) ^ s; std::string empty; @@ -156,7 +156,7 @@ struct BoothPassWorker { } // Booth unsigned radix4 decoder - void BuildBur4d_msb(std::string &name, RTLIL::Wire *msb_i, RTLIL::Wire *two_i, RTLIL::Wire *s_i, RTLIL::Wire *&ppij_o) + void BuildBur4d_msb(std::string &name, SigBit msb_i, SigBit two_i, SigBit s_i, SigBit &ppij_o) { // ppij = (msb & two) ^ s; std::string empty; @@ -165,7 +165,7 @@ struct BoothPassWorker { } // half adder, used in CPA - void BuildHa(std::string &name, RTLIL::Wire *a_i, RTLIL::Wire *b_i, RTLIL::Wire *&s_o, RTLIL::Wire *&c_o) + void BuildHa(std::string &name, SigBit a_i, SigBit b_i, SigBit &s_o, SigBit &c_o) { std::string empty; s_o = mk_ugate2(ID($xor), name, a_i, b_i, empty); @@ -173,9 +173,8 @@ struct BoothPassWorker { } // Booth unsigned radix 4 encoder - void BuildBur4e(std::string &name, RTLIL::Wire *y0_i, RTLIL::Wire *y1_i, RTLIL::Wire *y2_i, - - RTLIL::Wire *&one_o, RTLIL::Wire *&two_o, RTLIL::Wire *&s_o, RTLIL::Wire *&sb_o) + void BuildBur4e(std::string &name, SigBit y0_i, SigBit y1_i, SigBit y2_i, + SigBit &one_o, SigBit &two_o, SigBit &s_o, SigBit &sb_o) { std::string empty; @@ -186,11 +185,10 @@ struct BoothPassWorker { two_o = mk_ugate1(ID($not), name, mk_ugate2(ID($or), name, inv_y1_xor_y2, one_o, empty), empty); } - void BuildBr4e(std::string &name, RTLIL::Wire *y2_m1_i, - RTLIL::Wire *y2_i, // y2i - RTLIL::Wire *y2_p1_i, - - RTLIL::Wire *&negi_o, RTLIL::Wire *&twoi_n_o, RTLIL::Wire *&onei_n_o, RTLIL::Wire *&cori_o) + void BuildBr4e(std::string &name, SigBit y2_m1_i, + SigBit y2_i, // y2i + SigBit y2_p1_i, + SigBit &negi_o, SigBit &twoi_n_o, SigBit &onei_n_o, SigBit &cori_o) { std::string empty; @@ -217,9 +215,8 @@ struct BoothPassWorker { // // signed booth radix 4 decoder // - void BuildBr4d(std::string &name, RTLIL::Wire *nxj_m1_i, RTLIL::Wire *twoi_n_i, RTLIL::Wire *xj_i, RTLIL::Wire *negi_i, RTLIL::Wire *onei_n_i, - - RTLIL::Wire *&ppij_o, RTLIL::Wire *&nxj_o) + void BuildBr4d(std::string &name, SigBit nxj_m1_i, SigBit twoi_n_i, SigBit xj_i, SigBit negi_i, SigBit onei_n_i, + SigBit &ppij_o, SigBit &nxj_o) { std::string empty; @@ -227,8 +224,8 @@ struct BoothPassWorker { // nxj_o = xnj_in, // ppij = ~( (nxj_m1_i | twoi_n_i) & (nxj_int | onei_n_i)); nxj_o = mk_ugate2(ID($xnor), name, xj_i, negi_i, empty); - RTLIL::Wire *or1 = mk_ugate2(ID($or), name, nxj_m1_i, twoi_n_i, empty); - RTLIL::Wire *or2 = mk_ugate2(ID($or), name, nxj_o, onei_n_i, empty); + SigBit or1 = mk_ugate2(ID($or), name, nxj_m1_i, twoi_n_i, empty); + SigBit or2 = mk_ugate2(ID($or), name, nxj_o, onei_n_i, empty); ppij_o = mk_ugate1(ID($not), name, mk_ugate2(ID($and), name, or1, or2, empty), empty); } @@ -237,12 +234,9 @@ struct BoothPassWorker { using non-booth encoded logic. We can save a booth encoder for the first couple of bits. */ - void BuildBoothQ1(std::string &name, RTLIL::Wire *negi_i, RTLIL::Wire *cori_i, RTLIL::Wire *x0_i, RTLIL::Wire *x1_i, RTLIL::Wire *y0_i, - RTLIL::Wire *y1_i, - - RTLIL::Wire *&nxj_o, RTLIL::Wire *&cor_o, RTLIL::Wire *&pp0_o, RTLIL::Wire *&pp1_o - - ) + void BuildBoothQ1(std::string &name, SigBit negi_i, SigBit cori_i, SigBit x0_i, SigBit x1_i, SigBit y0_i, + SigBit y1_i, + SigBit &nxj_o, SigBit &cor_o, SigBit &pp0_o, SigBit &pp1_o) { /* assign NXJO = ~(X1 ^ NEGI); @@ -258,11 +252,11 @@ struct BoothPassWorker { std::string empty; nxj_o = mk_ugate2(ID($xnor), name, x1_i, negi_i, empty); pp0_o = mk_ugate2(ID($and), name, x0_i, y0_i, empty); - RTLIL::Wire *pp1_1_int = mk_ugate2(ID($and), name, x1_i, y0_i, empty); - RTLIL::Wire *pp1_2_int = mk_ugate2(ID($and), name, x0_i, y1_i, empty); + SigBit pp1_1_int = mk_ugate2(ID($and), name, x1_i, y0_i, empty); + SigBit pp1_2_int = mk_ugate2(ID($and), name, x0_i, y1_i, empty); pp1_o = mk_ugate2(ID($xor), name, pp1_1_int, pp1_2_int, empty); - RTLIL::Wire *pp1_nor_pp0 = mk_ugate1(ID($not), name, mk_ugate2(ID($or), name, pp1_o, pp0_o, empty), empty); + SigBit pp1_nor_pp0 = mk_ugate1(ID($not), name, mk_ugate2(ID($or), name, pp1_o, pp0_o, empty), empty); cor_o = mk_ugate2(ID($and), name, pp1_nor_pp0, cori_i, empty); } @@ -355,13 +349,13 @@ struct BoothPassWorker { buf->setPort(ID::Y, SigSpec(Y)); if (is_signed == false) /* unsigned multiplier */ - CreateBoothUMult(module, x_sz_revised, y_sz_revised, required_op_size, + CreateBoothUMult(module, expanded_A, // multiplicand expanded_B, // multiplier(scanned) expanded_Y // result ); else /*signed multiplier */ - CreateBoothSMult(module, x_sz_revised, y_sz_revised, required_op_size, + CreateBoothSMult(module, expanded_A, // multiplicand expanded_B, // multiplier(scanned) expanded_Y // result (sized) @@ -382,19 +376,17 @@ struct BoothPassWorker { extra row of decoders and extended multiplier */ - void CreateBoothUMult(RTLIL::Module *module, int x_sz, int y_sz, int z_sz, - RTLIL::Wire *X, // multiplicand - RTLIL::Wire *Y, // multiplier - RTLIL::Wire *Z) + void CreateBoothUMult(RTLIL::Module *module, + SigSpec X, // multiplicand + SigSpec Y, // multiplier + SigSpec Z) { // result + int x_sz = X.size(), z_sz = Z.size(); - std::vector one_int; - std::vector two_int; - std::vector s_int; - std::vector sb_int; + SigSpec one_int, two_int, s_int, sb_int; int encoder_count = 0; - BuildBoothUMultEncoders(Y, y_sz, one_int, two_int, s_int, sb_int, module, encoder_count); + BuildBoothUMultEncoders(Y, one_int, two_int, s_int, sb_int, module, encoder_count); // Build the decoder rows // format of each Partial product to be passed to CSA @@ -404,31 +396,10 @@ struct BoothPassWorker { // Shift // Sign bit to be added // - std::vector, int, RTLIL::Wire *>> ppij_int; - - static int constant_ix; - constant_ix++; - std::string buf_name = "constant_buf_" + std::to_string(constant_ix); - auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - RTLIL::Wire *constant_one = module->addWire(new_id(buf_name, __LINE__, ""), 1); - buf->setPort(ID::A, State::S1); - buf->setParam(ID::A_WIDTH, 1); - buf->setParam(ID::Y_WIDTH, 1); - buf->setParam(ID::A_SIGNED, true); - buf->setPort(ID::Y, constant_one); - - constant_ix++; - buf_name = "constant_buf_" + std::to_string(constant_ix); - buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - RTLIL::Wire *constant_zero = module->addWire(new_id(buf_name, __LINE__, ""), 1); - buf->setPort(ID::A, State::S0); - buf->setParam(ID::A_WIDTH, 1); - buf->setParam(ID::Y_WIDTH, 1); - buf->setParam(ID::A_SIGNED, true); - buf->setPort(ID::Y, constant_zero); + std::vector> ppij_int; // Row 0: special case 1. Format S/.S.S.C.Data - std::vector ppij_row_0; + SigSpec ppij_row_0; BuildBoothUMultDecoderRow0(module, X, s_int, sb_int, one_int, two_int, ppij_row_0); // data, shift, sign @@ -436,11 +407,11 @@ struct BoothPassWorker { for (int i = 1; i < encoder_count - 2; i++) { // format 1,S.Data.shift = encoder_ix*2,sign = sb_int[i] - std::vector ppij_row_n; + SigSpec ppij_row_n; BuildBoothUMultDecoderRowN(module, X, // multiplicand - one_int[i], two_int[i], s_int[i], sb_int[i], ppij_row_n, constant_one, i, + one_int[i], two_int[i], s_int[i], sb_int[i], ppij_row_n, i, false, // include sign false // include constant ); @@ -450,18 +421,18 @@ struct BoothPassWorker { // Build second to last row // format S/,Data + sign bit - std::vector ppij_row_em1; + SigSpec ppij_row_em1; BuildBoothUMultDecoderRowN(module, X, one_int[encoder_count - 2], two_int[encoder_count - 2], s_int[encoder_count - 2], - sb_int[encoder_count - 2], ppij_row_em1, constant_one, encoder_count - 2, + sb_int[encoder_count - 2], ppij_row_em1, encoder_count - 2, false, // include sign true // no constant ); ppij_int.push_back(std::make_tuple(ppij_row_em1, (encoder_count - 2) * 2, s_int[encoder_count - 2])); // Build last row // format Data + sign bit - std::vector ppij_row_e; + SigSpec ppij_row_e; BuildBoothUMultDecoderRowN(module, X, one_int[encoder_count - 1], two_int[encoder_count - 1], s_int[encoder_count - 1], - sb_int[encoder_count - 1], ppij_row_e, constant_one, encoder_count - 1, + sb_int[encoder_count - 1], ppij_row_e, encoder_count - 1, true, // no sign true // no constant ); @@ -471,13 +442,13 @@ struct BoothPassWorker { // DebugDumpPP(ppij_int); // Summation of Partial Products (Wallace Tree) - std::vector> aligned_pp; + std::vector aligned_pp; aligned_pp.resize(encoder_count + 1); // make an entirely redundant row // just for sign bit in lsb. (We then filter this out). // resize all to be same size as z for (int i = 0; i < encoder_count + 1; i++) - aligned_pp[i].resize(z_sz); + aligned_pp[i].extend_u0(z_sz); AlignPP(x_sz, z_sz, ppij_int, aligned_pp); @@ -485,8 +456,8 @@ struct BoothPassWorker { // Later on yosys will clean up unused constants // DebugDumpAlignPP(aligned_pp); - std::vector s_vec; - std::vector c_vec; + SigSpec s_vec; + SigSpec c_vec; std::vector> debug_csa_trees; debug_csa_trees.resize(z_sz); @@ -504,9 +475,9 @@ struct BoothPassWorker { */ void BuildBoothUMultDecoderRow0(RTLIL::Module *module, - RTLIL::Wire *X, // multiplicand - std::vector &s_int, std::vector &sb_int, std::vector &one_int, - std::vector &two_int, std::vector &ppij_vec) + SigSpec X, // multiplicand + SigSpec s_int, SigSpec sb_int, SigSpec one_int, + SigSpec two_int, SigSpec &ppij_vec) { (void)module; int x_sz = GetSize(X); @@ -514,73 +485,72 @@ struct BoothPassWorker { // lsb std::string dec_name = "row0_lsb_dec"; - RTLIL::Wire *ppij; + SigBit ppij; std::string ppij_name = "ppij_0_0"; - BuildBur4d_lsb(dec_name, mk_wireFromSigSpec(SigSpec(X, 0, 1)), one_int[0], s_int[0], ppij, ppij_name); - ppij_vec.push_back(ppij); + BuildBur4d_lsb(dec_name, X[0], one_int[0], s_int[0], ppij, ppij_name); + ppij_vec.append(ppij); // 1..xsize -1 for (int i = 1; i < x_sz; i++) { dec_name = "row0_dec_" + std::to_string(i); - RTLIL::Wire *ppij; - BuildBur4d_n(dec_name, mk_wireFromSigSpec(SigSpec(X, i, 1)), mk_wireFromSigSpec(SigSpec(X, i - 1, 1)), one_int[0], two_int[0], + SigBit ppij; + BuildBur4d_n(dec_name, X[i], X[i - 1], one_int[0], two_int[0], s_int[0], ppij); - ppij_vec.push_back(ppij); + ppij_vec.append(ppij); } // The redundant bit. Duplicate decoding of last bit. dec_name = "row0_dec_msb"; - BuildBur4d_msb(dec_name, mk_wireFromSigSpec(SigSpec(X, x_sz - 1, 1)), two_int[0], s_int[0], ppij); - ppij_vec.push_back(ppij); + BuildBur4d_msb(dec_name, X[x_sz - 1], two_int[0], s_int[0], ppij); + ppij_vec.append(ppij); // append the sign bits - ppij_vec.push_back(s_int[0]); - ppij_vec.push_back(s_int[0]); - ppij_vec.push_back(sb_int[0]); + ppij_vec.append(s_int[0]); + ppij_vec.append(s_int[0]); + ppij_vec.append(sb_int[0]); } // Build a generic row of decoders. void BuildBoothUMultDecoderRowN(RTLIL::Module *module, - RTLIL::Wire *X, // multiplicand - RTLIL::Wire *one_int, RTLIL::Wire *two_int, RTLIL::Wire *s_int, RTLIL::Wire *sb_int, - std::vector &ppij_vec, RTLIL::Wire *constant_one, int row_ix, bool no_sign, bool no_constant) + SigSpec X, // multiplicand + SigSpec one_int, SigSpec two_int, SigSpec s_int, SigSpec sb_int, + SigSpec &ppij_vec, int row_ix, bool no_sign, bool no_constant) { (void)module; int x_sz = GetSize(X); // lsb std::string ppij_name = "ppij_" + std::to_string(row_ix) + "_0"; - RTLIL::Wire *ppij = nullptr; + SigBit ppij; std::string empty; std::string dec_name = "row" + std::to_string(row_ix) + "_lsb_dec"; - BuildBur4d_lsb(dec_name, mk_wireFromSigSpec(SigSpec(X, 0, 1)), one_int, s_int, ppij, empty); + BuildBur4d_lsb(dec_name, X[0], one_int, s_int, ppij, empty); - ppij_vec.push_back(ppij); + ppij_vec.append(ppij); // core bits for (int i = 1; i < x_sz; i++) { dec_name = "row_" + std::to_string(row_ix) + "_dec_" + std::to_string(i); - RTLIL::Wire *ppij = nullptr; - BuildBur4d_n(dec_name, mk_wireFromSigSpec(SigSpec(X, i, 1)), mk_wireFromSigSpec(SigSpec(X, i - 1, 1)), one_int, two_int, - s_int, ppij); - ppij_vec.push_back(ppij); + BuildBur4d_n(dec_name, X[i], X[i - 1], + one_int, two_int, s_int, ppij); + ppij_vec.append(ppij); } // redundant bit dec_name = "row_dec_red"; - BuildBur4d_msb(dec_name, mk_wireFromSigSpec(SigSpec(X, x_sz - 1, 1)), two_int, s_int, ppij); - ppij_vec.push_back(ppij); + BuildBur4d_msb(dec_name, X[x_sz - 1], two_int, s_int, ppij); + ppij_vec.append(ppij); // sign bit if (no_sign == false) // if no sign is false then make a sign bit - ppij_vec.push_back(sb_int); + ppij_vec.append(sb_int); // constant bit if (no_constant == false) { // if non constant is false make a constant bit - ppij_vec.push_back(constant_one); + ppij_vec.append(State::S1); } } @@ -663,8 +633,8 @@ struct BoothPassWorker { } } - void BuildCSATree(RTLIL::Module *module, std::vector> &bits_to_reduce, std::vector &s_vec, - std::vector &c_vec, std::vector> &debug_csa_trees) + void BuildCSATree(RTLIL::Module *module, std::vector &bits_to_reduce, SigSpec &s_vec, + SigSpec &c_vec, std::vector> &debug_csa_trees) { if (!(bits_to_reduce.size() > 0)) @@ -672,24 +642,24 @@ struct BoothPassWorker { int column_size = bits_to_reduce[0].size(); int row_size = bits_to_reduce.size(); - std::vector carry_bits_to_add_to_next_column; + SigSpec carry_bits_to_add_to_next_column; for (int column_ix = 0; column_ix < column_size; column_ix++) { // get the bits in this column. - std::vector column_bits; + SigSpec column_bits; for (int row_ix = 0; row_ix < row_size; row_ix++) { - if (bits_to_reduce[row_ix].at(column_ix)) - column_bits.push_back(bits_to_reduce[row_ix].at(column_ix)); + if (bits_to_reduce[row_ix][column_ix].wire) + column_bits.append(bits_to_reduce[row_ix][column_ix]); } for (auto c : carry_bits_to_add_to_next_column) { #ifdef DEBUG_CSA printf("\t Propagating column bit %s to column %d from column %d\n", c->name.c_str(), column_ix, column_ix - 1); #endif - column_bits.push_back(c); + column_bits.append(c); } - carry_bits_to_add_to_next_column.resize(0); + carry_bits_to_add_to_next_column = {}; #ifdef DEBUG_CSA printf("Column %d Reducing %d bits\n", column_ix, column_bits.size()); @@ -699,16 +669,15 @@ struct BoothPassWorker { printf("\n"); #endif - RTLIL::Wire *s = nullptr; - RTLIL::Wire *c = nullptr; + SigBit s, c; #ifdef DEBUG_CSA int csa_count_before = debug_csa_trees[column_ix].size(); #endif ReduceBits(module, column_ix, column_bits, s, c, carry_bits_to_add_to_next_column, debug_csa_trees); - s_vec.push_back(s); - c_vec.push_back(c); + s_vec.append(s); + c_vec.append(c); #ifdef DEBUG_CSA int csa_count_after = debug_csa_trees[column_ix].size(); @@ -738,8 +707,8 @@ struct BoothPassWorker { Pad out rows with zeros and left the opt pass clean them up. */ - void AlignPP(int x_sz, int z_sz, std::vector, int, RTLIL::Wire *>> &ppij_int, - std::vector> &aligned_pp) + void AlignPP(int x_sz, int z_sz, std::vector> &ppij_int, + std::vector &aligned_pp) { unsigned aligned_pp_ix = aligned_pp.size() - 1; @@ -748,7 +717,7 @@ struct BoothPassWorker { for (unsigned i = 0; i < aligned_pp.size(); i++) { for (int j = 0; j < z_sz; j++) { - aligned_pp[i][j] = nullptr; + aligned_pp[i][j] = State::S0; } } @@ -758,21 +727,19 @@ struct BoothPassWorker { // in first column of the last partial product // which is at index corresponding to size of multiplicand { - RTLIL::Wire *prior_row_sign = nullptr; - prior_row_sign = get<2>(ppij_int[aligned_pp_ix - 1]); - if (prior_row_sign) { + SigBit prior_row_sign = get<2>(ppij_int[aligned_pp_ix - 1]); + //if (prior_row_sign) { log_assert(aligned_pp_ix < aligned_pp.size()); log_assert(x_sz - 1 < (int)(aligned_pp[aligned_pp_ix].size())); aligned_pp[aligned_pp_ix][x_sz - 1] = prior_row_sign; - } + //} } for (int row_ix = aligned_pp_ix - 1; row_ix >= 0; row_ix--) { int shift_amount = get<1>(ppij_int[row_ix]); - RTLIL::Wire *prior_row_sign = nullptr; // copy in data - unsigned copy_ix = shift_amount; + int copy_ix = shift_amount; for (auto w : get<0>(ppij_int[row_ix])) { if (copy_ix < aligned_pp[row_ix].size()) { aligned_pp[row_ix][copy_ix] = w; @@ -786,7 +753,7 @@ struct BoothPassWorker { // the destination of the sign bit is the (row_ix -1)*2 // eg destination for sign bit for row 0 is 0. // eg destination for sign bit for row 1 is 1 - prior_row_sign = get<2>(ppij_int[row_ix - 1]); + SigBit prior_row_sign = get<2>(ppij_int[row_ix - 1]); copy_ix = (row_ix - 1) * 2; aligned_pp[row_ix][copy_ix] = prior_row_sign; } @@ -797,32 +764,23 @@ struct BoothPassWorker { Build a Carry Propagate Adder ----------------------------- First build the sum and carry vectors to be added. - Axioms: - c_vec.size() == s_vec.size() - result.size() == s_vec.size() + 2; (assume result is reserved to hold correct size) */ - void BuildCPA(RTLIL::Module *module, std::vector &s_vec, std::vector &c_vec, RTLIL::Wire *result) + void BuildCPA(RTLIL::Module *module, SigSpec s_vec, SigSpec c_vec, SigSpec result) { - static int cpa_id; cpa_id++; - RTLIL::Wire *carry = nullptr; - - log_assert(s_vec.size() == c_vec.size()); + log_assert(c_vec.size() == s_vec.size()); + // TODO: doesn't pass + //log_assert(result.size() == s_vec.size() + 2); - for (unsigned n = 0; n < s_vec.size(); n++) { + SigBit carry; + for (int n = 0; n < s_vec.size(); n++) { std::string carry_name; // Base Case: Bit 0 is sum 0 if (n == 0) { - std::string buf_name = "base_buf_" + std::to_string(cpa_id) + "_" + std::to_string(n); - auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setPort(ID::A, s_vec[0]); - buf->setParam(ID::A_WIDTH, 1); - buf->setParam(ID::Y_WIDTH, 1); - buf->setParam(ID::A_SIGNED, false); - buf->setPort(ID::Y, SigSpec(result, 0, 1)); + module->addBufGate(NEW_ID_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]); #ifdef DEBUG_CPA printf("CPA bit [%d] Cell %s IP 0 %s \n", n, buf->name.c_str(), s_vec[0]->name.c_str()); @@ -835,10 +793,9 @@ struct BoothPassWorker { // else if (n == 1) { std::string ha_name = "cpa_" + std::to_string(cpa_id) + "_ha_" + std::to_string(n); - RTLIL::Wire *ha_op; + SigBit ha_op; BuildHa(ha_name, s_vec[n], c_vec[n - 1], ha_op, carry); - - module->connect(ha_op, SigSpec(result, n, 1)); + module->connect(result[n], ha_op); #ifdef DEBUG_CPA printf("CPA bit [%d] Cell %s IPs [%s] [%s] \n", n, ha_cell->name.c_str(), s_vec[n]->name.c_str(), @@ -847,9 +804,10 @@ struct BoothPassWorker { } // End Case - else if (n == (unsigned)((s_vec.size() - 1))) { + else if (n == s_vec.size() - 1) { // Make the carry results.. Two extra bits after fa. std::string fa_name = "cpa_" + std::to_string(cpa_id) + "_fa_" + std::to_string(n); + auto fa_cell = module->addCell(new_id(fa_name, __LINE__, ""), ID($fa)); fa_cell->setParam(ID::WIDTH, 1); carry_name = "cpa_" + std::to_string(cpa_id) + "carry_" + std::to_string(n); @@ -857,7 +815,7 @@ struct BoothPassWorker { fa_cell->setPort(ID::B, c_vec[n - 1]); fa_cell->setPort(ID::C, carry); // wire in result and carry out - fa_cell->setPort(ID::Y, SigSpec(result, n, 1)); + fa_cell->setPort(ID::Y, result[n]); // make a new carry bit for carry out... carry = module->addWire(new_id(carry_name, __LINE__, ""), 1); @@ -867,16 +825,16 @@ struct BoothPassWorker { printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.c_str(), s_vec[n]->name.c_str(), c_vec[n - 1]->name.c_str(), carry->name.c_str()); #endif - if (n + 1 < (unsigned)(GetSize(result))) { + if (n + 1 < GetSize(result)) { // Now make a half adder: c_vec[n] = carry std::string ha_name = "cpa_" + std::to_string(cpa_id) + "_ha_" + std::to_string(n); - RTLIL::Wire *ha_sum; - RTLIL::Wire *ha_carry; + SigBit ha_sum; + SigBit ha_carry; BuildHa(ha_name, c_vec[n], carry, ha_sum, ha_carry); - if (n + 1 < (unsigned)GetSize(result)) - module->connect(ha_sum, SigSpec(result, n + 1, 1)); - if (n + 2 < (unsigned)GetSize(result)) - module->connect(ha_carry, SigSpec(result, n + 2, 1)); + if (n + 1 < GetSize(result)) + module->connect(result[n + 1], ha_sum); + if (n + 2 < GetSize(result)) + module->connect(result[n + 2], ha_carry); } } // Step case @@ -890,7 +848,7 @@ struct BoothPassWorker { fa_cell->setPort(ID::B, c_vec[n - 1]); fa_cell->setPort(ID::C, carry); // wire in result and carry out - fa_cell->setPort(ID::Y, SigSpec(result, n, 1)); + fa_cell->setPort(ID::Y, result[n]); // make a new carry bit for carry out... carry = module->addWire(new_id(carry_name, __LINE__, ""), 1); fa_cell->setPort(ID::X, carry); @@ -907,8 +865,8 @@ struct BoothPassWorker { // Pass the carry bits from each csa to the next // column for summation. - void ReduceBits(RTLIL::Module *module, int column_ix, std::vector &column_bits, RTLIL::Wire *&s_result, RTLIL::Wire *&c_result, - std::vector &carry_bits_to_sum, std::vector> &debug_csa_trees) + void ReduceBits(RTLIL::Module *module, int column_ix, SigSpec column_bits, SigBit &s_result, SigBit &c_result, + SigSpec &carry_bits_to_sum, std::vector> &debug_csa_trees) { int csa_ix = 0; @@ -918,12 +876,12 @@ struct BoothPassWorker { unique_id++; if (column_size > 0) { - unsigned var_ix = 0; - std::vector first_csa_ips; + int var_ix = 0; + SigSpec first_csa_ips; // get the first 3 inputs, if possible for (var_ix = 0; var_ix < column_bits.size() && first_csa_ips.size() != 3; var_ix++) { - if (column_bits[var_ix]) - first_csa_ips.push_back(column_bits[var_ix]); + if (column_bits[var_ix].is_wire()) + first_csa_ips.append(column_bits[var_ix]); } if (first_csa_ips.size() > 0) { @@ -961,16 +919,16 @@ struct BoothPassWorker { c_result = c_wire; if (var_ix <= column_bits.size() - 1) - carry_bits_to_sum.push_back(c_wire); + carry_bits_to_sum.append(c_wire); // Now build the rest of the tree if we can while (var_ix <= column_bits.size() - 1) { - std::vector csa_ips; + SigSpec csa_ips; // get the next two variables to sum for (; var_ix <= column_bits.size() - 1 && csa_ips.size() < 2;) { // skip any empty bits - if (column_bits[var_ix] != nullptr) - csa_ips.push_back(column_bits[var_ix]); + if (column_bits[var_ix].is_wire()) + csa_ips.append(column_bits[var_ix]); var_ix++; } @@ -993,7 +951,7 @@ struct BoothPassWorker { c_wire = module->addWire(new_id(carry_wire_name, __LINE__, ""), 1); if (var_ix <= column_bits.size() - 1) - carry_bits_to_sum.push_back(c_wire); + carry_bits_to_sum.append(c_wire); sum_wire_name = "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix) + "_s"; s_wire = module->addWire(new_id(sum_wire_name, __LINE__, ""), 1); @@ -1009,28 +967,30 @@ struct BoothPassWorker { } } - void BuildBoothUMultEncoders(RTLIL::Wire *Y, int y_sz, std::vector &one_int, std::vector &two_int, - std::vector &s_int, std::vector &sb_int, RTLIL::Module *module, int &encoder_ix) + void BuildBoothUMultEncoders(SigSpec Y, SigSpec &one_int, SigSpec &two_int, + SigSpec &s_int, SigSpec &sb_int, RTLIL::Module *module, int &encoder_ix) { + int y_sz = GetSize(Y); + for (int y_ix = 0; y_ix < y_sz;) { std::string enc_name = "bur_enc_" + std::to_string(encoder_ix) + "_"; std::string two_name = "two_int" + std::to_string(encoder_ix); - two_int.push_back(module->addWire(new_id(two_name, __LINE__, ""), 1)); + two_int.append(module->addWire(new_id(two_name, __LINE__, ""), 1)); std::string one_name = "one_int" + std::to_string(encoder_ix); - one_int.push_back(module->addWire(new_id(one_name, __LINE__, ""), 1)); + one_int.append(module->addWire(new_id(one_name, __LINE__, ""), 1)); std::string s_name = "s_int" + std::to_string(encoder_ix); - s_int.push_back(module->addWire(new_id(s_name, __LINE__, ""), 1)); + s_int.append(module->addWire(new_id(s_name, __LINE__, ""), 1)); std::string sb_name = "sb_int" + std::to_string(encoder_ix); - sb_int.push_back(module->addWire(new_id(sb_name, __LINE__, ""), 1)); + sb_int.append(module->addWire(new_id(sb_name, __LINE__, ""), 1)); if (y_ix == 0) { - BuildBur4e(enc_name, mk_wireFromSigSpec(State::S0), mk_wireFromSigSpec(SigSpec(Y, y_ix, 1)), - mk_wireFromSigSpec(SigSpec(Y, y_ix + 1, 1)), one_int[encoder_ix], two_int[encoder_ix], s_int[encoder_ix], + BuildBur4e(enc_name, State::S0, Y[y_ix], + Y[y_ix + 1], one_int[encoder_ix], two_int[encoder_ix], s_int[encoder_ix], sb_int[encoder_ix]); y_ix = y_ix + 1; @@ -1041,39 +1001,37 @@ struct BoothPassWorker { // then add an extra booth encoder bounded by // zeroes to ensure unsigned works. // - RTLIL::Wire *y0_wire; - RTLIL::Wire *y1_wire; - RTLIL::Wire *y2_wire; + SigBit y0, y1, y2; bool need_padded_cell = false; if (y_ix > y_sz - 1) { - y0_wire = mk_wireFromSigSpec(SigSpec(Y, State::S0)); + y0 = State::S0; need_padded_cell = false; } else { - y0_wire = mk_wireFromSigSpec(SigSpec(Y, y_ix, 1)); + y0 = Y[y_ix]; y_ix++; } if (y_ix > y_sz - 1) { need_padded_cell = false; - y1_wire = mk_wireFromSigSpec(SigSpec(Y, State::S0)); + y1 = State::S0; } else { - y1_wire = mk_wireFromSigSpec(SigSpec(Y, y_ix, 1)); + y1 = Y[y_ix]; y_ix++; } if (y_ix > y_sz - 1) { need_padded_cell = false; - y2_wire = mk_wireFromSigSpec(SigSpec(Y, State::S0)); + y2 = State::S0; } else { if (y_ix == y_sz - 1) need_padded_cell = true; else need_padded_cell = false; - y2_wire = mk_wireFromSigSpec(SigSpec(Y, y_ix, 1)); + y2 = Y[y_ix]; - BuildBur4e(enc_name, y0_wire, y1_wire, y2_wire, one_int[encoder_ix], two_int[encoder_ix], s_int[encoder_ix], + BuildBur4e(enc_name, y0, y1, y2, one_int[encoder_ix], two_int[encoder_ix], s_int[encoder_ix], sb_int[encoder_ix]); } @@ -1087,25 +1045,25 @@ struct BoothPassWorker { std::string enc_name = "br_enc_pad" + std::to_string(encoder_ix) + "_"; std::string two_name = "two_int" + std::to_string(encoder_ix); - two_int.push_back(module->addWire(new_id(two_name, __LINE__, ""), 1)); + two_int.append(module->addWire(new_id(two_name, __LINE__, ""), 1)); std::string one_name = "one_int" + std::to_string(encoder_ix); - one_int.push_back(module->addWire(new_id(two_name, __LINE__, ""), 1)); + one_int.append(module->addWire(new_id(two_name, __LINE__, ""), 1)); std::string s_name = "s_int" + std::to_string(encoder_ix); - s_int.push_back(module->addWire(new_id(s_name, __LINE__, ""), 1)); + s_int.append(module->addWire(new_id(s_name, __LINE__, ""), 1)); std::string sb_name = "sb_int" + std::to_string(encoder_ix); - sb_int.push_back(module->addWire(new_id(sb_name, __LINE__, ""), 1)); + sb_int.append(module->addWire(new_id(sb_name, __LINE__, ""), 1)); - RTLIL::Wire *one_o_int, *two_o_int, *s_o_int, *sb_o_int; - BuildBur4e(enc_name, mk_wireFromSigSpec(SigSpec(Y, y_ix, 1)), mk_wireFromSigSpec(State::S0), - mk_wireFromSigSpec(State::S0), one_o_int, two_o_int, s_o_int, sb_o_int); + SigBit one_o_int, two_o_int, s_o_int, sb_o_int; + BuildBur4e(enc_name, Y[y_ix], State::S0, + State::S0, one_o_int, two_o_int, s_o_int, sb_o_int); - join_wires_with_buffer(one_o_int, one_int[encoder_ix]); - join_wires_with_buffer(two_o_int, two_int[encoder_ix]); - join_wires_with_buffer(s_o_int, s_int[encoder_ix]); - join_wires_with_buffer(sb_o_int, sb_int[encoder_ix]); + module->connect(one_int[encoder_ix], one_o_int); + module->connect(two_int[encoder_ix], two_o_int); + module->connect(s_int[encoder_ix], s_o_int); + module->connect(sb_int[encoder_ix], sb_o_int); y_ix++; encoder_ix++; } @@ -1116,8 +1074,10 @@ struct BoothPassWorker { /* Signed Multiplier */ - void CreateBoothSMult(RTLIL::Module *module, int x_sz, int y_sz, int z_sz, RTLIL::Wire *X, RTLIL::Wire *Y, RTLIL::Wire *Z) + void CreateBoothSMult(RTLIL::Module *module, SigSpec X, SigSpec Y, SigSpec Z) { // product + int x_sz = X.size(), y_sz = Y.size(), z_sz = Z.size(); + unsigned enc_count = (y_sz / 2) + (((y_sz % 2) != 0) ? 1 : 0); int dec_count = x_sz + 1; @@ -1128,10 +1088,12 @@ struct BoothPassWorker { "Result of size %d. %d encoders %d decoders\n", x_sz, y_sz, z_sz, enc_count, dec_count); - RTLIL::Wire **negi_n_int = new RTLIL::Wire *[enc_count]; - RTLIL::Wire **twoi_n_int = new RTLIL::Wire *[enc_count]; - RTLIL::Wire **onei_n_int = new RTLIL::Wire *[enc_count]; - RTLIL::Wire **cori_n_int = new RTLIL::Wire *[enc_count]; + SigSpec negi_n_int, twoi_n_int, onei_n_int, cori_n_int; + + negi_n_int.extend_u0(enc_count); + twoi_n_int.extend_u0(enc_count); + onei_n_int.extend_u0(enc_count); + cori_n_int.extend_u0(enc_count); for (unsigned encoder_ix = 1; encoder_ix <= enc_count; encoder_ix++) { std::string enc_name = "enc_" + std::to_string(encoder_ix) + "_"; @@ -1146,38 +1108,34 @@ struct BoothPassWorker { if (encoder_ix == 1) { - BuildBr4e(enc_name, mk_wireFromSigSpec(SigSpec(State::S0)), mk_wireFromSigSpec(SigSpec(Y, 0, 1)), - mk_wireFromSigSpec(SigSpec(Y, 1, 1)), - + BuildBr4e(enc_name, State::S0, Y[0], Y[1], negi_n_int[encoder_ix - 1], twoi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], cori_n_int[encoder_ix - 1]); } else { - RTLIL::Wire *y1_wire; - RTLIL::Wire *y2_wire; - RTLIL::Wire *y3_wire; + SigBit y1, y2, y3; + + y1 = Y[(encoder_ix - 1) * 2 - 1]; - y1_wire = mk_wireFromSigSpec(SigSpec(Y, ((encoder_ix - 1) * 2 - 1), 1)); //-1 if ((encoder_ix - 1) * 2 >= (unsigned)y_sz) - y2_wire = mk_wireFromSigSpec(SigSpec(State::S0)); // constant 0 + y2 = State::S0; // constant 0 else - y2_wire = mk_wireFromSigSpec(SigSpec(Y, ((encoder_ix - 1) * 2), 1)); // 0 + y2 = Y[(encoder_ix - 1) * 2]; // 0 if (((encoder_ix - 1) * 2 + 1) >= (unsigned)y_sz) - y3_wire = mk_wireFromSigSpec(SigSpec(State::S0)); // constant 0 + y3 = State::S0; // constant 0 else - y3_wire = mk_wireFromSigSpec(SigSpec(Y, ((encoder_ix - 1) * 2 + 1), 1)); //+1 - - BuildBr4e(enc_name, y1_wire, y2_wire, y3_wire, + y3 = Y[(encoder_ix - 1) * 2 + 1]; //+1 + BuildBr4e(enc_name, y1, y2, y3, negi_n_int[encoder_ix - 1], twoi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], cori_n_int[encoder_ix - 1]); } } // Decoders and PP generation - RTLIL::Wire **PPij = new RTLIL::Wire *[enc_count * dec_count]; - RTLIL::Wire **nxj = new RTLIL::Wire *[enc_count * dec_count]; + SigSpec PPij(State::S0, enc_count * dec_count); + SigSpec nxj(State::S0, enc_count * dec_count); for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) { for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) { @@ -1220,16 +1178,16 @@ struct BoothPassWorker { std::string dec_name = "dec_" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; BuildBr4d(dec_name, nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1], twoi_n_int[encoder_ix - 1], - mk_wireFromSigSpec(SigSpec(X, decoder_ix - 1, 1)), negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], + X[decoder_ix - 1], negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1], nxj[((encoder_ix - 1) * dec_count) + decoder_ix]); } // duplicate end for sign fix // applies to 9th decoder (xsz+1 decoder). std::string dec_name = "dec_" + std::to_string(encoder_ix) + "_" + std::to_string(x_sz + 1) + "_"; - RTLIL::Wire *unused_op = nullptr; + SigBit unused_op; BuildBr4d(dec_name, nxj[((encoder_ix - 1) * dec_count) + dec_count - 1], twoi_n_int[encoder_ix - 1], - mk_wireFromSigSpec(SigSpec(X, dec_count - 2, 1)), negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], + X[dec_count - 2], negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], PPij[((encoder_ix - 1) * dec_count) + dec_count - 1], unused_op); } @@ -1239,8 +1197,8 @@ struct BoothPassWorker { int fa_el_ix = 0; int fa_row_ix = 0; // use 1 d arrays (2d cannot have variable sized indices) - RTLIL::Wire **fa_sum_n = new RTLIL::Wire *[fa_row_count * fa_count]; - RTLIL::Wire **fa_carry_n = new RTLIL::Wire *[fa_row_count * fa_count]; + SigSpec fa_sum_n(State::S0, fa_row_count * fa_count); + SigSpec fa_carry_n(State::S0, fa_row_count * fa_count); for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) { for (fa_el_ix = 0; fa_el_ix < fa_count; fa_el_ix++) { @@ -1416,11 +1374,11 @@ struct BoothPassWorker { } // instantiate the cpa - RTLIL::Wire **cpa_carry = new RTLIL::Wire *[z_sz]; + SigSpec cpa_carry; for (int cix = 0; cix < z_sz; cix++) { std::string cpa_cix_name = "cpa_carry_" + std::to_string(cix) + "_"; - cpa_carry[cix] = module->addWire(new_id(cpa_cix_name, __LINE__, ""), 1); + cpa_carry.append(module->addWire(new_id(cpa_cix_name, __LINE__, ""), 1)); } for (int cpa_ix = 0; cpa_ix < z_sz; cpa_ix++) { @@ -1439,7 +1397,7 @@ struct BoothPassWorker { buf->setParam(ID::A_WIDTH, 1); buf->setParam(ID::Y_WIDTH, 1); buf->setParam(ID::A_SIGNED, true); - buf->setPort(ID::Y, SigSpec(Z, cpa_ix, 1)); + buf->setPort(ID::Y, Z[cpa_ix]); cpa_ix++; buf_name = "pp_buf_" + std::to_string(cpa_ix) + "_" + "driven_by_fa_row_" + std::to_string(fa_row_ix) + "_"; @@ -1448,22 +1406,22 @@ struct BoothPassWorker { buf->setParam(ID::A_WIDTH, 1); buf->setParam(ID::Y_WIDTH, 1); buf->setParam(ID::A_SIGNED, true); - buf->setPort(ID::Y, SigSpec(Z, cpa_ix, 1)); + buf->setPort(ID::Y, Z[cpa_ix]); } else { int offset = fa_row_count * 2; bool base_case = cpa_ix - offset == 0 ? true : false; std::string cpa_name = "cpa_" + std::to_string(cpa_ix - offset) + "_"; - RTLIL::Wire *ci_wire; + SigBit ci; if (base_case) - ci_wire = cori_n_int[enc_count - 1]; + ci = cori_n_int[enc_count - 1]; else - ci_wire = cpa_carry[cpa_ix - offset - 1]; + ci = cpa_carry[cpa_ix - offset - 1]; - RTLIL::Wire *op_wire = module->addWire(NEW_ID, 1); - BuildHa(cpa_name, fa_sum_n[(fa_row_count - 1) * fa_count + cpa_ix - offset + 2], ci_wire, op_wire, + SigBit op; + BuildHa(cpa_name, fa_sum_n[(fa_row_count - 1) * fa_count + cpa_ix - offset + 2], ci, op, cpa_carry[cpa_ix - offset]); - module->connect(op_wire, SigSpec(Z, cpa_ix, 1)); + module->connect(Z[cpa_ix], op); } } @@ -1473,35 +1431,23 @@ struct BoothPassWorker { // std::string q1_name = "icb_booth_q1_"; - RTLIL::Wire *pp0_o_int; - RTLIL::Wire *pp1_o_int; - RTLIL::Wire *nxj_o_int; - RTLIL::Wire *cor_o_int; + SigBit pp0_o_int; + SigBit pp1_o_int; + SigBit nxj_o_int; + SigBit cor_o_int; BuildBoothQ1(q1_name, negi_n_int[0], // negi cori_n_int[0], // cori - mk_wireFromSigSpec(SigSpec(X, 0, 1)), // x0 - mk_wireFromSigSpec(SigSpec(X, 1, 1)), // x1 - mk_wireFromSigSpec(SigSpec(Y, 0, 1)), // y0 - mk_wireFromSigSpec(SigSpec(Y, 1, 1)), // y1 + X[0], X[1], Y[0], Y[1], nxj_o_int, cor_o_int, pp0_o_int, pp1_o_int); - join_wires_with_buffer(pp0_o_int, fa_sum_n[(0 * fa_count) + 0]); - join_wires_with_buffer(pp1_o_int, fa_sum_n[(0 * fa_count) + 1]); - join_wires_with_buffer(cor_o_int, fa_carry_n[(0 * fa_count) + 1]); - join_wires_with_buffer(nxj_o_int, nxj[(0 * dec_count) + 2]); - - delete[] negi_n_int; - delete[] twoi_n_int; - delete[] onei_n_int; - delete[] cori_n_int; - - delete[] fa_sum_n; - delete[] fa_carry_n; - delete[] cpa_carry; + module->connect(fa_sum_n[(0 * fa_count) + 0], pp0_o_int); + module->connect(fa_sum_n[(0 * fa_count) + 1], pp1_o_int); + module->connect(fa_carry_n[(0 * fa_count) + 1], cor_o_int); + module->connect(nxj[(0 * dec_count) + 2], nxj_o_int); } }; From cb05262fc4098507e7be1fd52fe666a606687f90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 19 Sep 2023 13:06:05 +0200 Subject: [PATCH 029/240] booth: Remove now-unused helpers --- passes/techmap/booth.cc | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index fe9c1cec6c0..2713d33956a 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -66,33 +66,6 @@ struct BoothPassWorker { BoothPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; } - // Helper routines for building architecture subcomponents - - RTLIL::Wire *mk_wireFromSigSpec(const SigSpec &v) - { - - auto g = module->addCell(NEW_ID, ID($pos)); - Wire *ret = module->addWire(NEW_ID, 1); - g->setPort(ID::A, v); - g->setPort(ID::Y, ret); - g->setParam(ID::A_WIDTH, 1); - g->setParam(ID::Y_WIDTH, 1); - g->setParam(ID::A_SIGNED, false); - return ret; - } - - // fuse wires. - void join_wires_with_buffer(RTLIL::Wire *ip, RTLIL::Wire *op) - { - std::string wire_name = "join_"; - auto g = module->addCell(new_id(wire_name, __LINE__, ""), ID($pos)); - g->setParam(ID::A_WIDTH, 1); - g->setParam(ID::Y_WIDTH, 1); - g->setParam(ID::A_SIGNED, false); - g->setPort(ID::A, ip); - g->setPort(ID::Y, op); - } - // Unary gate RTLIL::Wire *mk_ugate1(const RTLIL::IdString &red_typ, std::string &name, SigBit ip1, std::string &op_name) { From 986507f95fa69c7b35960750f583f49e672062d0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 19 Sep 2023 15:48:23 +0200 Subject: [PATCH 030/240] booth: Streamline the low-level circuit emission For the basic single-bit operations, opt for gate cells (`$_AND_` etc.) instead of the coarse cells (`$and` etc.). For the emission of cells move to the conventional module methods (`module->addAndGate`) away from the local helpers. While at it, touch on the surrounding code. --- passes/techmap/booth.cc | 151 +++++++++++++++------------------------- 1 file changed, 58 insertions(+), 93 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 2713d33956a..64a924e4ffb 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -108,98 +108,88 @@ struct BoothPassWorker { } // Booth unsigned decoder lsb - void BuildBur4d_lsb(std::string &name, SigBit lsb_i, SigBit one_i, SigBit s_i, SigBit &ppij_o, - std::string op_wire_name) + SigBit Bur4d_lsb(std::string name, SigBit lsb_i, SigBit one_i, SigBit s_i) { - std::string empty; - auto and_op = mk_ugate2(ID($and), name, lsb_i, one_i, empty); - ppij_o = mk_ugate2(ID($xor), name, and_op, s_i, op_wire_name); + SigBit and_op = module->AndGate(NEW_ID_SUFFIX(name), lsb_i, one_i); + return module->XorGate(NEW_ID_SUFFIX(name), and_op, s_i); } // Booth unsigned radix4 decoder - void BuildBur4d_n(std::string &name, SigBit yn_i, SigBit ynm1_i, SigBit one_i, SigBit two_i, SigBit s_i, - SigBit &ppij_o) + SigBit Bur4d_n(std::string name, SigBit yn_i, SigBit ynm1_i, SigBit one_i, SigBit two_i, SigBit s_i) { // ppij = ((yn & one) | (ynm1 & two)) ^ s; - std::string empty; - auto an1 = mk_ugate2(ID($and), name, yn_i, one_i, empty); - auto an2 = mk_ugate2(ID($and), name, ynm1_i, two_i, empty); - auto or1 = mk_ugate2(ID($or), name, an1, an2, empty); - ppij_o = mk_ugate2(ID($xor), name, s_i, or1, empty); + SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), yn_i, one_i); + SigBit an2 = module->AndGate(NEW_ID_SUFFIX(name), ynm1_i, two_i); + SigBit or1 = module->OrGate(NEW_ID_SUFFIX(name), an1, an2); + return module->XorGate(NEW_ID_SUFFIX(name), s_i, or1); } // Booth unsigned radix4 decoder - void BuildBur4d_msb(std::string &name, SigBit msb_i, SigBit two_i, SigBit s_i, SigBit &ppij_o) + SigBit Bur4d_msb(std::string name, SigBit msb_i, SigBit two_i, SigBit s_i) { // ppij = (msb & two) ^ s; - std::string empty; - auto an1 = mk_ugate2(ID($and), name, msb_i, two_i, empty); - ppij_o = mk_ugate2(ID($xor), name, s_i, an1, empty); + SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), msb_i, two_i); + return module->XorGate(NEW_ID_SUFFIX(name), s_i, an1); } // half adder, used in CPA - void BuildHa(std::string &name, SigBit a_i, SigBit b_i, SigBit &s_o, SigBit &c_o) + void BuildHa(std::string name, SigBit a_i, SigBit b_i, SigBit &s_o, SigBit &c_o) { - std::string empty; - s_o = mk_ugate2(ID($xor), name, a_i, b_i, empty); - c_o = mk_ugate2(ID($and), name, a_i, b_i, empty); + s_o = module->XorGate(NEW_ID_SUFFIX(name), a_i, b_i); + c_o = module->AndGate(NEW_ID_SUFFIX(name), a_i, b_i); } // Booth unsigned radix 4 encoder - void BuildBur4e(std::string &name, SigBit y0_i, SigBit y1_i, SigBit y2_i, + void BuildBur4e(std::string name, SigBit y0_i, SigBit y1_i, SigBit y2_i, SigBit &one_o, SigBit &two_o, SigBit &s_o, SigBit &sb_o) { - - std::string empty; - one_o = mk_ugate2(ID($xor), name, y0_i, y1_i, empty); + one_o = module->XorGate(NEW_ID_SUFFIX(name), y0_i, y1_i); s_o = y2_i; - sb_o = mk_ugate1(ID($not), name, y2_i, empty); - auto inv_y1_xor_y2 = mk_ugate1(ID($not), name, mk_ugate2(ID($xor), name, y1_i, y2_i, empty), empty); - two_o = mk_ugate1(ID($not), name, mk_ugate2(ID($or), name, inv_y1_xor_y2, one_o, empty), empty); + sb_o = module->NotGate(NEW_ID_SUFFIX(name), y2_i); + SigBit y1_xnor_y2 = module->XnorGate(NEW_ID_SUFFIX(name), y1_i, y2_i); + two_o = module->NorGate(NEW_ID_SUFFIX(name), y1_xnor_y2, one_o); } - void BuildBr4e(std::string &name, SigBit y2_m1_i, + void BuildBr4e(std::string name, SigBit y2_m1_i, SigBit y2_i, // y2i SigBit y2_p1_i, SigBit &negi_o, SigBit &twoi_n_o, SigBit &onei_n_o, SigBit &cori_o) { + auto y2_p1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_p1_i); + auto y2_n = module->NotGate(NEW_ID_SUFFIX(name), y2_i); + auto y2_m1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_m1_i); - std::string empty; - auto y2_p1_n = mk_ugate1(ID($not), name, y2_p1_i, empty); - auto y2_n = mk_ugate1(ID($not), name, y2_i, empty); - auto y2_m1_n = mk_ugate1(ID($not), name, y2_m1_i, empty); + negi_o = y2_p1_i; - // negi_o = y2_p1_i - negi_o = mk_ugate1(ID($pos), name, y2_p1_i, empty); // twoi_n = ~( // (y2_p1_n & y2_i & y2_m1_i) | // (y2_p1 & y2_n & y2_m1_n) // ) - auto and3_1 = mk_ugate2(ID($and), name, y2_p1_n, mk_ugate2(ID($and), name, y2_i, y2_m1_i, empty), empty); - auto and3_2 = mk_ugate2(ID($and), name, y2_p1_i, mk_ugate2(ID($and), name, y2_n, y2_m1_n, empty), empty); + twoi_n_o = module->NorGate(NEW_ID_SUFFIX(name), + module->AndGate(NEW_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEW_ID_SUFFIX(name), y2_i, y2_m1_i)), + module->AndGate(NEW_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEW_ID_SUFFIX(name), y2_n, y2_m1_n)) + ); - twoi_n_o = mk_ugate1(ID($not), name, mk_ugate2(ID($or), name, and3_1, and3_2, empty), empty); // onei_n = ~(y2_m1_i ^ y2_i); - onei_n_o = mk_ugate1(ID($not), name, mk_ugate2(ID($xor), name, y2_m1_i, y2_i, empty), empty); + onei_n_o = module->XnorGate(NEW_ID_SUFFIX(name), y2_m1_i, y2_i); // cori = (y2_m1_n | y2_n) & y2_p1_i; - cori_o = mk_ugate2(ID($and), name, y2_p1_i, mk_ugate2(ID($or), name, y2_m1_n, y2_n, empty), empty); + cori_o = module->AndGate(NEW_ID_SUFFIX(name), module->OrGate(NEW_ID_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i); } // // signed booth radix 4 decoder // - void BuildBr4d(std::string &name, SigBit nxj_m1_i, SigBit twoi_n_i, SigBit xj_i, SigBit negi_i, SigBit onei_n_i, + void BuildBr4d(std::string name, SigBit nxj_m1_i, SigBit twoi_n_i, SigBit xj_i, SigBit negi_i, SigBit onei_n_i, SigBit &ppij_o, SigBit &nxj_o) { - - std::string empty; // nxj_in = xnor(xj,negi) // nxj_o = xnj_in, // ppij = ~( (nxj_m1_i | twoi_n_i) & (nxj_int | onei_n_i)); - nxj_o = mk_ugate2(ID($xnor), name, xj_i, negi_i, empty); - SigBit or1 = mk_ugate2(ID($or), name, nxj_m1_i, twoi_n_i, empty); - SigBit or2 = mk_ugate2(ID($or), name, nxj_o, onei_n_i, empty); - ppij_o = mk_ugate1(ID($not), name, mk_ugate2(ID($and), name, or1, or2, empty), empty); + nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), xj_i, negi_i); + ppij_o = module->NandGate(NEW_ID_SUFFIX(name), + module->OrGate(NEW_ID_SUFFIX(name), nxj_m1_i, twoi_n_i), + module->OrGate(NEW_ID_SUFFIX(name), nxj_o, onei_n_i) + ); } /* @@ -207,7 +197,7 @@ struct BoothPassWorker { using non-booth encoded logic. We can save a booth encoder for the first couple of bits. */ - void BuildBoothQ1(std::string &name, SigBit negi_i, SigBit cori_i, SigBit x0_i, SigBit x1_i, SigBit y0_i, + void BuildBoothQ1(std::string name, SigBit negi_i, SigBit cori_i, SigBit x0_i, SigBit x1_i, SigBit y0_i, SigBit y1_i, SigBit &nxj_o, SigBit &cor_o, SigBit &pp0_o, SigBit &pp1_o) { @@ -222,15 +212,14 @@ struct BoothPassWorker { //correction propagation assign CORO = (~PP1 & ~PP0)? CORI : 1'b0; */ - std::string empty; - nxj_o = mk_ugate2(ID($xnor), name, x1_i, negi_i, empty); - pp0_o = mk_ugate2(ID($and), name, x0_i, y0_i, empty); - SigBit pp1_1_int = mk_ugate2(ID($and), name, x1_i, y0_i, empty); - SigBit pp1_2_int = mk_ugate2(ID($and), name, x0_i, y1_i, empty); - pp1_o = mk_ugate2(ID($xor), name, pp1_1_int, pp1_2_int, empty); - - SigBit pp1_nor_pp0 = mk_ugate1(ID($not), name, mk_ugate2(ID($or), name, pp1_o, pp0_o, empty), empty); - cor_o = mk_ugate2(ID($and), name, pp1_nor_pp0, cori_i, empty); + nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), x1_i, negi_i); + pp0_o = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y0_i); + SigBit pp1_1_int = module->AndGate(NEW_ID_SUFFIX(name), x1_i, y0_i); + SigBit pp1_2_int = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y1_i); + pp1_o = module->XorGate(NEW_ID_SUFFIX(name), pp1_1_int, pp1_2_int); + + SigBit pp1_nor_pp0 = module->NorGate(NEW_ID_SUFFIX(name), pp1_o, pp0_o); + cor_o = module->AndGate(NEW_ID_SUFFIX(name), pp1_nor_pp0, cori_i); } void run() @@ -454,28 +443,18 @@ struct BoothPassWorker { { (void)module; int x_sz = GetSize(X); + SigBit ppij; // lsb - std::string dec_name = "row0_lsb_dec"; - - SigBit ppij; - std::string ppij_name = "ppij_0_0"; - BuildBur4d_lsb(dec_name, X[0], one_int[0], s_int[0], ppij, ppij_name); - ppij_vec.append(ppij); + ppij_vec.append(Bur4d_lsb("row0_lsb_dec", X[0], one_int[0], s_int[0])); // 1..xsize -1 - for (int i = 1; i < x_sz; i++) { - dec_name = "row0_dec_" + std::to_string(i); - SigBit ppij; - BuildBur4d_n(dec_name, X[i], X[i - 1], one_int[0], two_int[0], - s_int[0], ppij); - ppij_vec.append(ppij); - } + for (int i = 1; i < x_sz; i++) + ppij_vec.append(Bur4d_n(stringf("row0_dec_%d", i), X[i], X[i - 1], + one_int[0], two_int[0], s_int[0])); // The redundant bit. Duplicate decoding of last bit. - dec_name = "row0_dec_msb"; - BuildBur4d_msb(dec_name, X[x_sz - 1], two_int[0], s_int[0], ppij); - ppij_vec.append(ppij); + ppij_vec.append(Bur4d_msb("row0_dec_msb", X[x_sz - 1], two_int[0], s_int[0])); // append the sign bits ppij_vec.append(s_int[0]); @@ -494,37 +473,23 @@ struct BoothPassWorker { int x_sz = GetSize(X); // lsb - std::string ppij_name = "ppij_" + std::to_string(row_ix) + "_0"; - SigBit ppij; - std::string empty; - std::string dec_name = "row" + std::to_string(row_ix) + "_lsb_dec"; - BuildBur4d_lsb(dec_name, X[0], one_int, s_int, ppij, empty); - - ppij_vec.append(ppij); + ppij_vec.append(Bur4d_lsb(stringf("row_%d_lsb_dec", row_ix), X[0], one_int, s_int)); // core bits - for (int i = 1; i < x_sz; i++) { - - dec_name = "row_" + std::to_string(row_ix) + "_dec_" + std::to_string(i); - BuildBur4d_n(dec_name, X[i], X[i - 1], - one_int, two_int, s_int, ppij); - ppij_vec.append(ppij); - } + for (int i = 1; i < x_sz; i++) + ppij_vec.append(Bur4d_n(stringf("row_%d_dec_%d", row_ix, i), X[i], X[i - 1], + one_int, two_int, s_int)); // redundant bit - - dec_name = "row_dec_red"; - BuildBur4d_msb(dec_name, X[x_sz - 1], two_int, s_int, ppij); - ppij_vec.append(ppij); + ppij_vec.append(Bur4d_msb("row_dec_red", X[x_sz - 1], two_int, s_int)); // sign bit - if (no_sign == false) // if no sign is false then make a sign bit + if (!no_sign) // if no sign is false then make a sign bit ppij_vec.append(sb_int); // constant bit - if (no_constant == false) { // if non constant is false make a constant bit + if (!no_constant) // if non constant is false make a constant bit ppij_vec.append(State::S1); - } } void DebugDumpAlignPP(std::vector> &aligned_pp) From 30f8387b75f205ff360292bcd2459191daed9a66 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 19 Sep 2023 16:25:10 +0200 Subject: [PATCH 031/240] booth: Rewrite the main cell selection loop --- passes/techmap/booth.cc | 180 ++++++++++++++++++---------------------- 1 file changed, 82 insertions(+), 98 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 64a924e4ffb..df0f82ec289 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -225,108 +225,92 @@ struct BoothPassWorker { void run() { for (auto cell : module->selected_cells()) { - if (cell->type.in(ID($mul))) { - RTLIL::SigSpec A = sigmap(cell->getPort(ID::A)); - RTLIL::SigSpec B = sigmap(cell->getPort(ID::B)); - RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y)); - if (GetSize(A) >= 4 && GetSize(B) >= 4 && GetSize(Y) >= 8 && - ((cell->getParam(ID::A_SIGNED).as_bool() && cell->getParam(ID::B_SIGNED).as_bool()) || - (!cell->getParam(ID::A_SIGNED).as_bool() && !cell->getParam(ID::B_SIGNED).as_bool()))) { - bool is_signed = false; - if (cell->getParam(ID::A_SIGNED).as_bool()) { - log(" By passing macc inferencing for signed multiplier -- generating booth\n"); - is_signed = true; - } else - log(" By passing macc inferencing for unsigned multiplier -- generating booth\n"); - - int x_sz = GetSize(A); - int y_sz = GetSize(B); - int z_sz = GetSize(Y); - - // To simplify the generator size the arguments - // to be the same. Then allow logic synthesis to - // clean things up. Size to biggest - - int x_sz_revised = x_sz; - int y_sz_revised = y_sz; - - if (x_sz != y_sz) { - if (x_sz < y_sz) { - if (y_sz % 2 != 0) { - x_sz_revised = y_sz + 1; - y_sz_revised = y_sz + 1; - } else - x_sz_revised = y_sz; - - } else { - if (x_sz % 2 != 0) { - y_sz_revised = x_sz + 1; - x_sz_revised = x_sz + 1; - } else - y_sz_revised = x_sz; - } + if (cell->type != ID($mul)) + continue; + + SigSpec A = cell->getPort(ID::A); + SigSpec B = cell->getPort(ID::B); + SigSpec Y = cell->getPort(ID::Y); + int x_sz = GetSize(A), y_sz = GetSize(B), z_sz = GetSize(Y); + + if (x_sz < 4 || y_sz < 4 || z_sz < 8) { + log_debug("Not mapping cell %s sized at %dx%x, %x: size below threshold\n", + log_id(cell), x_sz, y_sz, z_sz); + continue; + } + + log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool()); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + + log("Mapping cell %s to %s Booth multiplier\n", log_id(cell), is_signed ? "signed" : "unsigned"); + + // To simplify the generator size the arguments + // to be the same. Then allow logic synthesis to + // clean things up. Size to biggest + + int x_sz_revised = x_sz; + int y_sz_revised = y_sz; + + if (x_sz != y_sz) { + if (x_sz < y_sz) { + if (y_sz % 2 != 0) { + x_sz_revised = y_sz + 1; + y_sz_revised = y_sz + 1; + } else { + x_sz_revised = y_sz; + } + } else { + if (x_sz % 2 != 0) { + y_sz_revised = x_sz + 1; + x_sz_revised = x_sz + 1; } else { - if (x_sz % 2 != 0) { - y_sz_revised = y_sz + 1; - x_sz_revised = x_sz + 1; - } + y_sz_revised = x_sz; } - - log_assert((x_sz_revised == y_sz_revised) && (x_sz_revised % 2 == 0) && (y_sz_revised % 2 == 0)); - - Wire *expanded_A = module->addWire(NEW_ID, x_sz_revised); - Wire *expanded_B = module->addWire(NEW_ID, y_sz_revised); - - std::string buf_name = "expand_a_buf_"; - auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setParam(ID::A_WIDTH, x_sz); - buf->setParam(ID::Y_WIDTH, x_sz_revised); - buf->setPort(ID::A, SigSpec(A)); - buf->setParam(ID::A_SIGNED, is_signed ? true : false); - buf->setPort(ID::Y, SigSpec(expanded_A)); - - buf_name = "expand_b_buf_"; - buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setPort(ID::A, SigSpec(B)); - buf->setParam(ID::A_WIDTH, y_sz); - buf->setParam(ID::Y_WIDTH, y_sz_revised); - buf->setParam(ID::A_SIGNED, is_signed ? true : false); - buf->setPort(ID::Y, SigSpec(expanded_B)); - - // Make sure output domain is big enough to take - // all combinations. - // Later logic synthesis will kill unused - // portions of the output domain. - - unsigned required_op_size = x_sz_revised + y_sz_revised; - Wire *expanded_Y = module->addWire(NEW_ID, required_op_size); - // now connect the expanded_Y with a tap to fill out sig Spec Y - buf_name = "reducer_buf_"; - buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setPort(ID::A, expanded_Y); - buf->setParam(ID::A_WIDTH, required_op_size); - buf->setParam(ID::Y_WIDTH, z_sz); // The real user width - buf->setParam(ID::A_SIGNED, is_signed ? true : false); - // wire in output Y - buf->setPort(ID::Y, SigSpec(Y)); - - if (is_signed == false) /* unsigned multiplier */ - CreateBoothUMult(module, - expanded_A, // multiplicand - expanded_B, // multiplier(scanned) - expanded_Y // result - ); - else /*signed multiplier */ - CreateBoothSMult(module, - expanded_A, // multiplicand - expanded_B, // multiplier(scanned) - expanded_Y // result (sized) - ); - module->remove(cell); - booth_counter++; - continue; } + } else { + if (x_sz % 2 != 0) { + y_sz_revised = y_sz + 1; + x_sz_revised = x_sz + 1; + } + } + + log_assert((x_sz_revised == y_sz_revised) && (x_sz_revised % 2 == 0) && (y_sz_revised % 2 == 0)); + + + A.extend_u0(x_sz_revised, is_signed); + B.extend_u0(y_sz_revised, is_signed); + + // Make sure output domain is big enough to take + // all combinations. + // Later logic synthesis will kill unused + // portions of the output domain. + + int required_op_size = x_sz_revised + y_sz_revised; + + if (required_op_size != z_sz) { + SigSpec expanded_Y = module->addWire(NEW_ID, required_op_size); + SigSpec Y_driver = expanded_Y; + Y_driver.extend_u0(Y.size(), is_signed); + module->connect(Y, Y_driver); + Y = expanded_Y; } + log_assert(GetSize(Y) == required_op_size); + + if (!is_signed) /* unsigned multiplier */ + CreateBoothUMult(module, + A, // multiplicand + B, // multiplier(scanned) + Y // result + ); + else /* signed multiplier */ + CreateBoothSMult(module, + A, // multiplicand + B, // multiplier(scanned) + Y // result (sized) + ); + + module->remove(cell); + booth_counter++; } } From 62302f601ddc9810b5b780748b97c84d875dfa10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 19 Sep 2023 16:25:40 +0200 Subject: [PATCH 032/240] booth: Remove more of unused helpers --- passes/techmap/booth.cc | 41 ----------------------------------------- 1 file changed, 41 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index df0f82ec289..086b2e85b8e 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -66,47 +66,6 @@ struct BoothPassWorker { BoothPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; } - // Unary gate - RTLIL::Wire *mk_ugate1(const RTLIL::IdString &red_typ, std::string &name, SigBit ip1, std::string &op_name) - { - std::string op_wire_name; - if (op_name.empty()) - op_wire_name = name + "_o"; - else - op_wire_name = op_name; - RTLIL::Wire *ret = module->addWire(new_id(op_wire_name, __LINE__, ""), 1); - auto g = module->addCell(new_id(name, __LINE__, ""), red_typ); - g->setPort(ID::A, ip1); - g->setPort(ID::Y, ret); - g->setParam(ID::A_SIGNED, false); - g->setParam(ID::A_WIDTH, 1); - g->setParam(ID::Y_WIDTH, 1); - return ret; - } - - // Binary gate - RTLIL::Wire *mk_ugate2(const RTLIL::IdString &red_typ, std::string &name, SigBit ip1, SigBit ip2, std::string &op_name) - { - auto g = module->addCell(new_id(name, __LINE__, ""), red_typ); - std::string op_wire_name; - if (op_name.empty()) - op_wire_name = name + "_o"; - else - op_wire_name = op_name; - - auto ret = module->addWire(new_id(op_wire_name, __LINE__, ""), 1); - - g->setPort(ID::A, ip1); - g->setPort(ID::B, ip2); - g->setPort(ID::Y, ret); - g->setParam(ID::A_SIGNED, false); - g->setParam(ID::B_SIGNED, false); - g->setParam(ID::A_WIDTH, 1); - g->setParam(ID::B_WIDTH, 1); - g->setParam(ID::Y_WIDTH, 1); - return ret; - } - // Booth unsigned decoder lsb SigBit Bur4d_lsb(std::string name, SigBit lsb_i, SigBit one_i, SigBit s_i) { From d641dfaec2a67a25afb4a82469af3b0627e9b334 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 19 Sep 2023 16:33:22 +0200 Subject: [PATCH 033/240] rtlil: Add helper to emit full-adder cells --- kernel/rtlil.cc | 13 +++++++++++++ kernel/rtlil.h | 2 ++ 2 files changed, 15 insertions(+) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1b57af60acb..efd76e9cd25 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2677,6 +2677,19 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &s return cell; } +RTLIL::Cell* RTLIL::Module::addFa(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src) +{ + RTLIL::Cell *cell = addCell(name, ID($fa)); + cell->parameters[ID::WIDTH] = sig_a.size(); + cell->setPort(ID::A, sig_a); + cell->setPort(ID::B, sig_b); + cell->setPort(ID::C, sig_c); + cell->setPort(ID::X, sig_x); + cell->setPort(ID::Y, sig_y); + cell->set_src_attribute(src); + return cell; +} + RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($slice)); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index c50d75e9087..3dff48b4f79 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1298,6 +1298,8 @@ struct RTLIL::Module : public RTLIL::AttrObject RTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); RTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); + RTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = ""); + RTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); RTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); RTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); From cde2a0b926c1edd24936748e878eee40a3389f26 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 25 Sep 2023 13:54:24 +0200 Subject: [PATCH 034/240] booth: Make more use of appropriate helpers Use the `addFa` helper, do not misuse `new_id` and make other changes to the transformation code. --- passes/techmap/booth.cc | 412 +++++++++++++++------------------------- 1 file changed, 152 insertions(+), 260 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 086b2e85b8e..aa5684b7427 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -687,20 +687,15 @@ struct BoothPassWorker { // End Case else if (n == s_vec.size() - 1) { // Make the carry results.. Two extra bits after fa. - std::string fa_name = "cpa_" + std::to_string(cpa_id) + "_fa_" + std::to_string(n); - - auto fa_cell = module->addCell(new_id(fa_name, __LINE__, ""), ID($fa)); - fa_cell->setParam(ID::WIDTH, 1); - carry_name = "cpa_" + std::to_string(cpa_id) + "carry_" + std::to_string(n); - fa_cell->setPort(ID::A, s_vec[n]); - fa_cell->setPort(ID::B, c_vec[n - 1]); - fa_cell->setPort(ID::C, carry); - // wire in result and carry out - fa_cell->setPort(ID::Y, result[n]); - - // make a new carry bit for carry out... - carry = module->addWire(new_id(carry_name, __LINE__, ""), 1); - fa_cell->setPort(ID::X, carry); + SigBit carry_out = module->addWire(NEW_ID, 1); + module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), + /* A */ s_vec[n], + /* B */ c_vec[n - 1], + /* C */ carry, + /* X */ carry_out, + /* Y */ result[n] + ); + carry = carry_out; #ifdef DEBUG_CPA printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.c_str(), s_vec[n]->name.c_str(), @@ -720,20 +715,15 @@ struct BoothPassWorker { } // Step case else { - std::string fa_name = "cpa_" + std::to_string(cpa_id) + "_fa_" + std::to_string(n); - auto fa_cell = module->addCell(new_id(fa_name, __LINE__, ""), ID($fa)); - fa_cell->setParam(ID::WIDTH, 1); - - carry_name = "cpa_" + std::to_string(cpa_id) + "carry_" + std::to_string(n); - fa_cell->setPort(ID::A, s_vec[n]); - fa_cell->setPort(ID::B, c_vec[n - 1]); - fa_cell->setPort(ID::C, carry); - // wire in result and carry out - fa_cell->setPort(ID::Y, result[n]); - // make a new carry bit for carry out... - carry = module->addWire(new_id(carry_name, __LINE__, ""), 1); - fa_cell->setPort(ID::X, carry); - + SigBit carry_out = module->addWire(NEW_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1); + module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), + /* A */ s_vec[n], + /* B */ c_vec[n - 1], + /* C */ carry, + /* X */ carry_out, + /* Y */ result[n] + ); + carry = carry_out; #ifdef DEBUG_CPA printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.c_str(), s_vec[n]->name.c_str(), c_vec[n - 1]->name.c_str(), carry->name.c_str()); @@ -752,9 +742,6 @@ struct BoothPassWorker { int csa_ix = 0; int column_size = column_bits.size(); - static int unique_id = 0; - - unique_id++; if (column_size > 0) { int var_ix = 0; @@ -767,38 +754,23 @@ struct BoothPassWorker { if (first_csa_ips.size() > 0) { // build the first csa - std::string csa_name = - "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix) + "_" + std::to_string(unique_id) + "_"; - auto csa = module->addCell(NEW_ID, - // new_id(csa_name, - // __LINE__, - // ""), - ID($fa)); - csa->setParam(ID::WIDTH, 1); - debug_csa_trees[column_ix].push_back(csa); - csa_ix++; - - csa->setPort(ID::A, first_csa_ips[0]); - - if (first_csa_ips.size() > 1) - csa->setPort(ID::B, first_csa_ips[1]); - else - csa->setPort(ID::B, State::S0); - - if (first_csa_ips.size() > 2) - csa->setPort(ID::C, first_csa_ips[2]); - else - csa->setPort(ID::C, State::S0); + auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); + auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); + + auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), + /* A */ first_csa_ips[0], + /* B */ first_csa_ips.size() > 1 ? first_csa_ips[1] : State::S0, + /* C */ first_csa_ips.size() > 2 ? first_csa_ips[2] : State::S0, + /* X */ c_wire, + /* Y */ s_wire + ); - std::string sum_wire_name = "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix) + "_s"; - auto s_wire = module->addWire(new_id(sum_wire_name, __LINE__, ""), 1); - csa->setPort(ID::Y, s_wire); s_result = s_wire; - std::string carry_wire_name = "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix) + "_c"; - auto c_wire = module->addWire(new_id(carry_wire_name, __LINE__, ""), 1); - csa->setPort(ID::X, c_wire); c_result = c_wire; + debug_csa_trees[column_ix].push_back(csa); + csa_ix++; + if (var_ix <= column_bits.size() - 1) carry_bits_to_sum.append(c_wire); @@ -814,32 +786,23 @@ struct BoothPassWorker { } if (csa_ips.size() > 0) { - csa_name = "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix); - auto csa = module->addCell(new_id(csa_name, __LINE__, ""), ID($fa)); - csa->setParam(ID::WIDTH, 1); - debug_csa_trees[column_ix].push_back(csa); + auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); + auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); - csa_ix++; - // prior level - csa->setPort(ID::A, s_wire); - csa->setPort(ID::B, csa_ips[0]); - if (csa_ips.size() > 1) - csa->setPort(ID::C, csa_ips[1]); - else - csa->setPort(ID::C, State::S0); + auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), + /* A */ s_result, + /* B */ csa_ips[0], + /* C */ csa_ips.size() > 1 ? csa_ips[1] : State::S0, + /* X */ c_wire, + /* Y */ s_wire + ); - carry_wire_name = "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix) + "_c"; - c_wire = module->addWire(new_id(carry_wire_name, __LINE__, ""), 1); + debug_csa_trees[column_ix].push_back(csa); + csa_ix++; if (var_ix <= column_bits.size() - 1) carry_bits_to_sum.append(c_wire); - sum_wire_name = "csa_" + std::to_string(column_ix) + "_" + std::to_string(csa_ix) + "_s"; - s_wire = module->addWire(new_id(sum_wire_name, __LINE__, ""), 1); - - csa->setPort(ID::X, c_wire); - csa->setPort(ID::Y, s_wire); - s_result = s_wire; c_result = c_wire; } @@ -854,22 +817,14 @@ struct BoothPassWorker { int y_sz = GetSize(Y); for (int y_ix = 0; y_ix < y_sz;) { - std::string enc_name = "bur_enc_" + std::to_string(encoder_ix) + "_"; - - std::string two_name = "two_int" + std::to_string(encoder_ix); - two_int.append(module->addWire(new_id(two_name, __LINE__, ""), 1)); + std::string enc_name = stringf("bur_enc_%d", encoder_ix); - std::string one_name = "one_int" + std::to_string(encoder_ix); - one_int.append(module->addWire(new_id(one_name, __LINE__, ""), 1)); - - std::string s_name = "s_int" + std::to_string(encoder_ix); - s_int.append(module->addWire(new_id(s_name, __LINE__, ""), 1)); - - std::string sb_name = "sb_int" + std::to_string(encoder_ix); - sb_int.append(module->addWire(new_id(sb_name, __LINE__, ""), 1)); + two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); + one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1)); + s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1)); + sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1)); if (y_ix == 0) { - BuildBur4e(enc_name, State::S0, Y[y_ix], Y[y_ix + 1], one_int[encoder_ix], two_int[encoder_ix], s_int[encoder_ix], sb_int[encoder_ix]); @@ -919,23 +874,15 @@ struct BoothPassWorker { encoder_ix++; if (need_padded_cell == true) { - // make extra encoder cell // y_ix at y0, rest 0 - std::string enc_name = "br_enc_pad" + std::to_string(encoder_ix) + "_"; - - std::string two_name = "two_int" + std::to_string(encoder_ix); - two_int.append(module->addWire(new_id(two_name, __LINE__, ""), 1)); - - std::string one_name = "one_int" + std::to_string(encoder_ix); - one_int.append(module->addWire(new_id(two_name, __LINE__, ""), 1)); + std::string enc_name = stringf("br_enc_pad_%d", encoder_ix); - std::string s_name = "s_int" + std::to_string(encoder_ix); - s_int.append(module->addWire(new_id(s_name, __LINE__, ""), 1)); - - std::string sb_name = "sb_int" + std::to_string(encoder_ix); - sb_int.append(module->addWire(new_id(sb_name, __LINE__, ""), 1)); + two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); + one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1)); + s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1)); + sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1)); SigBit one_o_int, two_o_int, s_o_int, sb_o_int; BuildBur4e(enc_name, Y[y_ix], State::S0, @@ -977,18 +924,13 @@ struct BoothPassWorker { cori_n_int.extend_u0(enc_count); for (unsigned encoder_ix = 1; encoder_ix <= enc_count; encoder_ix++) { - std::string enc_name = "enc_" + std::to_string(encoder_ix) + "_"; - std::string negi_name = "negi_n_int" + std::to_string(encoder_ix) + "_"; - negi_n_int[encoder_ix - 1] = module->addWire(new_id(negi_name, __LINE__, ""), 1); - std::string twoi_name = "twoi_n_int_" + std::to_string(encoder_ix) + "_"; - twoi_n_int[encoder_ix - 1] = module->addWire(new_id(twoi_name, __LINE__, ""), 1); - std::string onei_name = "onei_n_int_" + std::to_string(encoder_ix) + "_"; - onei_n_int[encoder_ix - 1] = module->addWire(new_id(onei_name, __LINE__, ""), 1); - std::string cori_name = "cori_n_int_" + std::to_string(encoder_ix) + "_"; - cori_n_int[encoder_ix - 1] = module->addWire(new_id(cori_name, __LINE__, ""), 1); + std::string enc_name = stringf("enc_%d", encoder_ix); + negi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1); + twoi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1); + onei_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1); + cori_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1); if (encoder_ix == 1) { - BuildBr4e(enc_name, State::S0, Y[0], Y[1], negi_n_int[encoder_ix - 1], twoi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], cori_n_int[encoder_ix - 1]); @@ -1020,22 +962,18 @@ struct BoothPassWorker { for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) { for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) { - std::string ppij_name = "ppij_" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; - PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1] = module->addWire(new_id(ppij_name, __LINE__, ""), 1); - std::string nxj_name; - if (decoder_ix == 1) - nxj_name = "nxj_pre_dec" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; - else - nxj_name = "nxj_" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; + PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1] = + module->addWire(NEW_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1); - nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1] = module->addWire(new_id(nxj_name, __LINE__, ""), 1); + nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1] = + module->addWire(NEW_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "", + encoder_ix, decoder_ix)), 1); } } // // build decoder array // - for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) { // pre-decoder std::string pre_dec_name = "pre_dec_" + std::to_string(encoder_ix) + "_"; @@ -1043,10 +981,10 @@ struct BoothPassWorker { if (encoder_ix == 1) { // quadrant 1 optimization } else { - auto cell = module->addCell(new_id(pre_dec_name, __LINE__, ""), ID($_NOT_)); - cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); - cell->setPort(ID::A, negi_n_int[encoder_ix - 1]); - cell->setPort(ID::Y, nxj[(encoder_ix - 1) * dec_count]); + module->addNotGate(NEW_ID_SUFFIX(stringf("pre_dec_%d", encoder_ix)), + negi_n_int[encoder_ix - 1], + nxj[(encoder_ix - 1) * dec_count] + ); } for (int decoder_ix = 1; decoder_ix < dec_count; decoder_ix++) { @@ -1056,8 +994,7 @@ struct BoothPassWorker { if ((decoder_ix == 1 || decoder_ix == 2) && encoder_ix == 1) continue; - std::string dec_name = "dec_" + std::to_string(encoder_ix) + "_" + std::to_string(decoder_ix) + "_"; - + std::string dec_name = stringf("dec_%d_%d", encoder_ix, decoder_ix); BuildBr4d(dec_name, nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1], twoi_n_int[encoder_ix - 1], X[decoder_ix - 1], negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1], nxj[((encoder_ix - 1) * dec_count) + decoder_ix]); @@ -1065,7 +1002,7 @@ struct BoothPassWorker { // duplicate end for sign fix // applies to 9th decoder (xsz+1 decoder). - std::string dec_name = "dec_" + std::to_string(encoder_ix) + "_" + std::to_string(x_sz + 1) + "_"; + std::string dec_name = stringf("dec_%d_%d", encoder_ix, x_sz + 1); SigBit unused_op; BuildBr4d(dec_name, nxj[((encoder_ix - 1) * dec_count) + dec_count - 1], twoi_n_int[encoder_ix - 1], X[dec_count - 2], negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], @@ -1083,11 +1020,10 @@ struct BoothPassWorker { for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) { for (fa_el_ix = 0; fa_el_ix < fa_count; fa_el_ix++) { - - std::string fa_sum_name = "fa_sum_n_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_"; - fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] = module->addWire(new_id(fa_sum_name, __LINE__, ""), 1); - std::string fa_carry_name = "fa_carry_n" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_"; - fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix] = module->addWire(new_id(fa_carry_name, __LINE__, ""), 1); + fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] = + module->addWire(NEW_ID_SUFFIX(stringf("fa_sum_n_%d_%d", fa_row_ix, fa_el_ix)), 1); + fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix] = + module->addWire(NEW_ID_SUFFIX(stringf("fa_carry_n_%d_%d", fa_row_ix, fa_el_ix)), 1); } } @@ -1110,67 +1046,52 @@ struct BoothPassWorker { // step case else if (fa_el_ix >= 2 && fa_el_ix <= x_sz) { // middle (2...x_sz cells) - bfa_name = "bfa_0_step_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; - auto cell = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); - cell->setParam(ID::WIDTH, 1); - cell->setPort(ID::A, PPij[(0 * dec_count) + fa_el_ix]); - cell->setPort(ID::B, PPij[(1 * dec_count) + fa_el_ix - 2]); - cell->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); - cell->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); - cell->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); + module->addFa(NEW_ID_SUFFIX(stringf("bfa_0_step_%d_%d_L", fa_row_ix, fa_el_ix)), + /* A */ PPij[(0 * dec_count) + fa_el_ix], + /* B */ PPij[(1 * dec_count) + fa_el_ix - 2], + /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], + /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], + /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] + ); } // end 3 cells: x_sz+1.2.3 // else { // fa_el_ix = x_sz+1 - bfa_name = "bfa_0_se_0" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; - auto cell1 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); - cell1->setParam(ID::WIDTH, 1); - cell1->setPort(ID::A, PPij[(0 * dec_count) + x_sz]); - cell1->setPort(ID::B, PPij[(1 * dec_count) + fa_el_ix - 2]); - cell1->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); - cell1->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); - cell1->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); + module->addFa(NEW_ID_SUFFIX(stringf("bfa_0_se_0_%d_%d_L", fa_row_ix, fa_el_ix)), + /* A */ PPij[(0 * dec_count) + x_sz], + /* B */ PPij[(1 * dec_count) + fa_el_ix - 2], + /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], + /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], + /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] + ); // exception:invert ppi fa_el_ix++; - exc_inv_name = "bfa_0_exc_inv1_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; - auto cellinv1 = module->addCell(new_id(exc_inv_name, __LINE__, ""), ID($_NOT_)); - cellinv1->add_strpool_attribute(ID::src, cellinv1->get_strpool_attribute(ID::src)); - - RTLIL::Wire *d08_inv = module->addWire(NEW_ID, 1); - - cellinv1->setPort(ID::A, PPij[(0 * dec_count) + dec_count - 1]); - cellinv1->setPort(ID::Y, d08_inv); - - exc_inv_name = "bfa_0_exc_inv2_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; - - auto cellinv2 = module->addCell(new_id(exc_inv_name, __LINE__, ""), ID($_NOT_)); - cellinv2->add_strpool_attribute(ID::src, cellinv2->get_strpool_attribute(ID::src)); - RTLIL::Wire *d18_inv = module->addWire(NEW_ID, 1); - cellinv2->setPort(ID::A, PPij[(1 * dec_count) + dec_count - 1]); - cellinv2->setPort(ID::Y, d18_inv); + SigBit d08_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_0_exc_inv1_%d_%d_L", fa_row_ix, fa_el_ix)), + PPij[(0 * dec_count) + dec_count - 1]); - bfa_name = "bfa_0_se_1_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; + SigBit d18_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_0_exc_inv2_%d_%d_L", fa_row_ix, fa_el_ix)), + PPij[(1 * dec_count) + dec_count - 1]); - auto cell2 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); - cell2->setParam(ID::WIDTH, 1); - cell2->setPort(ID::A, d08_inv); - cell2->setPort(ID::B, d18_inv); - cell2->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); - cell2->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); - cell2->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); + module->addFa(NEW_ID_SUFFIX(stringf("bfa_0_se_1_%d_%d_L", fa_row_ix, fa_el_ix)), + /* A */ d08_inv, + /* B */ d18_inv, + /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], + /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], + /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] + ); // sign extension fa_el_ix++; - bfa_name = "bfa_0_se_2_" + std::to_string(fa_row_ix) + "_" + std::to_string(fa_el_ix) + "_L"; - auto cell3 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); - cell3->setParam(ID::WIDTH, 1); - cell3->setPort(ID::A, State::S0); - cell3->setPort(ID::B, State::S1); - cell3->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); - cell3->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); - cell3->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); + + module->addFa(NEW_ID_SUFFIX(stringf("bfa_0_se_2_%d_%d_L", fa_row_ix, fa_el_ix)), + /* A */ State::S0, + /* B */ State::S1, + /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], + /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], + /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] + ); } } @@ -1181,74 +1102,59 @@ struct BoothPassWorker { if (fa_el_ix == 0) { // first two cells: have B input hooked to 0. // column is offset by row_ix*2 - bfa_name = "bfa_" + std::to_string(fa_row_ix) + "_base_" + std::to_string(fa_row_ix) + "_" + - std::to_string(fa_el_ix) + "_L"; - auto cell1 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); - cell1->setParam(ID::WIDTH, 1); - cell1->setPort(ID::A, fa_sum_n[(fa_row_ix - 1) * fa_count + 2]); // from prior full adder row - cell1->setPort(ID::B, State::S0); - cell1->setPort(ID::C, cori_n_int[fa_row_ix]); - cell1->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); - cell1->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); + + module->addFa(NEW_ID_SUFFIX(stringf("bfa_base_%d_%d_L", fa_row_ix, fa_el_ix)), + /* A */ fa_sum_n[(fa_row_ix - 1) * fa_count + 2], + /* B */ State::S0, + /* C */ cori_n_int[fa_row_ix], + /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], + /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] + ); fa_el_ix++; - bfa_name = "bfa_" + std::to_string(fa_row_ix) + "_base_" + std::to_string(fa_row_ix) + "_" + - std::to_string(fa_el_ix) + "_L"; - auto cell2 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); - cell2->setParam(ID::WIDTH, 1); - cell2->setPort(ID::A, - fa_sum_n[(fa_row_ix - 1) * fa_count + 3]); // from prior full adder row - cell2->setPort(ID::B, State::S0); - cell2->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); - cell2->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); - cell2->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); + module->addFa(NEW_ID_SUFFIX(stringf("bfa_base_%d_%d_L", fa_row_ix, fa_el_ix)), + /* A */ fa_sum_n[(fa_row_ix - 1) * fa_count + 3], // from prior full adder row + /* B */ State::S0, + /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], + /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], + /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] + ); + } else if (fa_el_ix >= 2 && fa_el_ix <= x_sz + 1) { // middle (2...x_sz+1 cells) - bfa_name = "bfa_" + std::to_string(fa_row_ix) + "_step_" + std::to_string(fa_row_ix) + "_" + - std::to_string(fa_el_ix) + "_L"; - auto cell = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); - cell->setParam(ID::WIDTH, 1); - cell->setPort(ID::A, fa_sum_n[(fa_row_ix - 1) * fa_count + fa_el_ix + 2]); - cell->setPort(ID::B, PPij[(fa_row_ix + 1) * dec_count + fa_el_ix - 2]); - cell->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); - cell->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); - cell->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); + module->addFa(NEW_ID_SUFFIX(stringf("bfa_step_%d_%d_L", fa_row_ix, fa_el_ix)), + /* A */ fa_sum_n[(fa_row_ix - 1) * fa_count + fa_el_ix + 2], + /* B */ PPij[(fa_row_ix + 1) * dec_count + fa_el_ix - 2], + /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], + /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], + /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] + ); } else if (fa_el_ix > x_sz + 1) { // end two bits: sign extension - std::string se_inv_name; - se_inv_name = "bfa_" + std::to_string(fa_row_ix) + "_se_inv_" + std::to_string(fa_row_ix) + "_" + - std::to_string(fa_el_ix) + "_L"; - auto cellinv = module->addCell(new_id(se_inv_name, __LINE__, ""), ID($_NOT_)); - cellinv->add_strpool_attribute(ID::src, cellinv->get_strpool_attribute(ID::src)); - RTLIL::Wire *d_inv = module->addWire(NEW_ID, 1); - cellinv->setPort(ID::A, PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]); - cellinv->setPort(ID::Y, d_inv); - - bfa_name = "bfa_" + std::to_string(fa_row_ix) + "_se_" + std::to_string(fa_row_ix) + "_" + - std::to_string(fa_el_ix) + "_L"; - auto cell1 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); - cell1->setParam(ID::WIDTH, 1); - cell1->setPort(ID::A, fa_carry_n[((fa_row_ix - 1) * fa_count) + fa_count - 1]); - cell1->setPort(ID::B, d_inv); - cell1->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); - cell1->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); - cell1->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); + SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_%d_L", fa_row_ix, fa_el_ix)), + PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]); + + module->addFa(NEW_ID_SUFFIX(stringf("bfa_se_%d_%d_L", fa_row_ix, fa_el_ix)), + /* A */ fa_carry_n[((fa_row_ix - 1) * fa_count) + fa_count - 1], + /* B */ d_inv, + /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], + /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], + /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] + ); fa_el_ix++; // sign extension - bfa_name = "bfa_" + std::to_string(fa_row_ix) + "_se_" + std::to_string(fa_row_ix) + "_" + - std::to_string(fa_el_ix) + "_L"; - auto cell2 = module->addCell(new_id(bfa_name, __LINE__, ""), ID($fa)); - cell2->setParam(ID::WIDTH, 1); - cell2->setPort(ID::A, State::S0); - cell2->setPort(ID::B, State::S1); - cell2->setPort(ID::C, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1]); - cell2->setPort(ID::X, fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix]); - cell2->setPort(ID::Y, fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix]); + module->addFa(NEW_ID_SUFFIX(stringf("bfa_se_%d_%d_L", fa_row_ix, fa_el_ix)), + /* A */ State::S0, + /* B */ State::S1, + /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], + /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], + /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] + ); } } } @@ -1257,13 +1163,10 @@ struct BoothPassWorker { // instantiate the cpa SigSpec cpa_carry; - for (int cix = 0; cix < z_sz; cix++) { - std::string cpa_cix_name = "cpa_carry_" + std::to_string(cix) + "_"; - cpa_carry.append(module->addWire(new_id(cpa_cix_name, __LINE__, ""), 1)); - } + for (int cix = 0; cix < z_sz; cix++) + cpa_carry.append(module->addWire(NEW_ID_SUFFIX(stringf("cpa_carry_%d", cix)), 1)); for (int cpa_ix = 0; cpa_ix < z_sz; cpa_ix++) { - // The end case where we pass the last two summands // from prior row directly to product output // without using a cpa cell. This is always @@ -1271,27 +1174,16 @@ struct BoothPassWorker { if (cpa_ix <= fa_row_count * 2 - 1) { int fa_row_ix = cpa_ix / 2; - std::string buf_name = - "pp_buf_" + std::to_string(cpa_ix) + "_" + "driven_by_fa_row_" + std::to_string(fa_row_ix) + "_"; - auto buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setPort(ID::A, fa_sum_n[(fa_row_ix * fa_count) + 0]); - buf->setParam(ID::A_WIDTH, 1); - buf->setParam(ID::Y_WIDTH, 1); - buf->setParam(ID::A_SIGNED, true); - buf->setPort(ID::Y, Z[cpa_ix]); + module->addBufGate(NEW_ID_SUFFIX(stringf("pp_buf_%d_driven_by_fa_row_%d", cpa_ix, fa_row_ix)), + fa_sum_n[(fa_row_ix * fa_count) + 0], Z[cpa_ix]); cpa_ix++; - buf_name = "pp_buf_" + std::to_string(cpa_ix) + "_" + "driven_by_fa_row_" + std::to_string(fa_row_ix) + "_"; - buf = module->addCell(new_id(buf_name, __LINE__, ""), ID($pos)); - buf->setPort(ID::A, fa_sum_n[(fa_row_ix * fa_count) + 1]); - buf->setParam(ID::A_WIDTH, 1); - buf->setParam(ID::Y_WIDTH, 1); - buf->setParam(ID::A_SIGNED, true); - buf->setPort(ID::Y, Z[cpa_ix]); + module->addBufGate(NEW_ID_SUFFIX(stringf("pp_buf_%d_driven_by_fa_row_%d", cpa_ix, fa_row_ix)), + fa_sum_n[(fa_row_ix * fa_count) + 1], Z[cpa_ix]); } else { int offset = fa_row_count * 2; bool base_case = cpa_ix - offset == 0 ? true : false; - std::string cpa_name = "cpa_" + std::to_string(cpa_ix - offset) + "_"; + std::string cpa_name = stringf("cpa_%d", cpa_ix - offset); SigBit ci; if (base_case) From 7179e4f4b89bfea706fbeeff13722a0417bed766 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 25 Sep 2023 14:44:45 +0200 Subject: [PATCH 035/240] booth: Improve user interface --- passes/techmap/booth.cc | 49 +++++++++++++++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 9 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index aa5684b7427..b81225d0783 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -912,9 +912,7 @@ struct BoothPassWorker { int fa_count = x_sz + 4; int fa_row_count = enc_count - 1; - log("Signed multiplier generator using low Power Negative First Booth Algorithm. Multiplicand of size %d Multiplier of size %d. " - "Result of size %d. %d encoders %d decoders\n", - x_sz, y_sz, z_sz, enc_count, dec_count); + log_debug("Mapping %d x %d -> %d multiplier: %d encoders %d decoders\n", x_sz, y_sz, z_sz, enc_count, dec_count); SigSpec negi_n_int, twoi_n_int, onei_n_int, cori_n_int; @@ -1225,18 +1223,51 @@ struct BoothPassWorker { }; struct BoothPass : public Pass { - BoothPass() : Pass("booth", "Map $mul to booth multipliers") {} + BoothPass() : Pass("booth", "map $mul cells to Booth multipliers") {} + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" booth [selection]\n"); + log("\n"); + log("This pass replaces multiplier cells with an implementation based on the Booth\n"); + log("algorithm. It operates on $mul cells whose width of operands is at least 4x4\n"); + log("and whose width of result is at least 8. The detailed architecture is selected\n"); + log("from two options based on the signedness of the operands to the $mul cell.\n"); + log("\n"); + log("See the references below for the description of the architectures.\n"); + log("\n"); + log("Signed-multiplier architecture:\n"); + log("Y. J. Chang, Y. C. Cheng, S. C. Liao and C. H. Hsiao, \"A Low Power Radix-4 Booth\n"); + log("Multiplier With Pre-Encoded Mechanism,\" in IEEE Access, vol. 8, pp. 114842-114853,\n"); + log("2020, doi: 10.1109/ACCESS.2020.3003684\n"); + log("\n"); + log("Unsigned-multiplier architecture:\n"); + log("G. W. Bewick, \"Fast Multiplication: Algorithms and Implementations,\" PhD Thesis,\n"); + log("Department of Electrical Engineering, Stanford University, 1994\n"); + log("\n"); + } void execute(vector args, RTLIL::Design *design) override { - (void)args; - log_header(design, - "Executing booth pass. Generating Booth Multiplier structures for signed/unsigned multipliers of 4 bits or more\n"); - for (auto mod : design->selected_modules()) + log_header(design, "Executing BOOTH pass (map to Booth multipliers).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + break; + } + extra_args(args, argidx, design); + + int total = 0; + + for (auto mod : design->selected_modules()) { if (!mod->has_processes_warn()) { BoothPassWorker worker(mod); worker.run(); - log_header(design, "Created %d booth multipliers.\n", worker.booth_counter); + total += worker.booth_counter; } + } + + log("Mapped %d multipliers.\n", total); } } MultPass; From 91bcf81dbda538ddb23a992eedc6c3ec67bcec56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 25 Sep 2023 14:45:56 +0200 Subject: [PATCH 036/240] booth: Note down debug prints are broken --- passes/techmap/booth.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index b81225d0783..be38c8fc39f 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -52,6 +52,9 @@ or in generic synthesis call with -booth argument: synth -top my_design -booth */ +//FIXME: These debug prints are broken now, should be fixed or removed. +//#define DEBUG_CPA + #include "kernel/sigtools.h" #include "kernel/yosys.h" From 3319fdc46e3a66690b6a90ad5e47d8a665310984 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 25 Sep 2023 17:20:16 +0200 Subject: [PATCH 037/240] show: use dot for wire aliases instead of BUF --- passes/cmds/show.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 0dc5c452c09..d57cbc6bb49 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -575,7 +575,7 @@ struct ShowWorker } else { net_conn_map[right_node].in.insert({stringf("x%d", single_idx_count), GetSize(conn.first)}); net_conn_map[left_node].out.insert({stringf("x%d", single_idx_count), GetSize(conn.first)}); - fprintf(f, "x%d [shape=box, style=rounded, label=\"BUF\", %s];\n", single_idx_count++, findColor(conn).c_str()); + fprintf(f, "x%d [shape=point, %s];\n", single_idx_count++, findColor(conn).c_str()); } } } From 10d0e69588a64c0ef451b54d42e8741e4be260e9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 4 Apr 2023 20:52:30 +0200 Subject: [PATCH 038/240] ast/simplify: Make tweaks in advance of big in_lvalue/in_param change The following commit will replace the way in_lvalue/in_param is being tracked in the simplify code. Make tweaks in advance so that it will be easier to make the old way and the new way agree. These changes all should be innocuous. --- frontends/ast/simplify.cc | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index ee1be3781c8..7f2b76af090 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -47,7 +47,7 @@ Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_ std::vector args; for (size_t index = first_arg_at; index < children.size(); index++) { AstNode *node_arg = children[index]; - while (node_arg->simplify(true, false, stage, -1, false, false)) { } + while (node_arg->simplify(true, false, stage, -1, false, in_param)) { } VerilogFmtArg arg = {}; arg.filename = filename; @@ -91,7 +91,7 @@ void AstNode::annotateTypedEnums(AstNode *template_node) log_assert(current_scope.count(enum_type) == 1); AstNode *enum_node = current_scope.at(enum_type); log_assert(enum_node->type == AST_ENUM); - while (enum_node->simplify(true, false, 1, -1, false, true)) { } + while (enum_node->simplify(true, false, 1, -1, false, false)) { } //get width from 1st enum item: log_assert(enum_node->children.size() >= 1); AstNode *enum_item0 = enum_node->children[0]; @@ -457,7 +457,8 @@ static int get_max_offset(AstNode *node) static AstNode *make_packed_struct(AstNode *template_node, std::string &name, decltype(AstNode::attributes) &attributes) { // create a wire for the packed struct - auto wnode = new AstNode(AST_WIRE); + int offset = get_max_offset(template_node); + auto wnode = new AstNode(AST_WIRE, make_range(offset, 0)); wnode->str = name; wnode->is_logic = true; wnode->range_valid = true; @@ -465,9 +466,6 @@ static AstNode *make_packed_struct(AstNode *template_node, std::string &name, de for (auto &pair : attributes) { wnode->attributes[pair.first] = pair.second->clone(); } - int offset = get_max_offset(template_node); - auto range = make_range(offset, 0); - wnode->children.push_back(range); // make sure this node is the one in scope for this name current_scope[name] = wnode; // add all the struct members to scope under the wire's name @@ -980,7 +978,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin // when $display()/$write() functions are used in an always block, simplify the expressions and // convert them to a special cell later in genrtlil for (auto node : children) - while (node->simplify(true, false, stage, -1, false, false)) {} + while (node->simplify(true, false, stage, -1, false, in_param)) {} return false; } @@ -1806,7 +1804,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *template_node = resolved_type_node->children[0]; // Ensure typedef itself is fully simplified - while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, false)) {}; if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) { // replace instance with wire representing the packed structure @@ -1871,7 +1869,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *template_node = resolved_type_node->children[0]; // Ensure typedef itself is fully simplified - while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + while (template_node->simplify(const_fold, false, stage, width_hint, sign_hint, false)) {}; if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) { // replace with wire representing the packed structure @@ -2761,7 +2759,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (children[0]->id2ast->attributes.count(ID::nowrshmsk)) { AstNode *node = children[0]->id2ast->attributes.at(ID::nowrshmsk); - while (node->simplify(true, false, stage, -1, false, false)) { } + while (node->simplify(true, false, stage, -1, false, true)) { } if (node->type != AST_CONSTANT) input_error("Non-constant value for `nowrshmsk' attribute on `%s'!\n", children[0]->id2ast->str.c_str()); if (node->asAttrConst().as_bool()) @@ -3582,7 +3580,7 @@ skip_dynamic_range_lvalue_expansion:; } if (children.size() >= 1) { - while (children[0]->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (children[0]->simplify(true, false, stage, width_hint, sign_hint, in_param)) { } if (!children[0]->isConst()) input_error("Failed to evaluate system function `%s' with non-constant argument.\n", RTLIL::unescape_id(str).c_str()); @@ -3593,7 +3591,7 @@ skip_dynamic_range_lvalue_expansion:; } if (children.size() >= 2) { - while (children[1]->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (children[1]->simplify(true, false, stage, width_hint, sign_hint, in_param)) { } if (!children[1]->isConst()) input_error("Failed to evaluate system function `%s' with non-constant argument.\n", RTLIL::unescape_id(str).c_str()); @@ -3650,7 +3648,7 @@ skip_dynamic_range_lvalue_expansion:; // Determine which bits to count for (size_t i = 1; i < children.size(); i++) { AstNode *node = children[i]; - while (node->simplify(true, false, stage, -1, false, false)) { } + while (node->simplify(true, false, stage, -1, false, in_param)) { } if (node->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str.c_str()); if (node->bits.size() != 1) @@ -3855,7 +3853,7 @@ skip_dynamic_range_lvalue_expansion:; bool require_const_eval = decl->has_const_only_constructs(); bool all_args_const = true; for (auto child : children) { - while (child->simplify(true, false, 1, -1, false, true)) { } + while (child->simplify(true, in_lvalue, 1, -1, false, in_param)) { } if (child->type != AST_CONSTANT && child->type != AST_REALVALUE) all_args_const = false; } @@ -4048,7 +4046,7 @@ skip_dynamic_range_lvalue_expansion:; } } // updates the sizing - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, false, 1, -1, false, true)) { } delete arg; continue; } From 22b99413e8e22147aeb8a6492c21b456d56a9a90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 5 Apr 2023 11:00:07 +0200 Subject: [PATCH 039/240] ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree. --- frontends/ast/ast.cc | 26 ++++- frontends/ast/ast.h | 25 +++++ frontends/ast/genrtlil.cc | 11 ++- frontends/ast/simplify.cc | 202 +++++++++++++++++++++++++++++++------- 4 files changed, 222 insertions(+), 42 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index a027295e979..5a5851c3e6b 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -229,6 +229,10 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch id2ast = NULL; basic_prep = false; lookahead = false; + in_lvalue_from_above = false; + in_param_from_above = false; + in_lvalue = false; + in_param = false; if (child1) children.push_back(child1); @@ -238,6 +242,8 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch children.push_back(child3); if (child4) children.push_back(child4); + + fixup_hierarchy_flags(); } // create a (deep recursive) copy of a node @@ -249,6 +255,10 @@ AstNode *AstNode::clone() const it = it->clone(); for (auto &it : that->attributes) it.second = it.second->clone(); + + that->set_in_lvalue_flag(false); + that->set_in_param_flag(false); + that->fixup_hierarchy_flags(); // fixup to set flags on cloned children return that; } @@ -256,10 +266,13 @@ AstNode *AstNode::clone() const void AstNode::cloneInto(AstNode *other) const { AstNode *tmp = clone(); + tmp->in_lvalue_from_above = other->in_lvalue_from_above; + tmp->in_param_from_above = other->in_param_from_above; other->delete_children(); *other = *tmp; tmp->children.clear(); tmp->attributes.clear(); + other->fixup_hierarchy_flags(); delete tmp; } @@ -351,6 +364,10 @@ void AstNode::dumpAst(FILE *f, std::string indent) const if (is_enum) { fprintf(f, " type=enum"); } + if (in_lvalue) + fprintf(f, " in_lvalue"); + if (in_param) + fprintf(f, " in_param"); fprintf(f, "\n"); for (auto &it : attributes) { @@ -1091,7 +1108,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d ast->attributes.erase(ID::whitebox); } AstNode *n = ast->attributes.at(ID::lib_whitebox); - ast->attributes[ID::whitebox] = n; + ast->set_attribute(ID::whitebox, n); ast->attributes.erase(ID::lib_whitebox); } } @@ -1150,7 +1167,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d ast->children.swap(new_children); if (ast->attributes.count(ID::blackbox) == 0) { - ast->attributes[ID::blackbox] = AstNode::mkconst_int(1, false); + ast->set_attribute(ID::blackbox, AstNode::mkconst_int(1, false)); } } @@ -1298,6 +1315,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump flag_pwires = pwires; flag_autowire = autowire; + ast->fixup_hierarchy_flags(true); + log_assert(current_ast->type == AST_DESIGN); for (AstNode *child : current_ast->children) { @@ -1748,7 +1767,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictclone(); if (!new_ast->attributes.count(ID::hdlname)) - new_ast->attributes[ID::hdlname] = AstNode::mkconst_str(stripped_name); + new_ast->set_attribute(ID::hdlname, AstNode::mkconst_str(stripped_name)); para_counter = 0; for (auto child : new_ast->children) { @@ -1795,6 +1814,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictchildren.push_back(defparam); } + new_ast->fixup_hierarchy_flags(true); (*new_ast_out) = new_ast; return modname; } diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index e357579add2..cd6e254215a 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -221,6 +221,13 @@ namespace AST std::string filename; AstSrcLocType location; + // are we embedded in an lvalue, param? + // (see fixup_hierarchy_flags) + bool in_lvalue; + bool in_param; + bool in_lvalue_from_above; + bool in_param_from_above; + // creating and deleting nodes AstNode(AstNodeType type = AST_NONE, AstNode *child1 = nullptr, AstNode *child2 = nullptr, AstNode *child3 = nullptr, AstNode *child4 = nullptr); AstNode *clone() const; @@ -343,6 +350,24 @@ namespace AST // to evaluate widths of dynamic ranges) AstNode *clone_at_zero(); + void set_attribute(RTLIL::IdString key, AstNode *node) + { + attributes[key] = node; + node->set_in_param_flag(true); + } + + // helper to set in_lvalue/in_param flags from the hierarchy context (the actual flag + // can be overridden based on the intrinsic properties of this node, i.e. based on its type) + void set_in_lvalue_flag(bool flag, bool no_descend = false); + void set_in_param_flag(bool flag, bool no_descend = false); + + // fix up the hierarchy flags (in_lvalue/in_param) of this node and its children + // + // to keep the flags in sync, fixup_hierarchy_flags(true) needs to be called once after + // parsing the AST to walk the full tree, then plain fixup_hierarchy_flags() performs + // localized fixups after modifying children/attributes of a particular node + void fixup_hierarchy_flags(bool force_descend = false); + // helper to print errors from simplify/genrtlil code [[noreturn]] void input_error(const char *format, ...) const YS_ATTRIBUTE(format(printf, 2, 3)); }; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d62f06ae549..64626d9a966 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -176,8 +176,9 @@ struct AST_INTERNAL::LookaheadRewriter AstNode *wire = new AstNode(AST_WIRE); for (auto c : node->id2ast->children) wire->children.push_back(c->clone()); + wire->fixup_hierarchy_flags(); wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++); - wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); wire->is_logic = true; while (wire->simplify(true, false, 1, -1, false, false)) { } current_ast_mod->children.push_back(wire); @@ -1198,8 +1199,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun log_assert(range->type == AST_RANGE && range->children.size() == 2); AstNode *left = range->children.at(0)->clone(); AstNode *right = range->children.at(1)->clone(); - while (left->simplify(true, false, 1, -1, false, true)) { } - while (right->simplify(true, false, 1, -1, false, true)) { } + left->set_in_param_flag(true); + right->set_in_param_flag(true); + while (left->simplify(true, in_lvalue, 1, -1, false, true)) { } + while (right->simplify(true, in_lvalue, 1, -1, false, true)) { } if (left->type != AST_CONSTANT || right->type != AST_CONSTANT) input_error("Function %s has non-constant width!", RTLIL::unescape_id(str).c_str()); @@ -1552,7 +1555,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) children[0]->children[1]->clone() : children[0]->children[0]->clone()); fake_ast->children[0]->delete_children(); if (member_node) - fake_ast->children[0]->attributes[ID::wiretype] = member_node->clone(); + fake_ast->children[0]->set_attribute(ID::wiretype, member_node->clone()); int fake_ast_width = 0; bool fake_ast_sign = true; diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 7f2b76af090..4583f770b2c 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -41,6 +41,95 @@ YOSYS_NAMESPACE_BEGIN using namespace AST; using namespace AST_INTERNAL; +void AstNode::set_in_lvalue_flag(bool flag, bool no_descend) +{ + if (flag != in_lvalue_from_above) { + in_lvalue_from_above = flag; + if (!no_descend) + fixup_hierarchy_flags(); + } +} + +void AstNode::set_in_param_flag(bool flag, bool no_descend) +{ + if (flag != in_param_from_above) { + in_param_from_above = flag; + if (!no_descend) + fixup_hierarchy_flags(); + } +} + +void AstNode::fixup_hierarchy_flags(bool force_descend) +{ + // With forced descend, we disable the implicit + // descend from within the set_* functions, instead + // we do an explicit descend at the end of this function + + in_param = in_param_from_above; + + switch (type) { + case AST_PARAMETER: + case AST_LOCALPARAM: + case AST_DEFPARAM: + case AST_PARASET: + case AST_PREFIX: + in_param = true; + for (auto child : children) + child->set_in_param_flag(true, force_descend); + break; + + case AST_REPLICATE: + case AST_WIRE: + case AST_GENIF: + case AST_GENCASE: + for (auto child : children) + child->set_in_param_flag(in_param, force_descend); + if (children.size() >= 1) + children[0]->set_in_param_flag(true, force_descend); + break; + + case AST_GENFOR: + case AST_FOR: + for (auto child : children) + child->set_in_param_flag(in_param, force_descend); + if (children.size() >= 2) + children[1]->set_in_param_flag(true, force_descend); + break; + + default: + in_param = in_param_from_above; + for (auto child : children) + child->set_in_param_flag(in_param, force_descend); + } + + for (auto attr : attributes) + attr.second->set_in_param_flag(true, force_descend); + + in_lvalue = in_lvalue_from_above; + + switch (type) { + case AST_ASSIGN: + case AST_ASSIGN_EQ: + case AST_ASSIGN_LE: + if (children.size() >= 1) + children[0]->set_in_lvalue_flag(true, force_descend); + if (children.size() >= 2) + children[1]->set_in_lvalue_flag(in_lvalue, force_descend); + break; + + default: + for (auto child : children) + child->set_in_lvalue_flag(in_lvalue, force_descend); + } + + if (force_descend) { + for (auto child : children) + child->fixup_hierarchy_flags(true); + for (auto attr : attributes) + attr.second->fixup_hierarchy_flags(true); + } +} + // Process a format string and arguments for $display, $write, $sprintf, etc Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_t first_arg_at) { @@ -132,7 +221,7 @@ void AstNode::annotateTypedEnums(AstNode *template_node) RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed); enum_item_str.append(val.as_string()); //set attribute for available val to enum item name mappings - attributes[enum_item_str.c_str()] = mkconst_str(enum_item->str); + set_attribute(enum_item_str.c_str(), mkconst_str(enum_item->str)); } } } @@ -464,7 +553,7 @@ static AstNode *make_packed_struct(AstNode *template_node, std::string &name, de wnode->range_valid = true; wnode->is_signed = template_node->is_signed; for (auto &pair : attributes) { - wnode->attributes[pair.first] = pair.second->clone(); + wnode->set_attribute(pair.first, pair.second->clone()); } // make sure this node is the one in scope for this name current_scope[name] = wnode; @@ -525,7 +614,7 @@ const RTLIL::Module* AstNode::lookup_cell_module() auto reprocess_after = [this] (const std::string &modname) { if (!attributes.count(ID::reprocess_after)) - attributes[ID::reprocess_after] = AstNode::mkconst_str(modname); + set_attribute(ID::reprocess_after, AstNode::mkconst_str(modname)); }; const AstNode *celltype = nullptr; @@ -705,6 +794,11 @@ AstNode *AstNode::clone_at_zero() it = it->clone_at_zero(); for (auto &it : that->attributes) it.second = it.second->clone(); + + that->set_in_lvalue_flag(false); + that->set_in_param_flag(false); + that->fixup_hierarchy_flags(); + return that; } @@ -743,8 +837,7 @@ static void mark_auto_nosync(AstNode *block, const AstNode *wire) { log_assert(block->type == AST_BLOCK); log_assert(wire->type == AST_WIRE); - block->attributes[auto_nosync_prefix + wire->str] = AstNode::mkconst_int(1, - false); + block->set_attribute(auto_nosync_prefix + wire->str, AstNode::mkconst_int(1, false)); } // block names can be prefixed with an explicit scope during elaboration @@ -785,7 +878,7 @@ static void check_auto_nosync(AstNode *node) // mark the wire with `nosync` AstNode *wire = it->second; log_assert(wire->type == AST_WIRE); - wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); } // remove the attributes we've "consumed" @@ -806,7 +899,7 @@ static void check_auto_nosync(AstNode *node) // // this function also does all name resolving and sets the id2ast member of all // nodes that link to a different node using names and lexical scoping. -bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param) +bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hint, bool sign_hint, bool in_param_) { static int recursion_counter = 0; static bool deep_recursion_warning = false; @@ -913,7 +1006,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin reg->is_signed = node->is_signed; for (auto &it : node->attributes) if (it.first != ID::mem2reg) - reg->attributes.emplace(it.first, it.second->clone()); + reg->set_attribute(it.first, it.second->clone()); reg->filename = node->filename; reg->location = node->location; children.push_back(reg); @@ -994,7 +1087,9 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin // in certain cases a function must be evaluated constant. this is what in_param controls. if (type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_PREFIX) - in_param = true; + in_param_ = true; + log_assert(in_param == in_param_); + log_assert(in_lvalue == in_lvalue_); std::map backup_scope; @@ -1015,7 +1110,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (!c->is_simple_const_expr()) { if (attributes.count(ID::dynports)) delete attributes.at(ID::dynports); - attributes[ID::dynports] = AstNode::mkconst_int(1, true); + set_attribute(ID::dynports, AstNode::mkconst_int(1, true)); } } } @@ -1064,7 +1159,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin for (auto &it : node->attributes) { if (first_node->attributes.count(it.first) > 0) delete first_node->attributes[it.first]; - first_node->attributes[it.first] = it.second->clone(); + first_node->set_attribute(it.first, it.second->clone()); } children.erase(children.begin()+(i--)); did_something = true; @@ -1261,6 +1356,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin asgn->children.push_back(arg); asgn->children.push_back(ident); } + asgn->fixup_hierarchy_flags(); } @@ -1382,7 +1478,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin range_left = template_node->range_left; range_right = template_node->range_right; - attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); + set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str)); // Copy clones of children from template for (auto template_child : template_node->children) { @@ -1414,7 +1510,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (children[0]->type == AST_IDENTIFIER && current_scope.count(children[0]->str) > 0) { auto item_node = current_scope[children[0]->str]; if (item_node->type == AST_STRUCT || item_node->type == AST_UNION) { - attributes[ID::wiretype] = item_node->clone(); + set_attribute(ID::wiretype, item_node->clone()); size_packed_struct(attributes[ID::wiretype], 0); add_members_to_scope(attributes[ID::wiretype], str); } @@ -1809,7 +1905,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) { // replace instance with wire representing the packed structure newNode = make_packed_struct(template_node, str, attributes); - newNode->attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); + newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str)); // add original input/output attribute to resolved wire newNode->is_input = this->is_input; newNode->is_output = this->is_output; @@ -1834,7 +1930,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin range_left = template_node->range_left; range_right = template_node->range_right; - attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); + set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str)); // if an enum then add attributes to support simulator tracing annotateTypedEnums(template_node); @@ -1848,6 +1944,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *rng = make_range(0, 0); children.insert(children.begin(), rng); } + fixup_hierarchy_flags(); did_something = true; } log_assert(!is_custom_type); @@ -1874,7 +1971,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) { // replace with wire representing the packed structure newNode = make_packed_struct(template_node, str, attributes); - newNode->attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); + newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str)); newNode->type = type; current_scope[str] = this; // copy param value, it needs to be 1st value @@ -1896,9 +1993,10 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin range_swapped = template_node->range_swapped; range_left = template_node->range_left; range_right = template_node->range_right; - attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); + set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str)); for (auto template_child : template_node->children) children.push_back(template_child->clone()); + fixup_hierarchy_flags(); did_something = true; } log_assert(!is_custom_type); @@ -2018,6 +2116,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin } delete children[1]; children[1] = new AstNode(AST_RANGE, AstNode::mkconst_int(0, true), AstNode::mkconst_int(total_size-1, true)); + fixup_hierarchy_flags(); did_something = true; } @@ -2052,6 +2151,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin else children[0] = new AstNode(AST_RANGE, index_expr); + fixup_hierarchy_flags(); did_something = true; } @@ -2067,6 +2167,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin children[0]->realvalue, log_signal(constvalue)); delete children[0]; children[0] = mkconst_bits(constvalue.bits, sign_hint); + fixup_hierarchy_flags(); did_something = true; } if (children[0]->type == AST_CONSTANT) { @@ -2076,6 +2177,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *old_child_0 = children[0]; children[0] = mkconst_bits(sig.as_const().bits, is_signed); delete old_child_0; + fixup_hierarchy_flags(); } children[0]->is_signed = is_signed; } @@ -2089,6 +2191,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin delete children[0]; children[0] = new AstNode(AST_REALVALUE); children[0]->realvalue = as_realvalue; + fixup_hierarchy_flags(); did_something = true; } } @@ -2105,7 +2208,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin newNode = new AstNode(AST_IDENTIFIER, range); newNode->str = sname; // save type and original number of dimensions for $size() etc. - newNode->attributes[ID::wiretype] = item_node->clone(); + newNode->set_attribute(ID::wiretype, item_node->clone()); if (!item_node->multirange_dimensions.empty() && children.size() > 0) { if (children[0]->type == AST_RANGE) newNode->integer = 1; @@ -2199,7 +2302,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true))); wire->str = wire_id; if (current_block) - wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); current_ast_mod->children.push_back(wire); while (wire->simplify(true, false, 1, -1, false, false)) { } @@ -2387,6 +2490,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin // eval 3rd expression buf = next_ast->children[1]->clone(); + buf->set_in_param_flag(true); { int expr_width_hint = -1; bool expr_sign_hint = true; @@ -2548,6 +2652,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin continue; buf = child->clone(); + buf->set_in_param_flag(true); while (buf->simplify(true, false, stage, width_hint, sign_hint, true)) { } if (buf->type != AST_CONSTANT) { // for (auto f : log_files) @@ -2654,6 +2759,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin children.push_back(children_list.at(0)); children.back()->was_checked = true; children.push_back(node); + fixup_hierarchy_flags(); did_something = true; } else if (str == "buf" || str == "not") @@ -2704,6 +2810,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin children.push_back(children_list[0]); children.back()->was_checked = true; children.push_back(node); + fixup_hierarchy_flags(); did_something = true; } } @@ -2782,7 +2889,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *lvalue = children[0]->clone(); lvalue->delete_children(); if (member_node) - lvalue->attributes[ID::wiretype] = member_node->clone(); + lvalue->set_attribute(ID::wiretype, member_node->clone()); lvalue->children.push_back(new AstNode(AST_RANGE, mkconst_int(end_bit, true), mkconst_int(start_bit, true))); cond->children.push_back(new AstNode(AST_BLOCK, new AstNode(type, lvalue, children[1]->clone()))); @@ -2795,14 +2902,14 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true))); wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); - wire_mask->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire_mask->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); wire_mask->is_logic = true; while (wire_mask->simplify(true, false, 1, -1, false, false)) { } current_ast_mod->children.push_back(wire_mask); AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true))); wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); - wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); wire_data->is_logic = true; while (wire_data->simplify(true, false, 1, -1, false, false)) { } current_ast_mod->children.push_back(wire_data); @@ -2813,7 +2920,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *wire_sel = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(shamt_width_hint-1, true), mkconst_int(0, true))); wire_sel->str = stringf("$bitselwrite$sel$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); - wire_sel->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire_sel->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); wire_sel->is_logic = true; wire_sel->is_signed = shamt_sign_hint; while (wire_sel->simplify(true, false, 1, -1, false, false)) { } @@ -2825,7 +2932,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *lvalue = children[0]->clone(); lvalue->delete_children(); if (member_node) - lvalue->attributes[ID::wiretype] = member_node->clone(); + lvalue->set_attribute(ID::wiretype, member_node->clone()); AstNode *ref_mask = new AstNode(AST_IDENTIFIER); ref_mask->str = wire_mask->str; @@ -2882,6 +2989,8 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin t = new AstNode(AST_BIT_OR, t, ref_data); t = new AstNode(type, lvalue, t); newNode->children.push_back(t); + + newNode->fixup_hierarchy_flags(true); } goto apply_newNode; @@ -2942,6 +3051,7 @@ skip_dynamic_range_lvalue_expansion:; assign_check->children[0]->str = id_check; assign_check->children[0]->was_checked = true; } + assign_check->fixup_hierarchy_flags(); if (current_always == nullptr || current_always->type != AST_INITIAL) { assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(1, false, 1)); @@ -2951,6 +3061,7 @@ skip_dynamic_range_lvalue_expansion:; } assign_en->children[0]->str = id_en; assign_en->children[0]->was_checked = true; + assign_en->fixup_hierarchy_flags(); newNode = new AstNode(AST_BLOCK); if (assign_check != nullptr) @@ -2973,6 +3084,7 @@ skip_dynamic_range_lvalue_expansion:; if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && children.size() == 1) { children.push_back(mkconst_int(1, false, 1)); + fixup_hierarchy_flags(); did_something = true; } @@ -3003,7 +3115,7 @@ skip_dynamic_range_lvalue_expansion:; wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); current_ast_mod->children.push_back(wire_tmp); current_scope[wire_tmp->str] = wire_tmp; - wire_tmp->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire_tmp->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); while (wire_tmp->simplify(true, false, 1, -1, false, false)) { } wire_tmp->is_logic = true; @@ -3743,6 +3855,7 @@ skip_dynamic_range_lvalue_expansion:; argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str)); args.push_back(children.at(i-2)->clone()); + args.back()->set_in_param_flag(true); while (args.back()->simplify(true, false, stage, -1, false, true)) { } if (args.back()->type != AST_CONSTANT && args.back()->type != AST_REALVALUE) @@ -3860,6 +3973,7 @@ skip_dynamic_range_lvalue_expansion:; if (all_args_const) { AstNode *func_workspace = decl->clone(); + func_workspace->set_in_param_flag(true); func_workspace->str = prefix_id(prefix, "$result"); newNode = func_workspace->eval_const_function(this, in_param || require_const_eval); delete func_workspace; @@ -4004,9 +4118,9 @@ skip_dynamic_range_lvalue_expansion:; wire->is_input = false; wire->is_output = false; wire->is_reg = true; - wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); if (child->type == AST_ENUM_ITEM) - wire->attributes[ID::enum_base_type] = child->attributes[ID::enum_base_type]; + wire->set_attribute(ID::enum_base_type, child->attributes[ID::enum_base_type]); wire_cache[child->str] = wire; @@ -4045,6 +4159,7 @@ skip_dynamic_range_lvalue_expansion:; range->children.push_back(mkconst_int(0, true)); } } + wire->fixup_hierarchy_flags(); // updates the sizing while (wire->simplify(true, false, 1, -1, false, true)) { } delete arg; @@ -4364,6 +4479,7 @@ replace_fcall_later:; newNode->filename = filename; newNode->location = location; newNode->cloneInto(this); + fixup_hierarchy_flags(); delete newNode; did_something = true; } @@ -4954,7 +5070,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, wire_addr->str = id_addr; wire_addr->is_reg = true; wire_addr->was_checked = true; - wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire_addr->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); mod->children.push_back(wire_addr); while (wire_addr->simplify(true, false, 1, -1, false, false)) { } @@ -4963,7 +5079,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, wire_data->is_reg = true; wire_data->was_checked = true; wire_data->is_signed = mem_signed; - wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); mod->children.push_back(wire_data); while (wire_data->simplify(true, false, 1, -1, false, false)) { } @@ -4992,6 +5108,10 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, cond_node->children[1]->children.push_back(assign_reg); case_node->children.push_back(cond_node); } + + // fixup on the full hierarchy below case_node + case_node->fixup_hierarchy_flags(true); + block->children.insert(block->children.begin()+assign_idx+2, case_node); children[0]->delete_children(); @@ -5001,6 +5121,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, type = AST_ASSIGN_EQ; children[0]->was_checked = true; + fixup_hierarchy_flags(); did_something = true; } @@ -5071,7 +5192,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, wire_addr->is_reg = true; wire_addr->was_checked = true; if (block) - wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire_addr->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); mod->children.push_back(wire_addr); while (wire_addr->simplify(true, false, 1, -1, false, false)) { } @@ -5081,7 +5202,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, wire_data->was_checked = true; wire_data->is_signed = mem_signed; if (block) - wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); mod->children.push_back(wire_data); while (wire_data->simplify(true, false, 1, -1, false, false)) { } @@ -5115,6 +5236,9 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, cond_node->children[1]->children.push_back(assign_reg); case_node->children.push_back(cond_node); + // fixup on the full hierarchy below case_node + case_node->fixup_hierarchy_flags(true); + if (block) { size_t assign_idx = 0; @@ -5126,10 +5250,10 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, } else { - AstNode *proc = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK)); - proc->children[0]->children.push_back(case_node); + AstNode *proc = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK, case_node)); mod->children.push_back(proc); mod->children.push_back(assign_addr); + mod->fixup_hierarchy_flags(); } delete_children(); @@ -5138,8 +5262,10 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, str = id_data; } - if (bit_part_sel) + if (bit_part_sel) { children.push_back(bit_part_sel); + fixup_hierarchy_flags(); + } did_something = true; } @@ -5302,6 +5428,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) { block->children.push_back(child->clone()); } + block->set_in_param_flag(true); while (!block->children.empty()) { @@ -5444,6 +5571,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) AstNode *cond = stmt->children.at(0)->clone(); if (!cond->replace_variables(variables, fcall, must_succeed)) goto finished; + cond->set_in_param_flag(true); while (cond->simplify(true, false, 1, -1, false, true)) { } if (cond->type != AST_CONSTANT) { @@ -5469,6 +5597,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) AstNode *num = stmt->children.at(0)->clone(); if (!num->replace_variables(variables, fcall, must_succeed)) goto finished; + num->set_in_param_flag(true); while (num->simplify(true, false, 1, -1, false, true)) { } if (num->type != AST_CONSTANT) { @@ -5492,6 +5621,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) AstNode *expr = stmt->children.at(0)->clone(); if (!expr->replace_variables(variables, fcall, must_succeed)) goto finished; + expr->set_in_param_flag(true); while (expr->simplify(true, false, 1, -1, false, true)) { } AstNode *sel_case = NULL; @@ -5512,6 +5642,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) goto finished; cond = new AstNode(AST_EQ, expr->clone(), cond); + cond->set_in_param_flag(true); while (cond->simplify(true, false, 1, -1, false, true)) { } if (cond->type != AST_CONSTANT) { @@ -5547,6 +5678,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) block->children.erase(block->children.begin()); block->children.insert(block->children.begin(), stmt->children.begin(), stmt->children.end()); stmt->children.clear(); + block->fixup_hierarchy_flags(); delete stmt; continue; } @@ -5581,7 +5713,7 @@ void AstNode::allocateDefaultEnumValues() int last_enum_int = -1; for (auto node : children) { log_assert(node->type==AST_ENUM_ITEM); - node->attributes[ID::enum_base_type] = mkconst_str(str); + node->set_attribute(ID::enum_base_type, mkconst_str(str)); for (size_t i = 0; i < node->children.size(); i++) { switch (node->children[i]->type) { case AST_NONE: From a511976b489ab266a511b9d8d96ee7e5001c9306 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 4 Apr 2023 22:59:44 +0200 Subject: [PATCH 040/240] ast/simplify: Retire in_lvalue/in_param arguments to simplify --- frontends/ast/ast.cc | 4 +- frontends/ast/ast.h | 2 +- frontends/ast/genrtlil.cc | 26 ++--- frontends/ast/simplify.cc | 197 ++++++++++++++++++-------------------- 4 files changed, 110 insertions(+), 119 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 5a5851c3e6b..5335a3992d6 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1078,7 +1078,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d // simplify this module or interface using the current design as context // for lookup up ports and wires within cells set_simplify_design_context(design); - while (ast->simplify(!flag_noopt, false, 0, -1, false, false)) { } + while (ast->simplify(!flag_noopt, 0, -1, false)) { } set_simplify_design_context(nullptr); if (flag_dump_ast2) { @@ -1380,7 +1380,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump } else if (child->type == AST_PACKAGE) { // process enum/other declarations - child->simplify(true, false, 1, -1, false, false); + child->simplify(true, 1, -1, false); rename_in_package_stmts(child); design->verilog_packages.push_back(child->clone()); current_scope.clear(); diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index cd6e254215a..f789e930b3e 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -258,7 +258,7 @@ namespace AST // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc. // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL() - bool simplify(bool const_fold, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param); + bool simplify(bool const_fold, int stage, int width_hint, bool sign_hint); void replace_result_wire_name_in_function(const std::string &from, const std::string &to); AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init); void expand_genblock(const std::string &prefix); diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 64626d9a966..6e750863fbe 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -180,7 +180,7 @@ struct AST_INTERNAL::LookaheadRewriter wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++); wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); wire->is_logic = true; - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } current_ast_mod->children.push_back(wire); lookaheadids[node->str] = make_pair(node->id2ast, wire); wire->genRTLIL(); @@ -927,7 +927,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1; } else { if (id_ast->children[0]->type != AST_CONSTANT) - while (id_ast->simplify(true, false, 1, -1, false, true)) { } + while (id_ast->simplify(true, 1, -1, false)) { } if (id_ast->children[0]->type == AST_CONSTANT) this_width = id_ast->children[0]->bits.size(); else @@ -971,8 +971,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun else if (!range->range_valid) { AstNode *left_at_zero_ast = children[0]->children[0]->clone_at_zero(); AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone_at_zero() : left_at_zero_ast->clone(); - while (left_at_zero_ast->simplify(true, false, 1, -1, false, false)) { } - while (right_at_zero_ast->simplify(true, false, 1, -1, false, false)) { } + while (left_at_zero_ast->simplify(true, 1, -1, false)) { } + while (right_at_zero_ast->simplify(true, 1, -1, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; @@ -988,7 +988,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun break; case AST_TO_BITS: - while (children[0]->simplify(true, false, 1, -1, false, false) == true) { } + while (children[0]->simplify(true, 1, -1, false) == true) { } if (children[0]->type != AST_CONSTANT) input_error("Left operand of tobits expression is not constant!\n"); children[1]->detectSignWidthWorker(sub_width_hint, sign_hint); @@ -1010,7 +1010,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun break; case AST_CAST_SIZE: - while (children.at(0)->simplify(true, false, 1, -1, false, false)) { } + while (children.at(0)->simplify(true, 1, -1, false)) { } if (children.at(0)->type != AST_CONSTANT) input_error("Static cast with non constant expression!\n"); children.at(1)->detectSignWidthWorker(width_hint, sign_hint); @@ -1032,7 +1032,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun break; case AST_REPLICATE: - while (children[0]->simplify(true, false, 1, -1, false, true) == true) { } + while (children[0]->simplify(true, 1, -1, false) == true) { } if (children[0]->type != AST_CONSTANT) input_error("Left operand of replicate expression is not constant!\n"); children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint); @@ -1144,7 +1144,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun case AST_PREFIX: // Prefix nodes always resolve to identifiers in generate loops, so we // can simply perform the resolution to determine the sign and width. - simplify(true, false, 1, -1, false, false); + simplify(true, 1, -1, false); log_assert(type == AST_IDENTIFIER); detectSignWidthWorker(width_hint, sign_hint, found_real); break; @@ -1152,7 +1152,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun case AST_FCALL: if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") { if (GetSize(children) == 1) { - while (children[0]->simplify(true, false, 1, -1, false, true) == true) { } + while (children[0]->simplify(true, 1, -1, false) == true) { } if (children[0]->type != AST_CONSTANT) input_error("System function %s called with non-const argument!\n", RTLIL::unescape_id(str).c_str()); @@ -1201,8 +1201,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun AstNode *right = range->children.at(1)->clone(); left->set_in_param_flag(true); right->set_in_param_flag(true); - while (left->simplify(true, in_lvalue, 1, -1, false, true)) { } - while (right->simplify(true, in_lvalue, 1, -1, false, true)) { } + while (left->simplify(true, 1, -1, false)) { } + while (right->simplify(true, 1, -1, false)) { } if (left->type != AST_CONSTANT || right->type != AST_CONSTANT) input_error("Function %s has non-constant width!", RTLIL::unescape_id(str).c_str()); @@ -1546,8 +1546,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (!children[0]->range_valid) { AstNode *left_at_zero_ast = children[0]->children[0]->clone_at_zero(); AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone_at_zero() : left_at_zero_ast->clone(); - while (left_at_zero_ast->simplify(true, false, 1, -1, false, false)) { } - while (right_at_zero_ast->simplify(true, false, 1, -1, false, false)) { } + while (left_at_zero_ast->simplify(true, 1, -1, false)) { } + while (right_at_zero_ast->simplify(true, 1, -1, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 4583f770b2c..c4a30302712 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -136,7 +136,7 @@ Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_ std::vector args; for (size_t index = first_arg_at; index < children.size(); index++) { AstNode *node_arg = children[index]; - while (node_arg->simplify(true, false, stage, -1, false, in_param)) { } + while (node_arg->simplify(true, stage, -1, false)) { } VerilogFmtArg arg = {}; arg.filename = filename; @@ -180,7 +180,7 @@ void AstNode::annotateTypedEnums(AstNode *template_node) log_assert(current_scope.count(enum_type) == 1); AstNode *enum_node = current_scope.at(enum_type); log_assert(enum_node->type == AST_ENUM); - while (enum_node->simplify(true, false, 1, -1, false, false)) { } + while (enum_node->simplify(true, 1, -1, false)) { } //get width from 1st enum item: log_assert(enum_node->children.size() >= 1); AstNode *enum_item0 = enum_node->children[0]; @@ -814,8 +814,8 @@ static bool try_determine_range_width(AstNode *range, int &result_width) AstNode *left_at_zero_ast = range->children[0]->clone_at_zero(); AstNode *right_at_zero_ast = range->children[1]->clone_at_zero(); - while (left_at_zero_ast->simplify(true, false, 1, -1, false, false)) {} - while (right_at_zero_ast->simplify(true, false, 1, -1, false, false)) {} + while (left_at_zero_ast->simplify(true, 1, -1, false)) {} + while (right_at_zero_ast->simplify(true, 1, -1, false)) {} bool ok = false; if (left_at_zero_ast->type == AST_CONSTANT @@ -899,7 +899,7 @@ static void check_auto_nosync(AstNode *node) // // this function also does all name resolving and sets the id2ast member of all // nodes that link to a different node using names and lexical scoping. -bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hint, bool sign_hint, bool in_param_) +bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hint) { static int recursion_counter = 0; static bool deep_recursion_warning = false; @@ -917,8 +917,8 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi #if 0 log("-------------\n"); log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, filename.c_str(), location.first_line, type2str(type).c_str(), this); - log("const_fold=%d, in_lvalue=%d, stage=%d, width_hint=%d, sign_hint=%d, in_param=%d\n", - int(const_fold), int(in_lvalue), int(stage), int(width_hint), int(sign_hint), int(in_param)); + log("const_fold=%d, stage=%d, width_hint=%d, sign_hint=%d\n", + int(const_fold), int(stage), int(width_hint), int(sign_hint)); // dumpAst(NULL, "> "); #endif @@ -927,7 +927,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi log_assert(type == AST_MODULE || type == AST_INTERFACE); deep_recursion_warning = true; - while (simplify(const_fold, in_lvalue, 1, width_hint, sign_hint, in_param)) { } + while (simplify(const_fold, 1, width_hint, sign_hint)) { } if (!flag_nomem2reg && !get_bool_attribute(ID::nomem2reg)) { @@ -1010,7 +1010,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi reg->filename = node->filename; reg->location = node->location; children.push_back(reg); - while (reg->simplify(true, false, 1, -1, false, false)) { } + while (reg->simplify(true, 1, -1, false)) { } } } @@ -1024,7 +1024,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi delete node; } - while (simplify(const_fold, in_lvalue, 2, width_hint, sign_hint, in_param)) { } + while (simplify(const_fold, 2, width_hint, sign_hint)) { } recursion_counter--; return false; } @@ -1071,7 +1071,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi // when $display()/$write() functions are used in an always block, simplify the expressions and // convert them to a special cell later in genrtlil for (auto node : children) - while (node->simplify(true, false, stage, -1, false, in_param)) {} + while (node->simplify(true, stage, -1, false)) {} return false; } @@ -1085,12 +1085,6 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi if (type == AST_IDENTIFIER && current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM || current_scope[str]->type == AST_ENUM_ITEM)) const_fold = true; - // in certain cases a function must be evaluated constant. this is what in_param controls. - if (type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_PREFIX) - in_param_ = true; - log_assert(in_param == in_param_); - log_assert(in_lvalue == in_lvalue_); - std::map backup_scope; // create name resolution entries for all objects with names @@ -1193,12 +1187,12 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi for (size_t i = 0; i < children.size(); i++) { AstNode *node = children[i]; if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY || node->type == AST_TYPEDEF) - while (node->simplify(true, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM)) + while (node->simplify(true, 1, -1, false)) did_something = true; if (node->type == AST_ENUM) { for (auto enode : node->children){ log_assert(enode->type==AST_ENUM_ITEM); - while (node->simplify(true, false, 1, -1, false, in_param)) + while (node->simplify(true, 1, -1, false)) did_something = true; } } @@ -1263,7 +1257,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi for (AstNode *child : children) { // simplify any parameters to constants if (child->type == AST_PARASET) - while (child->simplify(true, false, 1, -1, false, true)) { } + while (child->simplify(true, 1, -1, false)) { } // look for patterns which _may_ indicate ambiguity requiring // resolution of the underlying module @@ -1378,9 +1372,9 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi case AST_ASSIGN_EQ: case AST_ASSIGN_LE: case AST_ASSIGN: - while (!children[0]->basic_prep && children[0]->simplify(false, true, stage, -1, false, in_param) == true) + while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false) == true) did_something = true; - while (!children[1]->basic_prep && children[1]->simplify(false, false, stage, -1, false, in_param) == true) + while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false) == true) did_something = true; children[0]->detectSignWidth(backup_width_hint, backup_sign_hint); children[1]->detectSignWidth(width_hint, sign_hint); @@ -1416,7 +1410,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi if (!basic_prep) { for (auto *node : children) { // resolve any ranges - while (!node->basic_prep && node->simplify(true, false, stage, -1, false, false)) { + while (!node->basic_prep && node->simplify(true, stage, -1, false)) { did_something = true; } } @@ -1449,7 +1443,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi AstNode *template_node = resolved_type_node->children[0]; // Ensure typedef itself is fully simplified - while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + while (template_node->simplify(const_fold, stage, width_hint, sign_hint)) {}; // Remove type reference delete children[0]; @@ -1495,7 +1489,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi //log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep); if (!basic_prep) { for (auto item_node : children) { - while (!item_node->basic_prep && item_node->simplify(false, false, stage, -1, false, in_param)) + while (!item_node->basic_prep && item_node->simplify(false, stage, -1, false)) did_something = true; } // allocate values (called more than once) @@ -1515,11 +1509,11 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi add_members_to_scope(attributes[ID::wiretype], str); } } - while (!children[0]->basic_prep && children[0]->simplify(false, false, stage, -1, false, true) == true) + while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false) == true) did_something = true; children[0]->detectSignWidth(width_hint, sign_hint); if (children.size() > 1 && children[1]->type == AST_RANGE) { - while (!children[1]->basic_prep && children[1]->simplify(false, false, stage, -1, false, true) == true) + while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false) == true) did_something = true; if (!children[1]->range_valid) input_error("Non-constant width range on parameter decl.\n"); @@ -1527,11 +1521,11 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi } break; case AST_ENUM_ITEM: - while (!children[0]->basic_prep && children[0]->simplify(false, false, stage, -1, false, in_param)) + while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false)) did_something = true; children[0]->detectSignWidth(width_hint, sign_hint); if (children.size() > 1 && children[1]->type == AST_RANGE) { - while (!children[1]->basic_prep && children[1]->simplify(false, false, stage, -1, false, in_param)) + while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false)) did_something = true; if (!children[1]->range_valid) input_error("Non-constant width range on enum item decl.\n"); @@ -1590,7 +1584,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi width_hint = -1; sign_hint = true; for (auto child : children) { - while (!child->basic_prep && child->simplify(false, in_lvalue, stage, -1, false, in_param) == true) + while (!child->basic_prep && child->simplify(false, stage, -1, false) == true) did_something = true; child->detectSignWidthWorker(width_hint, sign_hint); } @@ -1625,10 +1619,10 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi if (detect_width_simple && width_hint < 0) { if (type == AST_REPLICATE) - while (children[0]->simplify(true, in_lvalue, stage, -1, false, true) == true) + while (children[0]->simplify(true, stage, -1, false) == true) did_something = true; for (auto child : children) - while (!child->basic_prep && child->simplify(false, in_lvalue, stage, -1, false, in_param) == true) + while (!child->basic_prep && child->simplify(false, stage, -1, false) == true) did_something = true; detectSignWidth(width_hint, sign_hint); } @@ -1638,18 +1632,18 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi if (type == AST_TERNARY) { if (width_hint < 0) { - while (!children[0]->basic_prep && children[0]->simplify(true, in_lvalue, stage, -1, false, in_param)) + while (!children[0]->basic_prep && children[0]->simplify(true, stage, -1, false)) did_something = true; bool backup_unevaluated_tern_branch = unevaluated_tern_branch; AstNode *chosen = get_tern_choice().first; unevaluated_tern_branch = backup_unevaluated_tern_branch || chosen == children[2]; - while (!children[1]->basic_prep && children[1]->simplify(false, in_lvalue, stage, -1, false, in_param)) + while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false)) did_something = true; unevaluated_tern_branch = backup_unevaluated_tern_branch || chosen == children[1]; - while (!children[2]->basic_prep && children[2]->simplify(false, in_lvalue, stage, -1, false, in_param)) + while (!children[2]->basic_prep && children[2]->simplify(false, stage, -1, false)) did_something = true; unevaluated_tern_branch = backup_unevaluated_tern_branch; @@ -1681,7 +1675,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi if (const_fold && type == AST_CASE) { detectSignWidth(width_hint, sign_hint); - while (children[0]->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) { } + while (children[0]->simplify(const_fold, stage, width_hint, sign_hint)) { } if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) { children[0]->is_signed = sign_hint; RTLIL::Const case_expr = children[0]->bitsAsConst(width_hint, sign_hint); @@ -1695,7 +1689,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi goto keep_const_cond; if (v->type == AST_BLOCK) continue; - while (v->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) { } + while (v->simplify(const_fold, stage, width_hint, sign_hint)) { } if (v->type == AST_CONSTANT && v->bits_only_01()) { RTLIL::Const case_item_expr = v->bitsAsConst(width_hint, sign_hint); RTLIL::Const match = const_eq(case_expr, case_item_expr, sign_hint, sign_hint, 1); @@ -1752,20 +1746,18 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi unevaluated_tern_branch = chosen && chosen != children[i]; } while (did_something_here && i < children.size()) { - bool const_fold_here = const_fold, in_lvalue_here = in_lvalue; + bool const_fold_here = const_fold; int width_hint_here = width_hint; bool sign_hint_here = sign_hint; bool in_param_here = in_param; if (i == 0 && (type == AST_REPLICATE || type == AST_WIRE)) - const_fold_here = true, in_param_here = true; + const_fold_here = true; if (i == 0 && (type == AST_GENIF || type == AST_GENCASE)) in_param_here = true; if (i == 1 && (type == AST_FOR || type == AST_GENFOR)) in_param_here = true; if (type == AST_PARAMETER || type == AST_LOCALPARAM) const_fold_here = true; - if (i == 0 && (type == AST_ASSIGN || type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE)) - in_lvalue_here = true; if (type == AST_BLOCK) { current_block = this; current_block_child = children[i]; @@ -1780,7 +1772,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi width_hint_here = -1, sign_hint_here = false; if (children_are_self_determined) width_hint_here = -1, sign_hint_here = false; - did_something_here = children[i]->simplify(const_fold_here, in_lvalue_here, stage, width_hint_here, sign_hint_here, in_param_here); + did_something_here = children[i]->simplify(const_fold_here, stage, width_hint_here, sign_hint_here); if (did_something_here) did_something = true; } @@ -1800,7 +1792,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi } } for (auto &attr : attributes) { - while (attr.second->simplify(true, false, stage, -1, false, true)) + while (attr.second->simplify(true, stage, -1, false)) did_something = true; } if (type == AST_CASE && stage == 2) { @@ -1878,7 +1870,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi log_assert(children.size() == 1); auto type_node = children[0]; log_assert(type_node->type == AST_WIRE || type_node->type == AST_MEMORY || type_node->type == AST_STRUCT || type_node->type == AST_UNION); - while (type_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) { + while (type_node->simplify(const_fold, stage, width_hint, sign_hint)) { did_something = true; } log_assert(!type_node->is_custom_type); @@ -1900,7 +1892,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi AstNode *template_node = resolved_type_node->children[0]; // Ensure typedef itself is fully simplified - while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, false)) {}; + while (template_node->simplify(const_fold, stage, width_hint, sign_hint)) {}; if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) { // replace instance with wire representing the packed structure @@ -1966,7 +1958,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi AstNode *template_node = resolved_type_node->children[0]; // Ensure typedef itself is fully simplified - while (template_node->simplify(const_fold, false, stage, width_hint, sign_hint, false)) {}; + while (template_node->simplify(const_fold, stage, width_hint, sign_hint)) {}; if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) { // replace with wire representing the packed structure @@ -2009,7 +2001,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi input_error("Index in generate block prefix syntax is not constant!\n"); } if (children[1]->type == AST_PREFIX) - children[1]->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param); + children[1]->simplify(const_fold, stage, width_hint, sign_hint); log_assert(children[1]->type == AST_IDENTIFIER); newNode = children[1]->clone(); const char *second_part = children[1]->str.c_str(); @@ -2304,7 +2296,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi if (current_block) wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); current_ast_mod->children.push_back(wire); - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } AstNode *data = clone(); delete data->children[1]; @@ -2346,7 +2338,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi AstNode *body = children[1]; // eval count expression - while (count->simplify(true, false, stage, 32, true, false)) { } + while (count->simplify(true, stage, 32, true)) { } if (count->type != AST_CONSTANT) input_error("Repeat loops outside must have constant repeat counts!\n"); @@ -2402,7 +2394,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi int expr_width_hint = -1; bool expr_sign_hint = true; varbuf->detectSignWidth(expr_width_hint, expr_sign_hint); - while (varbuf->simplify(true, false, stage, 32, true, false)) { } + while (varbuf->simplify(true, stage, 32, true)) { } } if (varbuf->type != AST_CONSTANT) @@ -2443,7 +2435,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi int expr_width_hint = -1; bool expr_sign_hint = true; buf->detectSignWidth(expr_width_hint, expr_sign_hint); - while (buf->simplify(true, false, stage, expr_width_hint, expr_sign_hint, false)) { } + while (buf->simplify(true, stage, expr_width_hint, expr_sign_hint)) { } } if (buf->type != AST_CONSTANT) @@ -2478,7 +2470,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi if (type == AST_GENFOR) { for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(const_fold, false, stage, -1, false, false); + buf->children[i]->simplify(const_fold, stage, -1, false); current_ast_mod->children.push_back(buf->children[i]); } } else { @@ -2495,7 +2487,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi int expr_width_hint = -1; bool expr_sign_hint = true; buf->detectSignWidth(expr_width_hint, expr_sign_hint); - while (buf->simplify(true, false, stage, expr_width_hint, expr_sign_hint, true)) { } + while (buf->simplify(true, stage, expr_width_hint, expr_sign_hint)) { } } if (buf->type != AST_CONSTANT) @@ -2547,7 +2539,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi std::vector new_children; for (size_t i = 0; i < children.size(); i++) if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) { - children[i]->simplify(false, false, stage, -1, false, false); + children[i]->simplify(false, stage, -1, false); current_ast_mod->children.push_back(children[i]); current_scope[children[i]->str] = children[i]; } else @@ -2566,7 +2558,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi } for (size_t i = 0; i < children.size(); i++) { - children[i]->simplify(const_fold, false, stage, -1, false, false); + children[i]->simplify(const_fold, stage, -1, false); current_ast_mod->children.push_back(children[i]); } @@ -2578,7 +2570,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi if (type == AST_GENIF && children.size() != 0) { AstNode *buf = children[0]->clone(); - while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (buf->simplify(true, stage, width_hint, sign_hint)) { } if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); @@ -2602,7 +2594,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi } for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(const_fold, false, stage, -1, false, false); + buf->children[i]->simplify(const_fold, stage, -1, false); current_ast_mod->children.push_back(buf->children[i]); } @@ -2618,7 +2610,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi if (type == AST_GENCASE && children.size() != 0) { AstNode *buf = children[0]->clone(); - while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (buf->simplify(true, stage, width_hint, sign_hint)) { } if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); @@ -2653,7 +2645,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi buf = child->clone(); buf->set_in_param_flag(true); - while (buf->simplify(true, false, stage, width_hint, sign_hint, true)) { } + while (buf->simplify(true, stage, width_hint, sign_hint)) { } if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); @@ -2681,7 +2673,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi } for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(const_fold, false, stage, -1, false, false); + buf->children[i]->simplify(const_fold, stage, -1, false); current_ast_mod->children.push_back(buf->children[i]); } @@ -2866,7 +2858,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi if (children[0]->id2ast->attributes.count(ID::nowrshmsk)) { AstNode *node = children[0]->id2ast->attributes.at(ID::nowrshmsk); - while (node->simplify(true, false, stage, -1, false, true)) { } + while (node->simplify(true, stage, -1, false)) { } if (node->type != AST_CONSTANT) input_error("Non-constant value for `nowrshmsk' attribute on `%s'!\n", children[0]->id2ast->str.c_str()); if (node->asAttrConst().as_bool()) @@ -2904,14 +2896,14 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); wire_mask->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); wire_mask->is_logic = true; - while (wire_mask->simplify(true, false, 1, -1, false, false)) { } + while (wire_mask->simplify(true, 1, -1, false)) { } current_ast_mod->children.push_back(wire_mask); AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true))); wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); wire_data->is_logic = true; - while (wire_data->simplify(true, false, 1, -1, false, false)) { } + while (wire_data->simplify(true, 1, -1, false)) { } current_ast_mod->children.push_back(wire_data); int shamt_width_hint = -1; @@ -2923,7 +2915,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue_, int stage, int width_hi wire_sel->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); wire_sel->is_logic = true; wire_sel->is_signed = shamt_sign_hint; - while (wire_sel->simplify(true, false, 1, -1, false, false)) { } + while (wire_sel->simplify(true, 1, -1, false)) { } current_ast_mod->children.push_back(wire_sel); did_something = true; @@ -3008,7 +3000,7 @@ skip_dynamic_range_lvalue_expansion:; wire_check->was_checked = true; current_ast_mod->children.push_back(wire_check); current_scope[wire_check->str] = wire_check; - while (wire_check->simplify(true, false, 1, -1, false, false)) { } + while (wire_check->simplify(true, 1, -1, false)) { } AstNode *wire_en = new AstNode(AST_WIRE); wire_en->str = id_en; @@ -3020,7 +3012,7 @@ skip_dynamic_range_lvalue_expansion:; current_ast_mod->children.back()->children[0]->children[0]->children[0]->was_checked = true; } current_scope[wire_en->str] = wire_en; - while (wire_en->simplify(true, false, 1, -1, false, false)) { } + while (wire_en->simplify(true, 1, -1, false)) { } AstNode *check_defval; if (type == AST_LIVE || type == AST_FAIR) { @@ -3116,7 +3108,7 @@ skip_dynamic_range_lvalue_expansion:; current_ast_mod->children.push_back(wire_tmp); current_scope[wire_tmp->str] = wire_tmp; wire_tmp->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); - while (wire_tmp->simplify(true, false, 1, -1, false, false)) { } + while (wire_tmp->simplify(true, 1, -1, false)) { } wire_tmp->is_logic = true; AstNode *wire_tmp_id = new AstNode(AST_IDENTIFIER); @@ -3186,7 +3178,7 @@ skip_dynamic_range_lvalue_expansion:; wire_addr->was_checked = true; current_ast_mod->children.push_back(wire_addr); current_scope[wire_addr->str] = wire_addr; - while (wire_addr->simplify(true, false, 1, -1, false, false)) { } + while (wire_addr->simplify(true, 1, -1, false)) { } AstNode *assign_addr = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false)); assign_addr->children[0]->str = id_addr; @@ -3212,7 +3204,7 @@ skip_dynamic_range_lvalue_expansion:; wire_data->is_signed = mem_signed; current_ast_mod->children.push_back(wire_data); current_scope[wire_data->str] = wire_data; - while (wire_data->simplify(true, false, 1, -1, false, false)) { } + while (wire_data->simplify(true, 1, -1, false)) { } AstNode *assign_data = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false)); assign_data->children[0]->str = id_data; @@ -3228,7 +3220,7 @@ skip_dynamic_range_lvalue_expansion:; wire_en->was_checked = true; current_ast_mod->children.push_back(wire_en); current_scope[wire_en->str] = wire_en; - while (wire_en->simplify(true, false, 1, -1, false, false)) { } + while (wire_en->simplify(true, 1, -1, false)) { } AstNode *assign_en_first = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width)); assign_en_first->children[0]->str = id_en; @@ -3356,7 +3348,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *wire = new AstNode(AST_WIRE); wire->str = stringf("$initstate$%d_wire", myidx); current_ast_mod->children.push_back(wire); - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } AstNode *cell = new AstNode(AST_CELL, new AstNode(AST_CELLTYPE), new AstNode(AST_ARGUMENT, new AstNode(AST_IDENTIFIER))); cell->str = stringf("$initstate$%d", myidx); @@ -3365,7 +3357,7 @@ skip_dynamic_range_lvalue_expansion:; cell->children[1]->children[0]->str = wire->str; cell->children[1]->children[0]->id2ast = wire; current_ast_mod->children.push_back(cell); - while (cell->simplify(true, false, 1, -1, false, false)) { } + while (cell->simplify(true, 1, -1, false)) { } newNode = new AstNode(AST_IDENTIFIER); newNode->str = wire->str; @@ -3391,7 +3383,7 @@ skip_dynamic_range_lvalue_expansion:; if (GetSize(children) == 2) { AstNode *buf = children[1]->clone(); - while (buf->simplify(true, false, stage, -1, false, false)) { } + while (buf->simplify(true, stage, -1, false)) { } if (buf->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); @@ -3426,7 +3418,7 @@ skip_dynamic_range_lvalue_expansion:; current_ast_mod->children.push_back(reg); - while (reg->simplify(true, false, 1, -1, false, false)) { } + while (reg->simplify(true, 1, -1, false)) { } AstNode *regid = new AstNode(AST_IDENTIFIER); regid->str = reg->str; @@ -3502,7 +3494,7 @@ skip_dynamic_range_lvalue_expansion:; RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *buf = children[0]->clone(); - while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (buf->simplify(true, stage, width_hint, sign_hint)) { } if (buf->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); @@ -3534,7 +3526,7 @@ skip_dynamic_range_lvalue_expansion:; if (children.size() == 2) { AstNode *buf = children[1]->clone(); // Evaluate constant expression - while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (buf->simplify(true, stage, width_hint, sign_hint)) { } dim = buf->asInt(false); delete buf; } @@ -3692,7 +3684,7 @@ skip_dynamic_range_lvalue_expansion:; } if (children.size() >= 1) { - while (children[0]->simplify(true, false, stage, width_hint, sign_hint, in_param)) { } + while (children[0]->simplify(true, stage, width_hint, sign_hint)) { } if (!children[0]->isConst()) input_error("Failed to evaluate system function `%s' with non-constant argument.\n", RTLIL::unescape_id(str).c_str()); @@ -3703,7 +3695,7 @@ skip_dynamic_range_lvalue_expansion:; } if (children.size() >= 2) { - while (children[1]->simplify(true, false, stage, width_hint, sign_hint, in_param)) { } + while (children[1]->simplify(true, stage, width_hint, sign_hint)) { } if (!children[1]->isConst()) input_error("Failed to evaluate system function `%s' with non-constant argument.\n", RTLIL::unescape_id(str).c_str()); @@ -3760,7 +3752,7 @@ skip_dynamic_range_lvalue_expansion:; // Determine which bits to count for (size_t i = 1; i < children.size(); i++) { AstNode *node = children[i]; - while (node->simplify(true, false, stage, -1, false, in_param)) { } + while (node->simplify(true, stage, -1, false)) { } if (node->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str.c_str()); if (node->bits.size() != 1) @@ -3855,8 +3847,7 @@ skip_dynamic_range_lvalue_expansion:; argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str)); args.push_back(children.at(i-2)->clone()); - args.back()->set_in_param_flag(true); - while (args.back()->simplify(true, false, stage, -1, false, true)) { } + while (args.back()->simplify(true, stage, -1, false)) { } if (args.back()->type != AST_CONSTANT && args.back()->type != AST_REALVALUE) input_error("Failed to evaluate DPI function with non-constant argument.\n"); @@ -3893,12 +3884,12 @@ skip_dynamic_range_lvalue_expansion:; RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *node_filename = children[0]->clone(); - while (node_filename->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (node_filename->simplify(true, stage, width_hint, sign_hint)) { } if (node_filename->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); AstNode *node_memory = children[1]->clone(); - while (node_memory->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (node_memory->simplify(true, stage, width_hint, sign_hint)) { } if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY) input_error("Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str()); @@ -3906,7 +3897,7 @@ skip_dynamic_range_lvalue_expansion:; if (GetSize(children) > 2) { AstNode *node_addr = children[2]->clone(); - while (node_addr->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (node_addr->simplify(true, stage, width_hint, sign_hint)) { } if (node_addr->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str()); start_addr = int(node_addr->asInt(false)); @@ -3914,7 +3905,7 @@ skip_dynamic_range_lvalue_expansion:; if (GetSize(children) > 3) { AstNode *node_addr = children[3]->clone(); - while (node_addr->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (node_addr->simplify(true, stage, width_hint, sign_hint)) { } if (node_addr->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str()); finish_addr = int(node_addr->asInt(false)); @@ -3966,7 +3957,7 @@ skip_dynamic_range_lvalue_expansion:; bool require_const_eval = decl->has_const_only_constructs(); bool all_args_const = true; for (auto child : children) { - while (child->simplify(true, in_lvalue, 1, -1, false, in_param)) { } + while (child->simplify(true, 1, -1, false)) { } if (child->type != AST_CONSTANT && child->type != AST_REALVALUE) all_args_const = false; } @@ -4011,7 +4002,7 @@ skip_dynamic_range_lvalue_expansion:; current_scope[wire->str] = wire; current_ast_mod->children.push_back(wire); - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } AstNode *lvalue = new AstNode(AST_IDENTIFIER); lvalue->str = wire->str; @@ -4057,7 +4048,7 @@ skip_dynamic_range_lvalue_expansion:; wire->is_input = false; wire->is_output = false; current_ast_mod->children.push_back(wire); - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } AstNode *wire_id = new AstNode(AST_IDENTIFIER); wire_id->str = wire->str; @@ -4100,7 +4091,7 @@ skip_dynamic_range_lvalue_expansion:; for (auto c : child->children) wire->children.push_back(c->clone()); } else if (!child->children.empty()) { - while (child->simplify(true, false, stage, -1, false, false)) { } + while (child->simplify(true, stage, -1, false)) { } if (GetSize(child->children) == GetSize(wire->children) - contains_value) { for (int i = 0; i < GetSize(child->children); i++) if (*child->children.at(i) != *wire->children.at(i + contains_value)) @@ -4128,7 +4119,7 @@ skip_dynamic_range_lvalue_expansion:; current_ast_mod->children.push_back(wire); } - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } if ((child->is_input || child->is_output) && arg_count < children.size()) { @@ -4161,7 +4152,7 @@ skip_dynamic_range_lvalue_expansion:; } wire->fixup_hierarchy_flags(); // updates the sizing - while (wire->simplify(true, false, 1, -1, false, true)) { } + while (wire->simplify(true, 1, -1, false)) { } delete arg; continue; } @@ -5072,7 +5063,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, wire_addr->was_checked = true; wire_addr->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); mod->children.push_back(wire_addr); - while (wire_addr->simplify(true, false, 1, -1, false, false)) { } + while (wire_addr->simplify(true, 1, -1, false)) { } AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); wire_data->str = id_data; @@ -5081,7 +5072,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, wire_data->is_signed = mem_signed; wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); mod->children.push_back(wire_data); - while (wire_data->simplify(true, false, 1, -1, false, false)) { } + while (wire_data->simplify(true, 1, -1, false)) { } log_assert(block != NULL); size_t assign_idx = 0; @@ -5194,7 +5185,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, if (block) wire_addr->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); mod->children.push_back(wire_addr); - while (wire_addr->simplify(true, false, 1, -1, false, false)) { } + while (wire_addr->simplify(true, 1, -1, false)) { } AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); wire_data->str = id_data; @@ -5204,7 +5195,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, if (block) wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); mod->children.push_back(wire_data); - while (wire_data->simplify(true, false, 1, -1, false, false)) { } + while (wire_data->simplify(true, 1, -1, false)) { } AstNode *assign_addr = new AstNode(block ? AST_ASSIGN_EQ : AST_ASSIGN, new AstNode(AST_IDENTIFIER), children[0]->children[0]->clone()); assign_addr->children[0]->str = id_addr; @@ -5387,7 +5378,7 @@ bool AstNode::replace_variables(std::map &varia } if (!children.at(0)->replace_variables(variables, fcall, must_succeed)) return false; - while (simplify(true, false, 1, -1, false, true)) { } + while (simplify(true, 1, -1, false)) { } if (!children.at(0)->range_valid) { if (!must_succeed) return false; @@ -5443,7 +5434,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) if (stmt->type == AST_WIRE) { - while (stmt->simplify(true, false, 1, -1, false, true)) { } + while (stmt->simplify(true, 1, -1, false)) { } if (!stmt->range_valid) { if (!must_succeed) goto finished; @@ -5487,7 +5478,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) if (stmt->type == AST_LOCALPARAM) { - while (stmt->simplify(true, false, 1, -1, false, true)) { } + while (stmt->simplify(true, 1, -1, false)) { } current_scope[stmt->str] = stmt; @@ -5504,7 +5495,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) goto finished; if (!stmt->children.at(1)->replace_variables(variables, fcall, must_succeed)) goto finished; - while (stmt->simplify(true, false, 1, -1, false, true)) { } + while (stmt->simplify(true, 1, -1, false)) { } if (stmt->type != AST_ASSIGN_EQ) continue; @@ -5572,7 +5563,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) if (!cond->replace_variables(variables, fcall, must_succeed)) goto finished; cond->set_in_param_flag(true); - while (cond->simplify(true, false, 1, -1, false, true)) { } + while (cond->simplify(true, 1, -1, false)) { } if (cond->type != AST_CONSTANT) { if (!must_succeed) @@ -5598,7 +5589,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) if (!num->replace_variables(variables, fcall, must_succeed)) goto finished; num->set_in_param_flag(true); - while (num->simplify(true, false, 1, -1, false, true)) { } + while (num->simplify(true, 1, -1, false)) { } if (num->type != AST_CONSTANT) { if (!must_succeed) @@ -5622,7 +5613,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) if (!expr->replace_variables(variables, fcall, must_succeed)) goto finished; expr->set_in_param_flag(true); - while (expr->simplify(true, false, 1, -1, false, true)) { } + while (expr->simplify(true, 1, -1, false)) { } AstNode *sel_case = NULL; for (size_t i = 1; i < stmt->children.size(); i++) @@ -5643,7 +5634,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) cond = new AstNode(AST_EQ, expr->clone(), cond); cond->set_in_param_flag(true); - while (cond->simplify(true, false, 1, -1, false, true)) { } + while (cond->simplify(true, 1, -1, false)) { } if (cond->type != AST_CONSTANT) { if (!must_succeed) From c172fef01a23deee96a3b1bf45bdfd7b993376bf Mon Sep 17 00:00:00 2001 From: Wanda Date: Tue, 26 Sep 2023 18:56:54 +0200 Subject: [PATCH 041/240] hashlib: Use a better hash for pool. --- kernel/hashlib.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index b3f99bf730f..be759fdf0a4 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -988,7 +988,7 @@ class pool return !operator==(other); } - bool hash() const { + unsigned int hash() const { unsigned int hashval = mkhash_init; for (auto &it : entries) hashval ^= ops.hash(it.udata); From 076c5ceb714bc8f20136a83cc9818b96e6a542b4 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 27 Sep 2023 00:15:07 +0000 Subject: [PATCH 042/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 77f7b80fadf..1fb47fa07d8 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.33+65 +YOSYS_VER := 0.33+67 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From f193ebdded593c837e9f3447fddf803723f8e5f9 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 27 Sep 2023 16:57:18 +0200 Subject: [PATCH 043/240] Verific: add default parameters to modules --- frontends/verific/verific.cc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index cd844dceeee..310e3918015 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1275,9 +1275,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma log("Importing module %s.\n", RTLIL::id2cstr(module->name)); } import_attributes(module->attributes, nl, nl); + const char *param_name ; + const char *param_value ; + MapIter mi; + FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) { + module->avail_parameters(RTLIL::escape_id(param_name)); + module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(param_value); + } SetIter si; - MapIter mi, mi2; + MapIter mi2; Port *port; PortBus *portbus; Net *net; From ac8b31e000cdcc68c2017070679821d4333f801e Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 28 Sep 2023 00:15:01 +0000 Subject: [PATCH 044/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 1fb47fa07d8..24184e8296e 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.33+67 +YOSYS_VER := 0.33+72 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 01a015747e274480fc5ae8d0fab18d89d04ea8b0 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Wed, 27 Sep 2023 17:16:13 -0700 Subject: [PATCH 045/240] Speed up RTLIL::Const::decode_string by 1.7x. --- kernel/rtlil.cc | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1b57af60acb..3663ca864e0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -313,18 +313,33 @@ RTLIL::Const RTLIL::Const::from_string(const std::string &str) std::string RTLIL::Const::decode_string() const { - std::string string; - string.reserve(GetSize(bits)/8); - for (int i = 0; i < GetSize(bits); i += 8) { + const int n = GetSize(bits); + const int n_over_8 = n / 8; + std::string s; + s.reserve(n_over_8); + int i = n_over_8 * 8; + if (i < n) { char ch = 0; - for (int j = 0; j < 8 && i + j < int (bits.size()); j++) - if (bits[i + j] == RTLIL::State::S1) + for (int j = 0; j < (n - i); j++) { + if (bits[j + i] == RTLIL::State::S1) { ch |= 1 << j; + } + } + if (ch != 0) + s.append({ch}); + } + i -= 8; + for (; i >= 0; i -= 8) { + char ch = 0; + for (int j = 0; j < 8; j++) { + if (bits[j + i] == RTLIL::State::S1) { + ch |= 1 << j; + } + } if (ch != 0) - string.append({ch}); + s.append({ch}); } - std::reverse(string.begin(), string.end()); - return string; + return s; } bool RTLIL::Const::is_fully_zero() const @@ -4044,7 +4059,7 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec other->bits_[j] = with.bits_[it->second]; } } - + other->check(); } From 6b70b3dbefea7972c44e312c356bf7377a7d5f7b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 28 Sep 2023 11:50:57 +0200 Subject: [PATCH 046/240] booth: Fix assertion Fix assertion to what it should be per Andy's comments. --- passes/techmap/booth.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index be38c8fc39f..000dcff14ec 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -655,8 +655,7 @@ struct BoothPassWorker { cpa_id++; log_assert(c_vec.size() == s_vec.size()); - // TODO: doesn't pass - //log_assert(result.size() == s_vec.size() + 2); + log_assert(result.size() == s_vec.size()); SigBit carry; for (int n = 0; n < s_vec.size(); n++) { From b0045300fd7ee6a123d3a3a373448e4780c3bcfe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 28 Sep 2023 11:55:51 +0200 Subject: [PATCH 047/240] booth: Cut down the test Cut the test down from taking ~25 s to ~3 s. --- tests/techmap/booth.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/techmap/booth.ys b/tests/techmap/booth.ys index f1dce1f3b27..ab7efc7b7fd 100644 --- a/tests/techmap/booth.ys +++ b/tests/techmap/booth.ys @@ -1 +1 @@ -test_cell -s 1694091355 -n 1000 -script booth_map_script.ys_ $mul +test_cell -s 1694091355 -n 100 -script booth_map_script.ys_ $mul From 7eaa4bcb4605d6c1d30d4daf96a94cea3b423df3 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Thu, 28 Sep 2023 17:29:24 +0200 Subject: [PATCH 048/240] sim: Add -noinitstate option and handle non-cosim initstate This adds the -noinitstate option which is required to simulate counterexamples to induction with yw-cosim. Also add handling for $initstate cells for non-co-simulation. --- passes/sat/sim.cc | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 1e6645303b5..963c6481b16 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -111,6 +111,7 @@ struct SimShared int step = 0; std::vector triggered_assertions; bool serious_asserts = false; + bool initstate = true; }; void zinit(State &v) @@ -1356,6 +1357,8 @@ struct SimWorker : SimShared set_inports(clock, State::Sx); set_inports(clockn, State::Sx); + top->set_initstate_outputs(initstate ? State::S1 : State::S0); + update(false); register_output_step(0); @@ -1372,6 +1375,9 @@ struct SimWorker : SimShared update(true); register_output_step(10*cycle + 5); + if (cycle == 0) + top->set_initstate_outputs(State::S0); + if (debug) log("\n===== %d =====\n", 10*cycle + 10); else if (verbose) @@ -1953,7 +1959,7 @@ struct SimWorker : SimShared if (yw.steps.empty()) { log_warning("Yosys witness file `%s` contains no time steps\n", yw.filename.c_str()); } else { - top->set_initstate_outputs(State::S1); + top->set_initstate_outputs(initstate ? State::S1 : State::S0); set_yw_state(yw, hierarchy, 0); set_yw_clocks(yw, hierarchy, true); initialize_stable_past(); @@ -2546,6 +2552,9 @@ struct SimPass : public Pass { log(" -n \n"); log(" number of clock cycles to simulate (default: 20)\n"); log("\n"); + log(" -noinitstate\n"); + log(" do not activate $initstate cells during the first cycle\n"); + log("\n"); log(" -a\n"); log(" use all nets in VCD/FST operations, not just those with public names\n"); log("\n"); @@ -2646,6 +2655,10 @@ struct SimPass : public Pass { worker.cycles_set = true; continue; } + if (args[argidx] == "-noinitstate") { + worker.initstate = false; + continue; + } if (args[argidx] == "-rstlen" && argidx+1 < args.size()) { worker.rstlen = atoi(args[++argidx].c_str()); continue; From 5daa49bafbcb40816e9a56f249568127d275c59d Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Thu, 28 Sep 2023 17:32:19 +0200 Subject: [PATCH 049/240] dft_tag: Fix size extending $x[n]or and $reduce_{or,bool}/$logic_not --- passes/cmds/dft_tag.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc index 9fd356ef65d..2b2340dab53 100644 --- a/passes/cmds/dft_tag.cc +++ b/passes/cmds/dft_tag.cc @@ -405,7 +405,7 @@ struct DftTagWorker { auto &sig_y = cell->getPort(ID::Y); auto sig_a = cell->getPort(ID::A); auto sig_b = cell->getPort(ID::B); - if (cell->type.in(ID($and), ID($or))) { + if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) { sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool()); } @@ -669,12 +669,12 @@ struct DftTagWorker { auto &sig_y = cell->getPort(ID::Y); auto sig_a = cell->getPort(ID::A); - if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) - sig_a = autoNot(NEW_ID, sig_a); - auto group_sig_a = tag_group_signal(tag, sig_a); auto tag_sig_a = tag_signal(tag, sig_a); + if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) + sig_a = autoNot(NEW_ID, sig_a); + auto filled = autoOr(NEW_ID, sig_a, group_sig_a); auto prop = autoReduceAnd(NEW_ID, filled); From 12218a4c744cb3877e5d9e78d15b7c2d90667907 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Thu, 28 Sep 2023 19:39:09 -0700 Subject: [PATCH 050/240] Unflip i and j. --- kernel/rtlil.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3663ca864e0..9834a0d37af 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -321,7 +321,7 @@ std::string RTLIL::Const::decode_string() const if (i < n) { char ch = 0; for (int j = 0; j < (n - i); j++) { - if (bits[j + i] == RTLIL::State::S1) { + if (bits[i + j] == RTLIL::State::S1) { ch |= 1 << j; } } @@ -332,7 +332,7 @@ std::string RTLIL::Const::decode_string() const for (; i >= 0; i -= 8) { char ch = 0; for (int j = 0; j < 8; j++) { - if (bits[j + i] == RTLIL::State::S1) { + if (bits[i + j] == RTLIL::State::S1) { ch |= 1 << j; } } From cc843d414f7a68c0140c0bc038b937210650ba78 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Fri, 29 Sep 2023 12:28:50 +0200 Subject: [PATCH 051/240] simplify: Avoid calling fixup_hierarchy_flags on nullptr Compiling on GCC hid this bug as it optimized the nullptr call away as undefined behavior, but running the SBY tests with a clang build hits this error. --- frontends/ast/simplify.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index c4a30302712..c5f0467041d 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -3042,8 +3042,8 @@ skip_dynamic_range_lvalue_expansion:; assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_REDUCE_BOOL, children[0]->clone())); assign_check->children[0]->str = id_check; assign_check->children[0]->was_checked = true; + assign_check->fixup_hierarchy_flags(); } - assign_check->fixup_hierarchy_flags(); if (current_always == nullptr || current_always->type != AST_INITIAL) { assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(1, false, 1)); From b52f6cb1991b7117d23fa119bf808f9fc1849789 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 30 Sep 2023 00:14:39 +0000 Subject: [PATCH 052/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 24184e8296e..a96f3f54919 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.33+72 +YOSYS_VER := 0.33+79 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 98d2c9088acfc1da368e36f15bc5d40a61718079 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Fri, 29 Sep 2023 13:26:22 -0700 Subject: [PATCH 053/240] Ignore emacs auto-save files. --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 49b886e7e43..9b799c1f38d 100644 --- a/.gitignore +++ b/.gitignore @@ -4,6 +4,7 @@ *.gch *.gcda *.gcno +*~ __pycache__ /.cproject /.project From abd9c519634f5279cb7f85a6884d47d23a8583e4 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Fri, 29 Sep 2023 10:53:37 -0700 Subject: [PATCH 054/240] Speed up simplemap_map by 11.6x by directly inserting the cell source attribute in the new object's 'attributes' map instead of calling set_attr_pool to create a new pool and then copying that. Based on a suggestion by Martin Poviser in a comment on https://github.com/YosysHQ/yosys/pull/3959 --- passes/techmap/simplemap.cc | 228 ++++++++++++++++-------------- passes/techmap/techmap.cc | 274 +++++++++++++++++------------------- 2 files changed, 252 insertions(+), 250 deletions(-) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 11692b715ea..14c07922b14 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -18,10 +18,10 @@ */ #include "simplemap.h" -#include "kernel/sigtools.h" #include "kernel/ff.h" -#include +#include "kernel/sigtools.h" #include +#include #include USING_YOSYS_NAMESPACE @@ -36,7 +36,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::Y, sig_y[i]); } @@ -64,16 +64,21 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) } IdString gate_type; - if (cell->type == ID($and)) gate_type = ID($_AND_); - if (cell->type == ID($or)) gate_type = ID($_OR_); - if (cell->type == ID($xor)) gate_type = ID($_XOR_); - if (cell->type == ID($xnor)) gate_type = ID($_XNOR_); - if (cell->type == ID($bweqx)) gate_type = ID($_XNOR_); + if (cell->type == ID($and)) + gate_type = ID($_AND_); + if (cell->type == ID($or)) + gate_type = ID($_OR_); + if (cell->type == ID($xor)) + gate_type = ID($_XOR_); + if (cell->type == ID($xnor)) + gate_type = ID($_XNOR_); + if (cell->type == ID($bweqx)) + gate_type = ID($_XNOR_); log_assert(!gate_type.empty()); for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::Y, sig_y[i]); @@ -89,45 +94,53 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) return; if (sig_a.size() == 0) { - if (cell->type == ID($reduce_and)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); - if (cell->type == ID($reduce_or)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); - if (cell->type == ID($reduce_xor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); - if (cell->type == ID($reduce_xnor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); - if (cell->type == ID($reduce_bool)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == ID($reduce_and)) + module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); + if (cell->type == ID($reduce_or)) + module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == ID($reduce_xor)) + module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == ID($reduce_xnor)) + module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); + if (cell->type == ID($reduce_bool)) + module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); return; } if (sig_y.size() > 1) { - module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); + module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size() - 1), RTLIL::SigSpec(0, sig_y.size() - 1))); sig_y = sig_y.extract(0, 1); } IdString gate_type; - if (cell->type == ID($reduce_and)) gate_type = ID($_AND_); - if (cell->type == ID($reduce_or)) gate_type = ID($_OR_); - if (cell->type == ID($reduce_xor)) gate_type = ID($_XOR_); - if (cell->type == ID($reduce_xnor)) gate_type = ID($_XOR_); - if (cell->type == ID($reduce_bool)) gate_type = ID($_OR_); + if (cell->type == ID($reduce_and)) + gate_type = ID($_AND_); + if (cell->type == ID($reduce_or)) + gate_type = ID($_OR_); + if (cell->type == ID($reduce_xor)) + gate_type = ID($_XOR_); + if (cell->type == ID($reduce_xnor)) + gate_type = ID($_XOR_); + if (cell->type == ID($reduce_bool)) + gate_type = ID($_OR_); log_assert(!gate_type.empty()); RTLIL::Cell *last_output_cell = NULL; - while (sig_a.size() > 1) - { + while (sig_a.size() > 1) { RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2); - for (int i = 0; i < sig_a.size(); i += 2) - { - if (i+1 == sig_a.size()) { + for (int i = 0; i < sig_a.size(); i += 2) { + if (i + 1 == sig_a.size()) { sig_t.append(sig_a[i]); continue; } RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); - gate->setPort(ID::B, sig_a[i+1]); - gate->setPort(ID::Y, sig_t[i/2]); + gate->setPort(ID::B, sig_a[i + 1]); + gate->setPort(ID::Y, sig_t[i / 2]); last_output_cell = gate; } @@ -137,7 +150,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == ID($reduce_xnor)) { RTLIL::SigSpec sig_t = module->addWire(NEW_ID); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_t); last_output_cell = gate; @@ -153,22 +166,20 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell *cell) { - while (sig.size() > 1) - { + while (sig.size() > 1) { RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2); - for (int i = 0; i < sig.size(); i += 2) - { - if (i+1 == sig.size()) { + for (int i = 0; i < sig.size(); i += 2) { + if (i + 1 == sig.size()) { sig_t.append(sig[i]); continue; } RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig[i]); - gate->setPort(ID::B, sig[i+1]); - gate->setPort(ID::Y, sig_t[i/2]); + gate->setPort(ID::B, sig[i + 1]); + gate->setPort(ID::Y, sig_t[i / 2]); } sig = sig_t; @@ -189,12 +200,12 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) return; if (sig_y.size() > 1) { - module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); + module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size() - 1), RTLIL::SigSpec(0, sig_y.size() - 1))); sig_y = sig_y.extract(0, 1); } RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_y); } @@ -213,17 +224,19 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) return; if (sig_y.size() > 1) { - module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); + module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size() - 1), RTLIL::SigSpec(0, sig_y.size() - 1))); sig_y = sig_y.extract(0, 1); } IdString gate_type; - if (cell->type == ID($logic_and)) gate_type = ID($_AND_); - if (cell->type == ID($logic_or)) gate_type = ID($_OR_); + if (cell->type == ID($logic_and)) + gate_type = ID($_AND_); + if (cell->type == ID($logic_or)) + gate_type = ID($_OR_); log_assert(!gate_type.empty()); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a); gate->setPort(ID::B, sig_b); gate->setPort(ID::Y, sig_y); @@ -239,19 +252,22 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); - xor_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + xor_cell->attributes[ID::src] = cell->attributes[ID::src]; + // xor_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); simplemap_bitop(module, xor_cell); module->remove(xor_cell); RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID); RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out); - reduce_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + reduce_cell->attributes[ID::src] = cell->attributes[ID::src]; + // reduce_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); simplemap_reduce(module, reduce_cell); module->remove(reduce_cell); if (!is_ne) { RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y); - not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + not_cell->attributes[ID::src] = cell->attributes[ID::src]; + // not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); simplemap_lognot(module, not_cell); module->remove(not_cell); } @@ -265,7 +281,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::S, cell->getPort(ID::S)); @@ -282,7 +298,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::S, sig_s[i]); @@ -298,7 +314,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::E, sig_e); gate->setPort(ID::Y, sig_y[i]); @@ -312,15 +328,15 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell) int width = GetSize(cell->getPort(ID::Y)); for (int idx = 0; idx < GetSize(sel); idx++) { - SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2); + SigSpec new_data = module->addWire(NEW_ID, GetSize(data) / 2); for (int i = 0; i < GetSize(new_data); i += width) { for (int k = 0; k < width; k++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); - gate->setPort(ID::A, data[i*2+k]); - gate->setPort(ID::B, data[i*2+width+k]); + gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->setPort(ID::A, data[i * 2 + k]); + gate->setPort(ID::B, data[i * 2 + width + k]); gate->setPort(ID::S, sel[idx]); - gate->setPort(ID::Y, new_data[i+k]); + gate->setPort(ID::Y, new_data[i + k]); } } data = new_data; @@ -336,14 +352,14 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell) lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int()); for (int idx = 0; GetSize(lut_data) > 1; idx++) { - SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2); + SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data) / 2); for (int i = 0; i < GetSize(lut_data); i += 2) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, lut_data[i]); - gate->setPort(ID::B, lut_data[i+1]); + gate->setPort(ID::B, lut_data[i + 1]); gate->setPort(ID::S, lut_ctrl[idx]); - gate->setPort(ID::Y, new_lut_data[i/2]); + gate->setPort(ID::Y, new_lut_data[i / 2]); } lut_data = new_lut_data; } @@ -365,11 +381,11 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < depth; i++) { SigSpec in, pat; for (int j = 0; j < width; j++) { - if (table[2*i*width + 2*j + 0] == State::S1) { + if (table[2 * i * width + 2 * j + 0] == State::S1) { in.append(ctrl[j]); pat.append(State::S0); } - if (table[2*i*width + 2*j + 1] == State::S1) { + if (table[2 * i * width + 2 * j + 1] == State::S1) { in.append(ctrl[j]); pat.append(State::S1); } @@ -407,56 +423,56 @@ void simplemap_ff(RTLIL::Module *, RTLIL::Cell *cell) } } -void simplemap_get_mappers(dict &mappers) +void simplemap_get_mappers(dict &mappers) { - mappers[ID($not)] = simplemap_not; - mappers[ID($pos)] = simplemap_pos; - mappers[ID($and)] = simplemap_bitop; - mappers[ID($or)] = simplemap_bitop; - mappers[ID($xor)] = simplemap_bitop; - mappers[ID($xnor)] = simplemap_bitop; - mappers[ID($bweqx)] = simplemap_bitop; - mappers[ID($reduce_and)] = simplemap_reduce; - mappers[ID($reduce_or)] = simplemap_reduce; - mappers[ID($reduce_xor)] = simplemap_reduce; + mappers[ID($not)] = simplemap_not; + mappers[ID($pos)] = simplemap_pos; + mappers[ID($and)] = simplemap_bitop; + mappers[ID($or)] = simplemap_bitop; + mappers[ID($xor)] = simplemap_bitop; + mappers[ID($xnor)] = simplemap_bitop; + mappers[ID($bweqx)] = simplemap_bitop; + mappers[ID($reduce_and)] = simplemap_reduce; + mappers[ID($reduce_or)] = simplemap_reduce; + mappers[ID($reduce_xor)] = simplemap_reduce; mappers[ID($reduce_xnor)] = simplemap_reduce; mappers[ID($reduce_bool)] = simplemap_reduce; - mappers[ID($logic_not)] = simplemap_lognot; - mappers[ID($logic_and)] = simplemap_logbin; - mappers[ID($logic_or)] = simplemap_logbin; - mappers[ID($eq)] = simplemap_eqne; - mappers[ID($eqx)] = simplemap_eqne; - mappers[ID($ne)] = simplemap_eqne; - mappers[ID($nex)] = simplemap_eqne; - mappers[ID($mux)] = simplemap_mux; - mappers[ID($bwmux)] = simplemap_bwmux; - mappers[ID($tribuf)] = simplemap_tribuf; - mappers[ID($bmux)] = simplemap_bmux; - mappers[ID($lut)] = simplemap_lut; - mappers[ID($sop)] = simplemap_sop; - mappers[ID($slice)] = simplemap_slice; - mappers[ID($concat)] = simplemap_concat; - mappers[ID($sr)] = simplemap_ff; - mappers[ID($ff)] = simplemap_ff; - mappers[ID($dff)] = simplemap_ff; - mappers[ID($dffe)] = simplemap_ff; - mappers[ID($dffsr)] = simplemap_ff; - mappers[ID($dffsre)] = simplemap_ff; - mappers[ID($adff)] = simplemap_ff; - mappers[ID($sdff)] = simplemap_ff; - mappers[ID($adffe)] = simplemap_ff; - mappers[ID($sdffe)] = simplemap_ff; - mappers[ID($sdffce)] = simplemap_ff; - mappers[ID($aldff)] = simplemap_ff; - mappers[ID($aldffe)] = simplemap_ff; - mappers[ID($dlatch)] = simplemap_ff; - mappers[ID($adlatch)] = simplemap_ff; - mappers[ID($dlatchsr)] = simplemap_ff; + mappers[ID($logic_not)] = simplemap_lognot; + mappers[ID($logic_and)] = simplemap_logbin; + mappers[ID($logic_or)] = simplemap_logbin; + mappers[ID($eq)] = simplemap_eqne; + mappers[ID($eqx)] = simplemap_eqne; + mappers[ID($ne)] = simplemap_eqne; + mappers[ID($nex)] = simplemap_eqne; + mappers[ID($mux)] = simplemap_mux; + mappers[ID($bwmux)] = simplemap_bwmux; + mappers[ID($tribuf)] = simplemap_tribuf; + mappers[ID($bmux)] = simplemap_bmux; + mappers[ID($lut)] = simplemap_lut; + mappers[ID($sop)] = simplemap_sop; + mappers[ID($slice)] = simplemap_slice; + mappers[ID($concat)] = simplemap_concat; + mappers[ID($sr)] = simplemap_ff; + mappers[ID($ff)] = simplemap_ff; + mappers[ID($dff)] = simplemap_ff; + mappers[ID($dffe)] = simplemap_ff; + mappers[ID($dffsr)] = simplemap_ff; + mappers[ID($dffsre)] = simplemap_ff; + mappers[ID($adff)] = simplemap_ff; + mappers[ID($sdff)] = simplemap_ff; + mappers[ID($adffe)] = simplemap_ff; + mappers[ID($sdffe)] = simplemap_ff; + mappers[ID($sdffce)] = simplemap_ff; + mappers[ID($aldff)] = simplemap_ff; + mappers[ID($aldffe)] = simplemap_ff; + mappers[ID($dlatch)] = simplemap_ff; + mappers[ID($adlatch)] = simplemap_ff; + mappers[ID($dlatchsr)] = simplemap_ff; } void simplemap(RTLIL::Module *module, RTLIL::Cell *cell) { - static dict mappers; + static dict mappers; static bool initialized_mappers = false; if (!initialized_mappers) { @@ -471,7 +487,7 @@ YOSYS_NAMESPACE_END PRIVATE_NAMESPACE_BEGIN struct SimplemapPass : public Pass { - SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { } + SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") {} void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -493,13 +509,13 @@ struct SimplemapPass : public Pass { log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n"); extra_args(args, 1, design); - dict mappers; + dict mappers; simplemap_get_mappers(mappers); for (auto mod : design->modules()) { if (!design->selected(mod) || mod->get_blackbox_attribute()) continue; - std::vector cells = mod->cells(); + std::vector cells = mod->cells(); for (auto cell : cells) { if (mappers.count(cell->type) == 0) continue; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 144f596c88c..52a24dcf3ba 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -17,14 +17,14 @@ * */ -#include "kernel/yosys.h" -#include "kernel/utils.h" -#include "kernel/sigtools.h" #include "kernel/ffinit.h" +#include "kernel/sigtools.h" +#include "kernel/utils.h" +#include "kernel/yosys.h" #include "libs/sha1/sha1.h" -#include #include +#include #include #include "simplemap.h" @@ -42,7 +42,7 @@ PRIVATE_NAMESPACE_BEGIN void apply_prefix(IdString prefix, IdString &id) { if (id[0] == '\\') - id = stringf("%s.%s", prefix.c_str(), id.c_str()+1); + id = stringf("%s.%s", prefix.c_str(), id.c_str() + 1); else id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str()); } @@ -60,13 +60,12 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) sig = chunks; } -struct TechmapWorker -{ - dict simplemap_mappers; - dict>, RTLIL::Module*> techmap_cache; - dict techmap_do_cache; - pool module_queue; - dict sigmaps; +struct TechmapWorker { + dict simplemap_mappers; + dict>, RTLIL::Module *> techmap_cache; + dict techmap_do_cache; + pool module_queue; + dict sigmaps; pool log_msg_cache; @@ -98,9 +97,9 @@ struct TechmapWorker } else if (connbits_map.count(bit)) { if (verbose) log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first), - connbits_map.at(bit).second, log_id(connbits_map.at(bit).first)); - constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, - log_id(connbits_map.at(bit).first), connbits_map.at(bit).second); + connbits_map.at(bit).second, log_id(connbits_map.at(bit).first)); + constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, log_id(connbits_map.at(bit).first), + connbits_map.at(bit).second); } else { connbits_map.emplace(bit, std::make_pair(conn.first, i)); constmap_info += stringf("|%s %d", log_id(conn.first), i); @@ -134,8 +133,8 @@ struct TechmapWorker if (!result.empty()) { SigMap sigmap(module); for (auto &it1 : result) - for (auto &it2 : it1.second) - sigmap.apply(it2.value); + for (auto &it2 : it1.second) + sigmap.apply(it2.value); } return result; @@ -146,7 +145,7 @@ struct TechmapWorker if (tpl->processes.size() != 0) { log("Technology map yielded processes:"); for (auto &it : tpl->processes) - log(" %s",log_id(it.first)); + log(" %s", log_id(it.first)); log("\n"); if (autoproc_mode) { Pass::call_on_module(tpl->design, tpl, "proc"); @@ -156,7 +155,6 @@ struct TechmapWorker } std::string orig_cell_name; - pool extra_src_attrs = cell->get_strpool_attribute(ID::src); orig_cell_name = cell->name.str(); for (auto tpl_cell : tpl->cells()) @@ -166,32 +164,28 @@ struct TechmapWorker } dict memory_renames; - for (auto &it : tpl->memories) { IdString m_name = it.first; apply_prefix(cell->name, m_name); RTLIL::Memory *m = module->addMemory(m_name, it.second); if (m->attributes.count(ID::src)) - m->add_strpool_attribute(ID::src, extra_src_attrs); + m->attributes[ID::src] = cell->attributes[ID::src]; memory_renames[it.first] = m->name; design->select(module, m); } dict positional_ports; - dict temp_renamed_wires; + dict temp_renamed_wires; pool autopurge_tpl_bits; - for (auto tpl_w : tpl->wires()) - { - if (tpl_w->port_id > 0) - { + for (auto tpl_w : tpl->wires()) { + if (tpl_w->port_id > 0) { IdString posportname = stringf("$%d", tpl_w->port_id); positional_ports.emplace(posportname, tpl_w->name); if (tpl_w->get_bool_attribute(ID::techmap_autopurge) && - (!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) && - (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname)))) - { + (!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) && + (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname)))) { if (sigmaps.count(tpl) == 0) sigmaps[tpl].set(tpl); @@ -217,7 +211,7 @@ struct TechmapWorker if (tpl_w->get_bool_attribute(ID::_techmap_special_)) w->attributes.clear(); if (w->attributes.count(ID::src)) - w->add_strpool_attribute(ID::src, extra_src_attrs); + w->attributes[ID::src] = cell->attributes[ID::src]; } design->select(module, w); @@ -230,24 +224,24 @@ struct TechmapWorker pool tpl_written_bits; for (auto tpl_cell : tpl->cells()) - for (auto &conn : tpl_cell->connections()) - if (tpl_cell->output(conn.first)) - for (auto bit : conn.second) - tpl_written_bits.insert(bit); + for (auto &conn : tpl_cell->connections()) + if (tpl_cell->output(conn.first)) + for (auto bit : conn.second) + tpl_written_bits.insert(bit); for (auto &conn : tpl->connections()) for (auto bit : conn.first) tpl_written_bits.insert(bit); SigMap port_signal_map; - for (auto &it : cell->connections()) - { + for (auto &it : cell->connections()) { IdString portname = it.first; if (positional_ports.count(portname) > 0) portname = positional_ports.at(portname); if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) { if (portname.begins_with("$")) - log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str()); + log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), + tpl->name.c_str()); continue; } @@ -297,8 +291,7 @@ struct TechmapWorker if (w->port_output && !w->port_input) { port_signal_map.add(c.second, c.first); - } else - if (!w->port_output && w->port_input) { + } else if (!w->port_output && w->port_input) { port_signal_map.add(c.first, c.second); } else { module->connect(c); @@ -311,16 +304,15 @@ struct TechmapWorker auto lhs = GetSize(extra_connect.first); auto rhs = GetSize(extra_connect.second); if (lhs > rhs) - extra_connect.first.remove(rhs, lhs-rhs); + extra_connect.first.remove(rhs, lhs - rhs); else if (rhs > lhs) - extra_connect.second.remove(lhs, rhs-lhs); + extra_connect.second.remove(lhs, rhs - lhs); module->connect(extra_connect); break; } } - for (auto tpl_cell : tpl->cells()) - { + for (auto tpl_cell : tpl->cells()) { IdString c_name = tpl_cell->name; bool techmap_replace_cell = c_name.ends_with("_TECHMAP_REPLACE_"); @@ -339,8 +331,7 @@ struct TechmapWorker vector autopurge_ports; - for (auto &conn : c->connections()) - { + for (auto &conn : c->connections()) { bool autopurge = false; if (!autopurge_tpl_bits.empty()) { autopurge = GetSize(conn.second) != 0; @@ -375,7 +366,7 @@ struct TechmapWorker } if (c->attributes.count(ID::src)) - c->add_strpool_attribute(ID::src, extra_src_attrs); + c->attributes[ID::src] = cell->attributes[ID::src]; if (techmap_replace_cell) { for (auto attr : cell->attributes) @@ -396,8 +387,7 @@ struct TechmapWorker module->remove(cell); - for (auto &it : temp_renamed_wires) - { + for (auto &it : temp_renamed_wires) { Wire *w = it.first; IdString name = it.second; IdString altname = module->uniquify(name); @@ -407,8 +397,8 @@ struct TechmapWorker } } - bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool &handled_cells, - const dict> &celltypeMap, bool in_recursion) + bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool &handled_cells, + const dict> &celltypeMap, bool in_recursion) { std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; @@ -422,12 +412,11 @@ struct TechmapWorker SigMap sigmap(module); FfInitVals initvals(&sigmap, module); - TopoSort> cells; - dict> cell_to_inbit; - dict> outbit_to_cell; + TopoSort> cells; + dict> cell_to_inbit; + dict> outbit_to_cell; - for (auto cell : module->selected_cells()) - { + for (auto cell : module->selected_cells()) { if (handled_cells.count(cell) > 0) continue; @@ -441,8 +430,7 @@ struct TechmapWorker continue; } - for (auto &conn : cell->connections()) - { + for (auto &conn : cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); sig.remove_const(); @@ -464,14 +452,13 @@ struct TechmapWorker } for (auto &it_right : cell_to_inbit) - for (auto &it_sigbit : it_right.second) - for (auto &it_left : outbit_to_cell[it_sigbit]) - cells.edge(it_left, it_right.first); + for (auto &it_sigbit : it_right.second) + for (auto &it_left : outbit_to_cell[it_sigbit]) + cells.edge(it_left, it_right.first); cells.sort(); - for (auto cell : cells.sorted) - { + for (auto cell : cells.sorted) { log_assert(handled_cells.count(cell) == 0); log_assert(cell == module->cell(cell->name)); bool mapped_cell = false; @@ -481,8 +468,7 @@ struct TechmapWorker if (in_recursion && cell->type.begins_with("\\$")) cell_type = cell_type.substr(1); - for (auto &tpl_name : celltypeMap.at(cell_type)) - { + for (auto &tpl_name : celltypeMap.at(cell_type)) { IdString derived_name = tpl_name; RTLIL::Module *tpl = map->module(tpl_name); dict parameters(cell->parameters); @@ -501,12 +487,10 @@ struct TechmapWorker if (tpl->attributes.count(ID::techmap_wrap)) extmapper_name = "wrap"; - if (!extmapper_name.empty()) - { + if (!extmapper_name.empty()) { cell->type = cell_type; - if ((extern_mode && !in_recursion) || extmapper_name == "wrap") - { + if ((extern_mode && !in_recursion) || extmapper_name == "wrap") { std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); for (auto &c : cell->parameters) @@ -518,8 +502,7 @@ struct TechmapWorker RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design; RTLIL::Module *extmapper_module = extmapper_design->module(m_name); - if (extmapper_module == nullptr) - { + if (extmapper_module == nullptr) { extmapper_module = extmapper_design->addModule(m_name); RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell); @@ -542,7 +525,8 @@ struct TechmapWorker if (extmapper_name == "simplemap") { log("Creating %s with simplemap.\n", log_id(extmapper_module)); if (simplemap_mappers.count(extmapper_cell->type) == 0) - log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type)); + log_error("No simplemap mapper for cell type %s found!\n", + log_id(extmapper_cell->type)); simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell); extmapper_module->remove(extmapper_cell); } @@ -550,7 +534,8 @@ struct TechmapWorker if (extmapper_name == "maccmap") { log("Creating %s with maccmap.\n", log_id(extmapper_module)); if (extmapper_cell->type != ID($macc)) - log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type)); + log_error("The maccmap mapper can only map $macc (not %s) cells!\n", + log_id(extmapper_cell->type)); maccmap(extmapper_module, extmapper_cell); extmapper_module->remove(extmapper_cell); } @@ -572,21 +557,23 @@ struct TechmapWorker goto use_wrapper_tpl; } - auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type)); + auto msg = + stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); log("%s\n", msg.c_str()); } - log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); - } - else - { - auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type)); + log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), + log_id(cell->type), log_id(extmapper_module)); + } else { + auto msg = + stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); log("%s\n", msg.c_str()); } - log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str()); + log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), + log_id(cell->type), extmapper_name.c_str()); if (extmapper_name == "simplemap") { if (simplemap_mappers.count(cell->type) == 0) @@ -596,7 +583,8 @@ struct TechmapWorker if (extmapper_name == "maccmap") { if (cell->type != ID($macc)) - log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type)); + log_error("The maccmap mapper can only map $macc (not %s) cells!\n", + log_id(cell->type)); maccmap(module, cell); } @@ -614,13 +602,14 @@ struct TechmapWorker continue; if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0) continue; - if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0) + if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || + tpl->avail_parameters.count(conn.first) == 0) goto next_tpl; parameters[conn.first] = conn.second.as_const(); } if (0) { - next_tpl: + next_tpl: continue; } @@ -634,14 +623,16 @@ struct TechmapWorker std::vector v = sigmap(conn.second).to_sigbit_vector(); for (auto &bit : v) bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0); - parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); + parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), + RTLIL::SigSpec(v).as_const()); } if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) { std::vector v = sigmap(conn.second).to_sigbit_vector(); for (auto &bit : v) if (bit.wire != nullptr) bit = RTLIL::SigBit(RTLIL::State::Sx); - parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); + parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), + RTLIL::SigSpec(v).as_const()); } if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) { parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), initvals(conn.second)); @@ -666,7 +657,7 @@ struct TechmapWorker // Find highest bit set int bits = 0; for (int i = 0; i < 32; i++) - if (((unique_bit_id_counter-1) & (1 << i)) != 0) + if (((unique_bit_id_counter - 1) & (1 << i)) != 0) bits = i; // Increment index by one to get number of bits bits++; @@ -688,7 +679,7 @@ struct TechmapWorker } if (0) { - use_wrapper_tpl:; + use_wrapper_tpl:; // do not register techmap_wrap modules with techmap_cache } else { std::pair> key(tpl_name, parameters); @@ -710,15 +701,13 @@ struct TechmapWorker if (constmapped_tpl != nullptr) tpl = constmapped_tpl; - if (techmap_do_cache.count(tpl) == 0) - { + if (techmap_do_cache.count(tpl) == 0) { bool keep_running = true; techmap_do_cache[tpl] = true; pool techmap_wire_names; - while (keep_running) - { + while (keep_running) { TechmapWires twd = techmap_find_special_wires(tpl); keep_running = false; @@ -731,8 +720,9 @@ struct TechmapWorker for (const TechmapWireData &elem : it.second) { RTLIL::SigSpec value = elem.value; if (value.is_fully_const() && value.as_bool()) { - log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n", - derived_name.c_str(), log_id(elem.wire->name), log_signal(value)); + log("Not using module `%s' from techmap as it contains a %s marker wire with " + "non-zero value %s.\n", + derived_name.c_str(), log_id(elem.wire->name), log_signal(value)); techmap_do_cache[tpl] = false; } } @@ -741,27 +731,26 @@ struct TechmapWorker if (!techmap_do_cache[tpl]) break; - for (auto &it : twd) - { + for (auto &it : twd) { if (!it.first.contains("_TECHMAP_DO_") || it.second.empty()) continue; auto &data = it.second.front(); if (!data.value.is_fully_const()) - log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(data.wire->name), log_signal(data.value)); + log_error("Techmap yielded config wire %s with non-const value %s.\n", + log_id(data.wire->name), log_signal(data.value)); techmap_wire_names.erase(it.first); const char *p = data.wire->name.c_str(); - const char *q = strrchr(p+1, '.'); - q = q ? q+1 : p+1; + const char *q = strrchr(p + 1, '.'); + q = q ? q + 1 : p + 1; std::string cmd_string = data.value.as_const().decode_string(); restart_eval_cmd_string: - if (cmd_string.rfind("CONSTMAP; ", 0) == 0) - { + if (cmd_string.rfind("CONSTMAP; ", 0) == 0) { cmd_string = cmd_string.substr(strlen("CONSTMAP; ")); log("Analyzing pattern of constant bits for this cell:\n"); @@ -780,8 +769,7 @@ struct TechmapWorker dict port_connmap; dict cellbits_to_tplbits; - for (auto wire : tpl->wires().to_vector()) - { + for (auto wire : tpl->wires().to_vector()) { if (!wire->port_input || wire->port_output) continue; @@ -793,14 +781,15 @@ struct TechmapWorker wire->port_id = 0; for (int i = 0; i < wire->width; i++) { - port_new2old_map.emplace(RTLIL::SigBit(new_wire, i), RTLIL::SigBit(wire, i)); - port_connmap.emplace(RTLIL::SigBit(wire, i), RTLIL::SigBit(new_wire, i)); + port_new2old_map.emplace(RTLIL::SigBit(new_wire, i), + RTLIL::SigBit(wire, i)); + port_connmap.emplace(RTLIL::SigBit(wire, i), + RTLIL::SigBit(new_wire, i)); } } // Handle outputs first, as these cannot be remapped. - for (auto &conn : cell->connections()) - { + for (auto &conn : cell->connections()) { Wire *twire = tpl->wire(conn.first); if (!twire->port_output) continue; @@ -813,28 +802,22 @@ struct TechmapWorker } // Now handle inputs, remapping as necessary. - for (auto &conn : cell->connections()) - { + for (auto &conn : cell->connections()) { Wire *twire = tpl->wire(conn.first); if (twire->port_output) continue; - for (int i = 0; i < GetSize(conn.second); i++) - { + for (int i = 0; i < GetSize(conn.second); i++) { RTLIL::SigBit bit = sigmap(conn.second[i]); RTLIL::SigBit tplbit(twire, i); - if (bit.wire == nullptr) - { + if (bit.wire == nullptr) { RTLIL::SigBit oldbit = port_new2old_map.at(tplbit); port_connmap.at(oldbit) = bit; - } - else if (cellbits_to_tplbits.count(bit)) - { + } else if (cellbits_to_tplbits.count(bit)) { RTLIL::SigBit oldbit = port_new2old_map.at(tplbit); port_connmap.at(oldbit) = cellbits_to_tplbits[bit]; - } - else + } else cellbits_to_tplbits[bit] = tplbit; } } @@ -850,17 +833,18 @@ struct TechmapWorker goto restart_eval_cmd_string; } - if (cmd_string.rfind("RECURSION; ", 0) == 0) - { + if (cmd_string.rfind("RECURSION; ", 0) == 0) { cmd_string = cmd_string.substr(strlen("RECURSION; ")); - while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { } + while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { + } goto restart_eval_cmd_string; } Pass::call_on_module(map, tpl, cmd_string); log_assert(!strncmp(q, "_TECHMAP_DO_", 12)); - std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12); + std::string new_name = + data.wire->name.substr(0, q - p) + "_TECHMAP_DONE_" + data.wire->name.substr(q - p + 12); while (tpl->wire(new_name) != nullptr) new_name += "_"; tpl->rename(data.wire->name, new_name); @@ -872,12 +856,15 @@ struct TechmapWorker TechmapWires twd = techmap_find_special_wires(tpl); for (auto &it : twd) { - if (!it.first.ends_with("_TECHMAP_FAIL_") && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.contains("_TECHMAP_DO_") && !it.first.contains("_TECHMAP_DONE_")) + if (!it.first.ends_with("_TECHMAP_FAIL_") && + (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && + !it.first.contains("_TECHMAP_DO_") && !it.first.contains("_TECHMAP_DONE_")) log_error("Techmap yielded unknown config wire %s.\n", log_id(it.first)); if (techmap_do_cache[tpl]) for (auto &it2 : it.second) if (!it2.value.is_fully_const()) - log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(it2.wire->name), log_signal(it2.value)); + log_error("Techmap yielded config wire %s with non-const value %s.\n", + log_id(it2.wire->name), log_signal(it2.value)); techmap_wire_names.erase(it.first); } @@ -890,7 +877,8 @@ struct TechmapWorker log_continue = false; mkdebug.off(); } - while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { } + while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { + } } } @@ -920,12 +908,10 @@ struct TechmapWorker } } - if (extern_mode && !in_recursion) - { + if (extern_mode && !in_recursion) { std::string m_name = stringf("$extern:%s", log_id(tpl)); - if (!design->module(m_name)) - { + if (!design->module(m_name)) { RTLIL::Module *m = design->addModule(m_name); tpl->cloneInto(m); @@ -940,15 +926,14 @@ struct TechmapWorker log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name)); cell->type = m_name; cell->parameters.clear(); - } - else - { + } else { auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); log("%s\n", msg.c_str()); } - log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); + log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), + log_id(cell->type), log_id(tpl)); techmap_module_worker(design, module, cell, tpl); cell = nullptr; } @@ -974,7 +959,7 @@ struct TechmapWorker }; struct TechmapPass : public Pass { - TechmapPass() : Pass("techmap", "generic technology mapper") { } + TechmapPass() : Pass("techmap", "generic technology mapper") {} void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -1155,19 +1140,19 @@ struct TechmapPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-map" && argidx+1 < args.size()) { + if (args[argidx] == "-map" && argidx + 1 < args.size()) { map_files.push_back(args[++argidx]); continue; } - if (args[argidx] == "-max_iter" && argidx+1 < args.size()) { + if (args[argidx] == "-max_iter" && argidx + 1 < args.size()) { max_iter = atoi(args[++argidx].c_str()); continue; } - if (args[argidx] == "-D" && argidx+1 < args.size()) { + if (args[argidx] == "-D" && argidx + 1 < args.size()) { verilog_frontend += " -D " + args[++argidx]; continue; } - if (args[argidx] == "-I" && argidx+1 < args.size()) { + if (args[argidx] == "-I" && argidx + 1 < args.size()) { verilog_frontend += " -I " + args[++argidx]; continue; } @@ -1203,13 +1188,15 @@ struct TechmapPass : public Pass { if (fn.compare(0, 1, "%") == 0) { if (!saved_designs.count(fn.substr(1))) { delete map; - log_cmd_error("Can't open saved design `%s'.\n", fn.c_str()+1); + log_cmd_error("Can't open saved design `%s'.\n", fn.c_str() + 1); } for (auto mod : saved_designs.at(fn.substr(1))->modules()) if (!map->module(mod->name)) map->add(mod->clone()); } else { - Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend)); + Frontend::frontend_call( + map, nullptr, fn, + (fn.size() > 3 && fn.compare(fn.size() - 3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend)); } } @@ -1235,15 +1222,15 @@ struct TechmapPass : public Pass { if (epos == std::string::npos) log_error("Malformed techmap_celltype pattern %s\n", q); for (size_t i = pos + 1; i < epos; i++) { - queue.push_back(name.substr(0, pos) + name[i] + name.substr(epos + 1, std::string::npos)); + queue.push_back(name.substr(0, pos) + name[i] + + name.substr(epos + 1, std::string::npos)); } } } } free(p); } else { - IdString module_name = module->name.begins_with("\\$") ? - module->name.substr(1) : module->name.str(); + IdString module_name = module->name.begins_with("\\$") ? module->name.substr(1) : module->name.str(); celltypeMap[module_name].insert(module->name); } } @@ -1260,14 +1247,13 @@ struct TechmapPass : public Pass { for (auto module : design->modules()) worker.module_queue.insert(module); - while (!worker.module_queue.empty()) - { + while (!worker.module_queue.empty()) { RTLIL::Module *module = *worker.module_queue.begin(); worker.module_queue.erase(module); int module_max_iter = max_iter; bool did_something = true; - pool handled_cells; + pool handled_cells; while (did_something) { did_something = false; if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false)) From 67f17004869c3aeea75c1e5620f73bfb1b34e7cd Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Fri, 29 Sep 2023 13:20:43 -0700 Subject: [PATCH 055/240] Revert formatting changes. --- passes/techmap/simplemap.cc | 200 ++++++++++++-------------- passes/techmap/techmap.cc | 274 +++++++++++++++++++----------------- 2 files changed, 235 insertions(+), 239 deletions(-) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 14c07922b14..7461460fed8 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -18,10 +18,10 @@ */ #include "simplemap.h" -#include "kernel/ff.h" #include "kernel/sigtools.h" -#include +#include "kernel/ff.h" #include +#include #include USING_YOSYS_NAMESPACE @@ -64,16 +64,11 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) } IdString gate_type; - if (cell->type == ID($and)) - gate_type = ID($_AND_); - if (cell->type == ID($or)) - gate_type = ID($_OR_); - if (cell->type == ID($xor)) - gate_type = ID($_XOR_); - if (cell->type == ID($xnor)) - gate_type = ID($_XNOR_); - if (cell->type == ID($bweqx)) - gate_type = ID($_XNOR_); + if (cell->type == ID($and)) gate_type = ID($_AND_); + if (cell->type == ID($or)) gate_type = ID($_OR_); + if (cell->type == ID($xor)) gate_type = ID($_XOR_); + if (cell->type == ID($xnor)) gate_type = ID($_XNOR_); + if (cell->type == ID($bweqx)) gate_type = ID($_XNOR_); log_assert(!gate_type.empty()); for (int i = 0; i < GetSize(sig_y); i++) { @@ -94,44 +89,36 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) return; if (sig_a.size() == 0) { - if (cell->type == ID($reduce_and)) - module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); - if (cell->type == ID($reduce_or)) - module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); - if (cell->type == ID($reduce_xor)) - module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); - if (cell->type == ID($reduce_xnor)) - module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); - if (cell->type == ID($reduce_bool)) - module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == ID($reduce_and)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); + if (cell->type == ID($reduce_or)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == ID($reduce_xor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == ID($reduce_xnor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); + if (cell->type == ID($reduce_bool)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); return; } if (sig_y.size() > 1) { - module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size() - 1), RTLIL::SigSpec(0, sig_y.size() - 1))); + module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } IdString gate_type; - if (cell->type == ID($reduce_and)) - gate_type = ID($_AND_); - if (cell->type == ID($reduce_or)) - gate_type = ID($_OR_); - if (cell->type == ID($reduce_xor)) - gate_type = ID($_XOR_); - if (cell->type == ID($reduce_xnor)) - gate_type = ID($_XOR_); - if (cell->type == ID($reduce_bool)) - gate_type = ID($_OR_); + if (cell->type == ID($reduce_and)) gate_type = ID($_AND_); + if (cell->type == ID($reduce_or)) gate_type = ID($_OR_); + if (cell->type == ID($reduce_xor)) gate_type = ID($_XOR_); + if (cell->type == ID($reduce_xnor)) gate_type = ID($_XOR_); + if (cell->type == ID($reduce_bool)) gate_type = ID($_OR_); log_assert(!gate_type.empty()); RTLIL::Cell *last_output_cell = NULL; - while (sig_a.size() > 1) { + while (sig_a.size() > 1) + { RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2); - for (int i = 0; i < sig_a.size(); i += 2) { - if (i + 1 == sig_a.size()) { + for (int i = 0; i < sig_a.size(); i += 2) + { + if (i+1 == sig_a.size()) { sig_t.append(sig_a[i]); continue; } @@ -139,8 +126,8 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); - gate->setPort(ID::B, sig_a[i + 1]); - gate->setPort(ID::Y, sig_t[i / 2]); + gate->setPort(ID::B, sig_a[i+1]); + gate->setPort(ID::Y, sig_t[i/2]); last_output_cell = gate; } @@ -166,11 +153,13 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell *cell) { - while (sig.size() > 1) { + while (sig.size() > 1) + { RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2); - for (int i = 0; i < sig.size(); i += 2) { - if (i + 1 == sig.size()) { + for (int i = 0; i < sig.size(); i += 2) + { + if (i+1 == sig.size()) { sig_t.append(sig[i]); continue; } @@ -178,8 +167,8 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_)); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig[i]); - gate->setPort(ID::B, sig[i + 1]); - gate->setPort(ID::Y, sig_t[i / 2]); + gate->setPort(ID::B, sig[i+1]); + gate->setPort(ID::Y, sig_t[i/2]); } sig = sig_t; @@ -200,7 +189,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) return; if (sig_y.size() > 1) { - module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size() - 1), RTLIL::SigSpec(0, sig_y.size() - 1))); + module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } @@ -224,15 +213,13 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) return; if (sig_y.size() > 1) { - module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size() - 1), RTLIL::SigSpec(0, sig_y.size() - 1))); + module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } IdString gate_type; - if (cell->type == ID($logic_and)) - gate_type = ID($_AND_); - if (cell->type == ID($logic_or)) - gate_type = ID($_OR_); + if (cell->type == ID($logic_and)) gate_type = ID($_AND_); + if (cell->type == ID($logic_or)) gate_type = ID($_OR_); log_assert(!gate_type.empty()); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); @@ -253,22 +240,19 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); xor_cell->attributes[ID::src] = cell->attributes[ID::src]; - // xor_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); simplemap_bitop(module, xor_cell); module->remove(xor_cell); RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID); RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out); reduce_cell->attributes[ID::src] = cell->attributes[ID::src]; - // reduce_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); simplemap_reduce(module, reduce_cell); module->remove(reduce_cell); if (!is_ne) { RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y); not_cell->attributes[ID::src] = cell->attributes[ID::src]; - // not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); - simplemap_lognot(module, not_cell); + simplemap_lognot(module, not_cell); module->remove(not_cell); } } @@ -328,15 +312,15 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell) int width = GetSize(cell->getPort(ID::Y)); for (int idx = 0; idx < GetSize(sel); idx++) { - SigSpec new_data = module->addWire(NEW_ID, GetSize(data) / 2); + SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2); for (int i = 0; i < GetSize(new_data); i += width) { for (int k = 0; k < width; k++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); gate->attributes[ID::src] = cell->attributes[ID::src]; - gate->setPort(ID::A, data[i * 2 + k]); - gate->setPort(ID::B, data[i * 2 + width + k]); + gate->setPort(ID::A, data[i*2+k]); + gate->setPort(ID::B, data[i*2+width+k]); gate->setPort(ID::S, sel[idx]); - gate->setPort(ID::Y, new_data[i + k]); + gate->setPort(ID::Y, new_data[i+k]); } } data = new_data; @@ -352,14 +336,14 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell) lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int()); for (int idx = 0; GetSize(lut_data) > 1; idx++) { - SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data) / 2); + SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2); for (int i = 0; i < GetSize(lut_data); i += 2) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, lut_data[i]); - gate->setPort(ID::B, lut_data[i + 1]); + gate->setPort(ID::B, lut_data[i+1]); gate->setPort(ID::S, lut_ctrl[idx]); - gate->setPort(ID::Y, new_lut_data[i / 2]); + gate->setPort(ID::Y, new_lut_data[i/2]); } lut_data = new_lut_data; } @@ -381,11 +365,11 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < depth; i++) { SigSpec in, pat; for (int j = 0; j < width; j++) { - if (table[2 * i * width + 2 * j + 0] == State::S1) { + if (table[2*i*width + 2*j + 0] == State::S1) { in.append(ctrl[j]); pat.append(State::S0); } - if (table[2 * i * width + 2 * j + 1] == State::S1) { + if (table[2*i*width + 2*j + 1] == State::S1) { in.append(ctrl[j]); pat.append(State::S1); } @@ -423,56 +407,56 @@ void simplemap_ff(RTLIL::Module *, RTLIL::Cell *cell) } } -void simplemap_get_mappers(dict &mappers) +void simplemap_get_mappers(dict &mappers) { - mappers[ID($not)] = simplemap_not; - mappers[ID($pos)] = simplemap_pos; - mappers[ID($and)] = simplemap_bitop; - mappers[ID($or)] = simplemap_bitop; - mappers[ID($xor)] = simplemap_bitop; - mappers[ID($xnor)] = simplemap_bitop; - mappers[ID($bweqx)] = simplemap_bitop; - mappers[ID($reduce_and)] = simplemap_reduce; - mappers[ID($reduce_or)] = simplemap_reduce; - mappers[ID($reduce_xor)] = simplemap_reduce; + mappers[ID($not)] = simplemap_not; + mappers[ID($pos)] = simplemap_pos; + mappers[ID($and)] = simplemap_bitop; + mappers[ID($or)] = simplemap_bitop; + mappers[ID($xor)] = simplemap_bitop; + mappers[ID($xnor)] = simplemap_bitop; + mappers[ID($bweqx)] = simplemap_bitop; + mappers[ID($reduce_and)] = simplemap_reduce; + mappers[ID($reduce_or)] = simplemap_reduce; + mappers[ID($reduce_xor)] = simplemap_reduce; mappers[ID($reduce_xnor)] = simplemap_reduce; mappers[ID($reduce_bool)] = simplemap_reduce; - mappers[ID($logic_not)] = simplemap_lognot; - mappers[ID($logic_and)] = simplemap_logbin; - mappers[ID($logic_or)] = simplemap_logbin; - mappers[ID($eq)] = simplemap_eqne; - mappers[ID($eqx)] = simplemap_eqne; - mappers[ID($ne)] = simplemap_eqne; - mappers[ID($nex)] = simplemap_eqne; - mappers[ID($mux)] = simplemap_mux; - mappers[ID($bwmux)] = simplemap_bwmux; - mappers[ID($tribuf)] = simplemap_tribuf; - mappers[ID($bmux)] = simplemap_bmux; - mappers[ID($lut)] = simplemap_lut; - mappers[ID($sop)] = simplemap_sop; - mappers[ID($slice)] = simplemap_slice; - mappers[ID($concat)] = simplemap_concat; - mappers[ID($sr)] = simplemap_ff; - mappers[ID($ff)] = simplemap_ff; - mappers[ID($dff)] = simplemap_ff; - mappers[ID($dffe)] = simplemap_ff; - mappers[ID($dffsr)] = simplemap_ff; - mappers[ID($dffsre)] = simplemap_ff; - mappers[ID($adff)] = simplemap_ff; - mappers[ID($sdff)] = simplemap_ff; - mappers[ID($adffe)] = simplemap_ff; - mappers[ID($sdffe)] = simplemap_ff; - mappers[ID($sdffce)] = simplemap_ff; - mappers[ID($aldff)] = simplemap_ff; - mappers[ID($aldffe)] = simplemap_ff; - mappers[ID($dlatch)] = simplemap_ff; - mappers[ID($adlatch)] = simplemap_ff; - mappers[ID($dlatchsr)] = simplemap_ff; + mappers[ID($logic_not)] = simplemap_lognot; + mappers[ID($logic_and)] = simplemap_logbin; + mappers[ID($logic_or)] = simplemap_logbin; + mappers[ID($eq)] = simplemap_eqne; + mappers[ID($eqx)] = simplemap_eqne; + mappers[ID($ne)] = simplemap_eqne; + mappers[ID($nex)] = simplemap_eqne; + mappers[ID($mux)] = simplemap_mux; + mappers[ID($bwmux)] = simplemap_bwmux; + mappers[ID($tribuf)] = simplemap_tribuf; + mappers[ID($bmux)] = simplemap_bmux; + mappers[ID($lut)] = simplemap_lut; + mappers[ID($sop)] = simplemap_sop; + mappers[ID($slice)] = simplemap_slice; + mappers[ID($concat)] = simplemap_concat; + mappers[ID($sr)] = simplemap_ff; + mappers[ID($ff)] = simplemap_ff; + mappers[ID($dff)] = simplemap_ff; + mappers[ID($dffe)] = simplemap_ff; + mappers[ID($dffsr)] = simplemap_ff; + mappers[ID($dffsre)] = simplemap_ff; + mappers[ID($adff)] = simplemap_ff; + mappers[ID($sdff)] = simplemap_ff; + mappers[ID($adffe)] = simplemap_ff; + mappers[ID($sdffe)] = simplemap_ff; + mappers[ID($sdffce)] = simplemap_ff; + mappers[ID($aldff)] = simplemap_ff; + mappers[ID($aldffe)] = simplemap_ff; + mappers[ID($dlatch)] = simplemap_ff; + mappers[ID($adlatch)] = simplemap_ff; + mappers[ID($dlatchsr)] = simplemap_ff; } void simplemap(RTLIL::Module *module, RTLIL::Cell *cell) { - static dict mappers; + static dict mappers; static bool initialized_mappers = false; if (!initialized_mappers) { @@ -487,7 +471,7 @@ YOSYS_NAMESPACE_END PRIVATE_NAMESPACE_BEGIN struct SimplemapPass : public Pass { - SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") {} + SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -509,13 +493,13 @@ struct SimplemapPass : public Pass { log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n"); extra_args(args, 1, design); - dict mappers; + dict mappers; simplemap_get_mappers(mappers); for (auto mod : design->modules()) { if (!design->selected(mod) || mod->get_blackbox_attribute()) continue; - std::vector cells = mod->cells(); + std::vector cells = mod->cells(); for (auto cell : cells) { if (mappers.count(cell->type) == 0) continue; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 52a24dcf3ba..23d0d93fc57 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -17,14 +17,14 @@ * */ -#include "kernel/ffinit.h" -#include "kernel/sigtools.h" -#include "kernel/utils.h" #include "kernel/yosys.h" +#include "kernel/utils.h" +#include "kernel/sigtools.h" +#include "kernel/ffinit.h" #include "libs/sha1/sha1.h" -#include #include +#include #include #include "simplemap.h" @@ -42,7 +42,7 @@ PRIVATE_NAMESPACE_BEGIN void apply_prefix(IdString prefix, IdString &id) { if (id[0] == '\\') - id = stringf("%s.%s", prefix.c_str(), id.c_str() + 1); + id = stringf("%s.%s", prefix.c_str(), id.c_str()+1); else id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str()); } @@ -60,12 +60,13 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) sig = chunks; } -struct TechmapWorker { - dict simplemap_mappers; - dict>, RTLIL::Module *> techmap_cache; - dict techmap_do_cache; - pool module_queue; - dict sigmaps; +struct TechmapWorker +{ + dict simplemap_mappers; + dict>, RTLIL::Module*> techmap_cache; + dict techmap_do_cache; + pool module_queue; + dict sigmaps; pool log_msg_cache; @@ -97,9 +98,9 @@ struct TechmapWorker { } else if (connbits_map.count(bit)) { if (verbose) log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first), - connbits_map.at(bit).second, log_id(connbits_map.at(bit).first)); - constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, log_id(connbits_map.at(bit).first), - connbits_map.at(bit).second); + connbits_map.at(bit).second, log_id(connbits_map.at(bit).first)); + constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, + log_id(connbits_map.at(bit).first), connbits_map.at(bit).second); } else { connbits_map.emplace(bit, std::make_pair(conn.first, i)); constmap_info += stringf("|%s %d", log_id(conn.first), i); @@ -133,8 +134,8 @@ struct TechmapWorker { if (!result.empty()) { SigMap sigmap(module); for (auto &it1 : result) - for (auto &it2 : it1.second) - sigmap.apply(it2.value); + for (auto &it2 : it1.second) + sigmap.apply(it2.value); } return result; @@ -145,7 +146,7 @@ struct TechmapWorker { if (tpl->processes.size() != 0) { log("Technology map yielded processes:"); for (auto &it : tpl->processes) - log(" %s", log_id(it.first)); + log(" %s",log_id(it.first)); log("\n"); if (autoproc_mode) { Pass::call_on_module(tpl->design, tpl, "proc"); @@ -155,7 +156,6 @@ struct TechmapWorker { } std::string orig_cell_name; - orig_cell_name = cell->name.str(); for (auto tpl_cell : tpl->cells()) if (tpl_cell->name.ends_with("_TECHMAP_REPLACE_")) { @@ -164,28 +164,32 @@ struct TechmapWorker { } dict memory_renames; + for (auto &it : tpl->memories) { IdString m_name = it.first; apply_prefix(cell->name, m_name); RTLIL::Memory *m = module->addMemory(m_name, it.second); if (m->attributes.count(ID::src)) - m->attributes[ID::src] = cell->attributes[ID::src]; + m->attributes[ID::src] = cell->attributes[ID::src]; memory_renames[it.first] = m->name; design->select(module, m); } dict positional_ports; - dict temp_renamed_wires; + dict temp_renamed_wires; pool autopurge_tpl_bits; - for (auto tpl_w : tpl->wires()) { - if (tpl_w->port_id > 0) { + for (auto tpl_w : tpl->wires()) + { + if (tpl_w->port_id > 0) + { IdString posportname = stringf("$%d", tpl_w->port_id); positional_ports.emplace(posportname, tpl_w->name); if (tpl_w->get_bool_attribute(ID::techmap_autopurge) && - (!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) && - (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname)))) { + (!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) && + (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname)))) + { if (sigmaps.count(tpl) == 0) sigmaps[tpl].set(tpl); @@ -211,7 +215,7 @@ struct TechmapWorker { if (tpl_w->get_bool_attribute(ID::_techmap_special_)) w->attributes.clear(); if (w->attributes.count(ID::src)) - w->attributes[ID::src] = cell->attributes[ID::src]; + w->attributes[ID::src] = cell->attributes[ID::src]; } design->select(module, w); @@ -224,24 +228,24 @@ struct TechmapWorker { pool tpl_written_bits; for (auto tpl_cell : tpl->cells()) - for (auto &conn : tpl_cell->connections()) - if (tpl_cell->output(conn.first)) - for (auto bit : conn.second) - tpl_written_bits.insert(bit); + for (auto &conn : tpl_cell->connections()) + if (tpl_cell->output(conn.first)) + for (auto bit : conn.second) + tpl_written_bits.insert(bit); for (auto &conn : tpl->connections()) for (auto bit : conn.first) tpl_written_bits.insert(bit); SigMap port_signal_map; - for (auto &it : cell->connections()) { + for (auto &it : cell->connections()) + { IdString portname = it.first; if (positional_ports.count(portname) > 0) portname = positional_ports.at(portname); if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) { if (portname.begins_with("$")) - log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), - tpl->name.c_str()); + log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str()); continue; } @@ -291,7 +295,8 @@ struct TechmapWorker { if (w->port_output && !w->port_input) { port_signal_map.add(c.second, c.first); - } else if (!w->port_output && w->port_input) { + } else + if (!w->port_output && w->port_input) { port_signal_map.add(c.first, c.second); } else { module->connect(c); @@ -304,15 +309,16 @@ struct TechmapWorker { auto lhs = GetSize(extra_connect.first); auto rhs = GetSize(extra_connect.second); if (lhs > rhs) - extra_connect.first.remove(rhs, lhs - rhs); + extra_connect.first.remove(rhs, lhs-rhs); else if (rhs > lhs) - extra_connect.second.remove(lhs, rhs - lhs); + extra_connect.second.remove(lhs, rhs-lhs); module->connect(extra_connect); break; } } - for (auto tpl_cell : tpl->cells()) { + for (auto tpl_cell : tpl->cells()) + { IdString c_name = tpl_cell->name; bool techmap_replace_cell = c_name.ends_with("_TECHMAP_REPLACE_"); @@ -331,7 +337,8 @@ struct TechmapWorker { vector autopurge_ports; - for (auto &conn : c->connections()) { + for (auto &conn : c->connections()) + { bool autopurge = false; if (!autopurge_tpl_bits.empty()) { autopurge = GetSize(conn.second) != 0; @@ -366,7 +373,7 @@ struct TechmapWorker { } if (c->attributes.count(ID::src)) - c->attributes[ID::src] = cell->attributes[ID::src]; + c->attributes[ID::src] = cell->attributes[ID::src]; if (techmap_replace_cell) { for (auto attr : cell->attributes) @@ -387,7 +394,8 @@ struct TechmapWorker { module->remove(cell); - for (auto &it : temp_renamed_wires) { + for (auto &it : temp_renamed_wires) + { Wire *w = it.first; IdString name = it.second; IdString altname = module->uniquify(name); @@ -397,8 +405,8 @@ struct TechmapWorker { } } - bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool &handled_cells, - const dict> &celltypeMap, bool in_recursion) + bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool &handled_cells, + const dict> &celltypeMap, bool in_recursion) { std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; @@ -412,11 +420,12 @@ struct TechmapWorker { SigMap sigmap(module); FfInitVals initvals(&sigmap, module); - TopoSort> cells; - dict> cell_to_inbit; - dict> outbit_to_cell; + TopoSort> cells; + dict> cell_to_inbit; + dict> outbit_to_cell; - for (auto cell : module->selected_cells()) { + for (auto cell : module->selected_cells()) + { if (handled_cells.count(cell) > 0) continue; @@ -430,7 +439,8 @@ struct TechmapWorker { continue; } - for (auto &conn : cell->connections()) { + for (auto &conn : cell->connections()) + { RTLIL::SigSpec sig = sigmap(conn.second); sig.remove_const(); @@ -452,13 +462,14 @@ struct TechmapWorker { } for (auto &it_right : cell_to_inbit) - for (auto &it_sigbit : it_right.second) - for (auto &it_left : outbit_to_cell[it_sigbit]) - cells.edge(it_left, it_right.first); + for (auto &it_sigbit : it_right.second) + for (auto &it_left : outbit_to_cell[it_sigbit]) + cells.edge(it_left, it_right.first); cells.sort(); - for (auto cell : cells.sorted) { + for (auto cell : cells.sorted) + { log_assert(handled_cells.count(cell) == 0); log_assert(cell == module->cell(cell->name)); bool mapped_cell = false; @@ -468,7 +479,8 @@ struct TechmapWorker { if (in_recursion && cell->type.begins_with("\\$")) cell_type = cell_type.substr(1); - for (auto &tpl_name : celltypeMap.at(cell_type)) { + for (auto &tpl_name : celltypeMap.at(cell_type)) + { IdString derived_name = tpl_name; RTLIL::Module *tpl = map->module(tpl_name); dict parameters(cell->parameters); @@ -487,10 +499,12 @@ struct TechmapWorker { if (tpl->attributes.count(ID::techmap_wrap)) extmapper_name = "wrap"; - if (!extmapper_name.empty()) { + if (!extmapper_name.empty()) + { cell->type = cell_type; - if ((extern_mode && !in_recursion) || extmapper_name == "wrap") { + if ((extern_mode && !in_recursion) || extmapper_name == "wrap") + { std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); for (auto &c : cell->parameters) @@ -502,7 +516,8 @@ struct TechmapWorker { RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design; RTLIL::Module *extmapper_module = extmapper_design->module(m_name); - if (extmapper_module == nullptr) { + if (extmapper_module == nullptr) + { extmapper_module = extmapper_design->addModule(m_name); RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell); @@ -525,8 +540,7 @@ struct TechmapWorker { if (extmapper_name == "simplemap") { log("Creating %s with simplemap.\n", log_id(extmapper_module)); if (simplemap_mappers.count(extmapper_cell->type) == 0) - log_error("No simplemap mapper for cell type %s found!\n", - log_id(extmapper_cell->type)); + log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type)); simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell); extmapper_module->remove(extmapper_cell); } @@ -534,8 +548,7 @@ struct TechmapWorker { if (extmapper_name == "maccmap") { log("Creating %s with maccmap.\n", log_id(extmapper_module)); if (extmapper_cell->type != ID($macc)) - log_error("The maccmap mapper can only map $macc (not %s) cells!\n", - log_id(extmapper_cell->type)); + log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type)); maccmap(extmapper_module, extmapper_cell); extmapper_module->remove(extmapper_cell); } @@ -557,23 +570,21 @@ struct TechmapWorker { goto use_wrapper_tpl; } - auto msg = - stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type)); + auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); log("%s\n", msg.c_str()); } - log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), - log_id(cell->type), log_id(extmapper_module)); - } else { - auto msg = - stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type)); + log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); + } + else + { + auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); log("%s\n", msg.c_str()); } - log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), - log_id(cell->type), extmapper_name.c_str()); + log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str()); if (extmapper_name == "simplemap") { if (simplemap_mappers.count(cell->type) == 0) @@ -583,8 +594,7 @@ struct TechmapWorker { if (extmapper_name == "maccmap") { if (cell->type != ID($macc)) - log_error("The maccmap mapper can only map $macc (not %s) cells!\n", - log_id(cell->type)); + log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type)); maccmap(module, cell); } @@ -602,14 +612,13 @@ struct TechmapWorker { continue; if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0) continue; - if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || - tpl->avail_parameters.count(conn.first) == 0) + if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0) goto next_tpl; parameters[conn.first] = conn.second.as_const(); } if (0) { - next_tpl: + next_tpl: continue; } @@ -623,16 +632,14 @@ struct TechmapWorker { std::vector v = sigmap(conn.second).to_sigbit_vector(); for (auto &bit : v) bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0); - parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), - RTLIL::SigSpec(v).as_const()); + parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); } if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) { std::vector v = sigmap(conn.second).to_sigbit_vector(); for (auto &bit : v) if (bit.wire != nullptr) bit = RTLIL::SigBit(RTLIL::State::Sx); - parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), - RTLIL::SigSpec(v).as_const()); + parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); } if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) { parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), initvals(conn.second)); @@ -657,7 +664,7 @@ struct TechmapWorker { // Find highest bit set int bits = 0; for (int i = 0; i < 32; i++) - if (((unique_bit_id_counter - 1) & (1 << i)) != 0) + if (((unique_bit_id_counter-1) & (1 << i)) != 0) bits = i; // Increment index by one to get number of bits bits++; @@ -679,7 +686,7 @@ struct TechmapWorker { } if (0) { - use_wrapper_tpl:; + use_wrapper_tpl:; // do not register techmap_wrap modules with techmap_cache } else { std::pair> key(tpl_name, parameters); @@ -701,13 +708,15 @@ struct TechmapWorker { if (constmapped_tpl != nullptr) tpl = constmapped_tpl; - if (techmap_do_cache.count(tpl) == 0) { + if (techmap_do_cache.count(tpl) == 0) + { bool keep_running = true; techmap_do_cache[tpl] = true; pool techmap_wire_names; - while (keep_running) { + while (keep_running) + { TechmapWires twd = techmap_find_special_wires(tpl); keep_running = false; @@ -720,9 +729,8 @@ struct TechmapWorker { for (const TechmapWireData &elem : it.second) { RTLIL::SigSpec value = elem.value; if (value.is_fully_const() && value.as_bool()) { - log("Not using module `%s' from techmap as it contains a %s marker wire with " - "non-zero value %s.\n", - derived_name.c_str(), log_id(elem.wire->name), log_signal(value)); + log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n", + derived_name.c_str(), log_id(elem.wire->name), log_signal(value)); techmap_do_cache[tpl] = false; } } @@ -731,26 +739,27 @@ struct TechmapWorker { if (!techmap_do_cache[tpl]) break; - for (auto &it : twd) { + for (auto &it : twd) + { if (!it.first.contains("_TECHMAP_DO_") || it.second.empty()) continue; auto &data = it.second.front(); if (!data.value.is_fully_const()) - log_error("Techmap yielded config wire %s with non-const value %s.\n", - log_id(data.wire->name), log_signal(data.value)); + log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(data.wire->name), log_signal(data.value)); techmap_wire_names.erase(it.first); const char *p = data.wire->name.c_str(); - const char *q = strrchr(p + 1, '.'); - q = q ? q + 1 : p + 1; + const char *q = strrchr(p+1, '.'); + q = q ? q+1 : p+1; std::string cmd_string = data.value.as_const().decode_string(); restart_eval_cmd_string: - if (cmd_string.rfind("CONSTMAP; ", 0) == 0) { + if (cmd_string.rfind("CONSTMAP; ", 0) == 0) + { cmd_string = cmd_string.substr(strlen("CONSTMAP; ")); log("Analyzing pattern of constant bits for this cell:\n"); @@ -769,7 +778,8 @@ struct TechmapWorker { dict port_connmap; dict cellbits_to_tplbits; - for (auto wire : tpl->wires().to_vector()) { + for (auto wire : tpl->wires().to_vector()) + { if (!wire->port_input || wire->port_output) continue; @@ -781,15 +791,14 @@ struct TechmapWorker { wire->port_id = 0; for (int i = 0; i < wire->width; i++) { - port_new2old_map.emplace(RTLIL::SigBit(new_wire, i), - RTLIL::SigBit(wire, i)); - port_connmap.emplace(RTLIL::SigBit(wire, i), - RTLIL::SigBit(new_wire, i)); + port_new2old_map.emplace(RTLIL::SigBit(new_wire, i), RTLIL::SigBit(wire, i)); + port_connmap.emplace(RTLIL::SigBit(wire, i), RTLIL::SigBit(new_wire, i)); } } // Handle outputs first, as these cannot be remapped. - for (auto &conn : cell->connections()) { + for (auto &conn : cell->connections()) + { Wire *twire = tpl->wire(conn.first); if (!twire->port_output) continue; @@ -802,22 +811,28 @@ struct TechmapWorker { } // Now handle inputs, remapping as necessary. - for (auto &conn : cell->connections()) { + for (auto &conn : cell->connections()) + { Wire *twire = tpl->wire(conn.first); if (twire->port_output) continue; - for (int i = 0; i < GetSize(conn.second); i++) { + for (int i = 0; i < GetSize(conn.second); i++) + { RTLIL::SigBit bit = sigmap(conn.second[i]); RTLIL::SigBit tplbit(twire, i); - if (bit.wire == nullptr) { + if (bit.wire == nullptr) + { RTLIL::SigBit oldbit = port_new2old_map.at(tplbit); port_connmap.at(oldbit) = bit; - } else if (cellbits_to_tplbits.count(bit)) { + } + else if (cellbits_to_tplbits.count(bit)) + { RTLIL::SigBit oldbit = port_new2old_map.at(tplbit); port_connmap.at(oldbit) = cellbits_to_tplbits[bit]; - } else + } + else cellbits_to_tplbits[bit] = tplbit; } } @@ -833,18 +848,17 @@ struct TechmapWorker { goto restart_eval_cmd_string; } - if (cmd_string.rfind("RECURSION; ", 0) == 0) { + if (cmd_string.rfind("RECURSION; ", 0) == 0) + { cmd_string = cmd_string.substr(strlen("RECURSION; ")); - while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { - } + while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { } goto restart_eval_cmd_string; } Pass::call_on_module(map, tpl, cmd_string); log_assert(!strncmp(q, "_TECHMAP_DO_", 12)); - std::string new_name = - data.wire->name.substr(0, q - p) + "_TECHMAP_DONE_" + data.wire->name.substr(q - p + 12); + std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12); while (tpl->wire(new_name) != nullptr) new_name += "_"; tpl->rename(data.wire->name, new_name); @@ -856,15 +870,12 @@ struct TechmapWorker { TechmapWires twd = techmap_find_special_wires(tpl); for (auto &it : twd) { - if (!it.first.ends_with("_TECHMAP_FAIL_") && - (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && - !it.first.contains("_TECHMAP_DO_") && !it.first.contains("_TECHMAP_DONE_")) + if (!it.first.ends_with("_TECHMAP_FAIL_") && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.contains("_TECHMAP_DO_") && !it.first.contains("_TECHMAP_DONE_")) log_error("Techmap yielded unknown config wire %s.\n", log_id(it.first)); if (techmap_do_cache[tpl]) for (auto &it2 : it.second) if (!it2.value.is_fully_const()) - log_error("Techmap yielded config wire %s with non-const value %s.\n", - log_id(it2.wire->name), log_signal(it2.value)); + log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(it2.wire->name), log_signal(it2.value)); techmap_wire_names.erase(it.first); } @@ -877,8 +888,7 @@ struct TechmapWorker { log_continue = false; mkdebug.off(); } - while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { - } + while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { } } } @@ -908,10 +918,12 @@ struct TechmapWorker { } } - if (extern_mode && !in_recursion) { + if (extern_mode && !in_recursion) + { std::string m_name = stringf("$extern:%s", log_id(tpl)); - if (!design->module(m_name)) { + if (!design->module(m_name)) + { RTLIL::Module *m = design->addModule(m_name); tpl->cloneInto(m); @@ -926,14 +938,15 @@ struct TechmapWorker { log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name)); cell->type = m_name; cell->parameters.clear(); - } else { + } + else + { auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); log("%s\n", msg.c_str()); } - log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), - log_id(cell->type), log_id(tpl)); + log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); techmap_module_worker(design, module, cell, tpl); cell = nullptr; } @@ -959,7 +972,7 @@ struct TechmapWorker { }; struct TechmapPass : public Pass { - TechmapPass() : Pass("techmap", "generic technology mapper") {} + TechmapPass() : Pass("techmap", "generic technology mapper") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -1140,19 +1153,19 @@ struct TechmapPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-map" && argidx + 1 < args.size()) { + if (args[argidx] == "-map" && argidx+1 < args.size()) { map_files.push_back(args[++argidx]); continue; } - if (args[argidx] == "-max_iter" && argidx + 1 < args.size()) { + if (args[argidx] == "-max_iter" && argidx+1 < args.size()) { max_iter = atoi(args[++argidx].c_str()); continue; } - if (args[argidx] == "-D" && argidx + 1 < args.size()) { + if (args[argidx] == "-D" && argidx+1 < args.size()) { verilog_frontend += " -D " + args[++argidx]; continue; } - if (args[argidx] == "-I" && argidx + 1 < args.size()) { + if (args[argidx] == "-I" && argidx+1 < args.size()) { verilog_frontend += " -I " + args[++argidx]; continue; } @@ -1188,15 +1201,13 @@ struct TechmapPass : public Pass { if (fn.compare(0, 1, "%") == 0) { if (!saved_designs.count(fn.substr(1))) { delete map; - log_cmd_error("Can't open saved design `%s'.\n", fn.c_str() + 1); + log_cmd_error("Can't open saved design `%s'.\n", fn.c_str()+1); } for (auto mod : saved_designs.at(fn.substr(1))->modules()) if (!map->module(mod->name)) map->add(mod->clone()); } else { - Frontend::frontend_call( - map, nullptr, fn, - (fn.size() > 3 && fn.compare(fn.size() - 3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend)); + Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend)); } } @@ -1222,15 +1233,15 @@ struct TechmapPass : public Pass { if (epos == std::string::npos) log_error("Malformed techmap_celltype pattern %s\n", q); for (size_t i = pos + 1; i < epos; i++) { - queue.push_back(name.substr(0, pos) + name[i] + - name.substr(epos + 1, std::string::npos)); + queue.push_back(name.substr(0, pos) + name[i] + name.substr(epos + 1, std::string::npos)); } } } } free(p); } else { - IdString module_name = module->name.begins_with("\\$") ? module->name.substr(1) : module->name.str(); + IdString module_name = module->name.begins_with("\\$") ? + module->name.substr(1) : module->name.str(); celltypeMap[module_name].insert(module->name); } } @@ -1247,13 +1258,14 @@ struct TechmapPass : public Pass { for (auto module : design->modules()) worker.module_queue.insert(module); - while (!worker.module_queue.empty()) { + while (!worker.module_queue.empty()) + { RTLIL::Module *module = *worker.module_queue.begin(); worker.module_queue.erase(module); int module_max_iter = max_iter; bool did_something = true; - pool handled_cells; + pool handled_cells; while (did_something) { did_something = false; if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false)) From 1bbc12f389a131e8af65dece57ba25d8c96b77d0 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Fri, 29 Sep 2023 15:17:42 -0700 Subject: [PATCH 056/240] Revert changes to techmap.cc. --- passes/techmap/techmap.cc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 23d0d93fc57..144f596c88c 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -156,6 +156,8 @@ struct TechmapWorker } std::string orig_cell_name; + pool extra_src_attrs = cell->get_strpool_attribute(ID::src); + orig_cell_name = cell->name.str(); for (auto tpl_cell : tpl->cells()) if (tpl_cell->name.ends_with("_TECHMAP_REPLACE_")) { @@ -170,7 +172,7 @@ struct TechmapWorker apply_prefix(cell->name, m_name); RTLIL::Memory *m = module->addMemory(m_name, it.second); if (m->attributes.count(ID::src)) - m->attributes[ID::src] = cell->attributes[ID::src]; + m->add_strpool_attribute(ID::src, extra_src_attrs); memory_renames[it.first] = m->name; design->select(module, m); } @@ -215,7 +217,7 @@ struct TechmapWorker if (tpl_w->get_bool_attribute(ID::_techmap_special_)) w->attributes.clear(); if (w->attributes.count(ID::src)) - w->attributes[ID::src] = cell->attributes[ID::src]; + w->add_strpool_attribute(ID::src, extra_src_attrs); } design->select(module, w); @@ -373,7 +375,7 @@ struct TechmapWorker } if (c->attributes.count(ID::src)) - c->attributes[ID::src] = cell->attributes[ID::src]; + c->add_strpool_attribute(ID::src, extra_src_attrs); if (techmap_replace_cell) { for (auto attr : cell->attributes) From bce984fa60fed1b46a95383d0737eb620fb0c340 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Mon, 2 Oct 2023 15:57:18 -0700 Subject: [PATCH 057/240] Speed up OptMergePass by 1.7x. The main speedup comes from swithing from using a SHA1 hash to std::hash. There is no need to use an expensive cryptographic hash for fingerprinting in this context. --- kernel/celltypes.h | 10 +++++----- kernel/rtlil.h | 6 +++++- passes/opt/opt_merge.cc | 11 +++++------ 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/kernel/celltypes.h b/kernel/celltypes.h index cad505d9afd..58c6907dc63 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -56,7 +56,7 @@ struct CellTypes setup_stdcells_mem(); } - void setup_type(RTLIL::IdString type, const pool &inputs, const pool &outputs, bool is_evaluable = false) + void setup_type(const RTLIL::IdString& type, const pool &inputs, const pool &outputs, bool is_evaluable = false) { CellType ct = {type, inputs, outputs, is_evaluable}; cell_types[ct.type] = ct; @@ -298,24 +298,24 @@ struct CellTypes cell_types.clear(); } - bool cell_known(RTLIL::IdString type) const + bool cell_known(const RTLIL::IdString& type) const { return cell_types.count(type) != 0; } - bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const + bool cell_output(const RTLIL::IdString& type, const RTLIL::IdString& port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.outputs.count(port) != 0; } - bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const + bool cell_input(const RTLIL::IdString& type, const RTLIL::IdString& port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.inputs.count(port) != 0; } - bool cell_evaluable(RTLIL::IdString type) const + bool cell_evaluable(const RTLIL::IdString& type) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.is_evaluable; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index c50d75e9087..f53d9df8c84 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -308,10 +308,14 @@ namespace RTLIL bool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; } char operator[](size_t i) const { - const char *p = c_str(); + const char *p = c_str(); +#ifndef NDEBUG for (; i != 0; i--, p++) log_assert(*p != 0); return *p; +#else + return *(p + i); +#endif } std::string substr(size_t pos = 0, size_t len = std::string::npos) const { diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index e9d98cd4304..4bcd5a18947 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -41,7 +41,7 @@ struct OptMergeWorker CellTypes ct; int total_count; - SHA1 checksum; + using FingerPrint = std::hash::result_type; static void sort_pmux_conn(dict &conn) { @@ -78,7 +78,7 @@ struct OptMergeWorker return str; } - std::string hash_cell_parameters_and_connections(const RTLIL::Cell *cell) + FingerPrint hash_cell_parameters_and_connections(const RTLIL::Cell *cell) { vector hash_conn_strings; std::string hash_string = cell->type.str() + "\n"; @@ -149,8 +149,7 @@ struct OptMergeWorker for (auto it : hash_conn_strings) hash_string += it; - checksum.update(hash_string); - return checksum.final(); + return std::hash{}(hash_string); } bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) @@ -268,13 +267,13 @@ struct OptMergeWorker } did_something = false; - dict sharemap; + std::unordered_map sharemap; for (auto cell : cells) { if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known()) continue; - auto hash = hash_cell_parameters_and_connections(cell); + FingerPrint hash = hash_cell_parameters_and_connections(cell); auto r = sharemap.insert(std::make_pair(hash, cell)); if (!r.second) { if (compare_cell_parameters_and_connections(cell, r.first->second)) { From 058973faee14b822d4b68444b0cc09eea099f6f1 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Mon, 2 Oct 2023 16:15:47 -0700 Subject: [PATCH 058/240] Undo formatting change. --- kernel/rtlil.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f53d9df8c84..ef33ab2d728 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -308,7 +308,7 @@ namespace RTLIL bool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; } char operator[](size_t i) const { - const char *p = c_str(); + const char *p = c_str(); #ifndef NDEBUG for (; i != 0; i--, p++) log_assert(*p != 0); From 11ffd7df40260f782c82b43be190a48ec88214a1 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 3 Oct 2023 00:15:18 +0000 Subject: [PATCH 059/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a96f3f54919..ce76fda9ac2 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.33+79 +YOSYS_VER := 0.33+103 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 4968229efc2918365b2da0493fd33b6c57f09380 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Mon, 2 Oct 2023 11:00:00 -0700 Subject: [PATCH 060/240] Speed up stringf / vstringf by 1.8x. The main speedup is accomplished by avoiding a heap allocation in the common case where the final string length is less than 128. Inlining stringf & vstringf adds an additional improvement. --- kernel/yosys.cc | 46 +++--------------------------------- kernel/yosys.h | 63 +++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 64 insertions(+), 45 deletions(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index bd8dded4b5f..82f1a9dd9f7 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -74,6 +74,7 @@ #include #include "libs/json11/json11.hpp" +#include "devtools/build/runtime/get_runfiles_dir.h" YOSYS_NAMESPACE_BEGIN @@ -175,48 +176,6 @@ int ceil_log2(int x) #endif } -std::string stringf(const char *fmt, ...) -{ - std::string string; - va_list ap; - - va_start(ap, fmt); - string = vstringf(fmt, ap); - va_end(ap); - - return string; -} - -std::string vstringf(const char *fmt, va_list ap) -{ - std::string string; - char *str = NULL; - -#if defined(_WIN32 )|| defined(__CYGWIN__) - int sz = 64, rc; - while (1) { - va_list apc; - va_copy(apc, ap); - str = (char*)realloc(str, sz); - rc = vsnprintf(str, sz, fmt, apc); - va_end(apc); - if (rc >= 0 && rc < sz) - break; - sz *= 2; - } -#else - if (vasprintf(&str, fmt, ap) < 0) - str = NULL; -#endif - - if (str != NULL) { - string = str; - free(str); - } - - return string; -} - int readsome(std::istream &f, char *s, int n) { int rc = int(f.readsome(s, n)); @@ -1025,7 +984,8 @@ void init_share_dirname() return; } # ifdef YOSYS_DATDIR - proc_share_path = YOSYS_DATDIR "/"; + proc_share_path = devtools_build::GetRunfilesDir() + "/"; + proc_share_path += YOSYS_DATDIR "/"; if (check_file_exists(proc_share_path, true)) { yosys_share_dirname = proc_share_path; return; diff --git a/kernel/yosys.h b/kernel/yosys.h index 29415ff842e..57deb72365e 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -272,8 +272,62 @@ inline void memhasher() { if (memhasher_active) memhasher_do(); } void yosys_banner(); int ceil_log2(int x) YS_ATTRIBUTE(const); -std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2)); -std::string vstringf(const char *fmt, va_list ap); + +inline std::string vstringf(const char *fmt, va_list ap) +{ + // For the common case of strings shorter than 128 (including the trailing + // '\0'), save a heap allocation by using a stack allocated buffer. + const int kBufSize = 128; + char buf[kBufSize]; + buf[0] = '\0'; + va_list apc; + va_copy(apc, ap); + int n = vsnprintf(buf, kBufSize, fmt, apc); + va_end(apc); + if (n < kBufSize) + return std::string(buf); + + std::string string; + char *str = NULL; +#if defined(_WIN32 )|| defined(__CYGWIN__) + int sz = 2 * kBufSize, rc; + while (1) { + va_copy(apc, ap); + str = (char*)realloc(str, sz); + rc = vsnprintf(str, sz, fmt, apc); + va_end(apc); + if (rc >= 0 && rc < sz) + break; + sz *= 2; + } + if (str != NULL) { + string = str; + free(str); + } + return string; +#else + if (vasprintf(&str, fmt, ap) < 0) + str = NULL; + if (str != NULL) { + string = str; + free(str); + } + return string; +#endif +} + +inline std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2)) +{ + std::string string; + va_list ap; + + va_start(ap, fmt); + string = vstringf(fmt, ap); + va_end(ap); + + return string; +} + int readsome(std::istream &f, char *s, int n); std::string next_token(std::string &text, const char *sep = " \t\r\n", bool long_strings = false); std::vector split_tokens(const std::string &text, const char *sep = " \t\r\n"); @@ -289,6 +343,11 @@ bool is_absolute_path(std::string filename); void remove_directory(std::string dirname); std::string escape_filename_spaces(const std::string& filename); +using ys_size_type = int64_t; // Large enough to deal with large number of data, but also not experiencing unsigned overflow. + +// TODO(hzeller): these need to return ys_size_type, but in the course of +// refactoring, each type will be handled separately (and gets their own GetSize() function). After all +// size types are converted, this template can be changed to return ys_size_type. template int GetSize(const T &obj) { return obj.size(); } inline int GetSize(RTLIL::Wire *wire); From ff915d21b67b2746573372568c51e5737b356083 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Mon, 2 Oct 2023 11:05:04 -0700 Subject: [PATCH 061/240] Update comment. --- kernel/yosys.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/yosys.h b/kernel/yosys.h index 57deb72365e..5ee5eb75f30 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -275,8 +275,8 @@ int ceil_log2(int x) YS_ATTRIBUTE(const); inline std::string vstringf(const char *fmt, va_list ap) { - // For the common case of strings shorter than 128 (including the trailing - // '\0'), save a heap allocation by using a stack allocated buffer. + // For the common case of strings shorter than 128, save a heap + // allocation by using a stack allocated buffer. const int kBufSize = 128; char buf[kBufSize]; buf[0] = '\0'; From cb9f318d37bdb557b7111914e8c25b3ed505ac3d Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Mon, 2 Oct 2023 11:07:28 -0700 Subject: [PATCH 062/240] Remove local modifications. --- kernel/yosys.cc | 4 +--- kernel/yosys.h | 5 ----- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 82f1a9dd9f7..559ce872cad 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -74,7 +74,6 @@ #include #include "libs/json11/json11.hpp" -#include "devtools/build/runtime/get_runfiles_dir.h" YOSYS_NAMESPACE_BEGIN @@ -984,8 +983,7 @@ void init_share_dirname() return; } # ifdef YOSYS_DATDIR - proc_share_path = devtools_build::GetRunfilesDir() + "/"; - proc_share_path += YOSYS_DATDIR "/"; + proc_share_path = YOSYS_DATDIR "/"; if (check_file_exists(proc_share_path, true)) { yosys_share_dirname = proc_share_path; return; diff --git a/kernel/yosys.h b/kernel/yosys.h index 5ee5eb75f30..99edfb70036 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -343,11 +343,6 @@ bool is_absolute_path(std::string filename); void remove_directory(std::string dirname); std::string escape_filename_spaces(const std::string& filename); -using ys_size_type = int64_t; // Large enough to deal with large number of data, but also not experiencing unsigned overflow. - -// TODO(hzeller): these need to return ys_size_type, but in the course of -// refactoring, each type will be handled separately (and gets their own GetSize() function). After all -// size types are converted, this template can be changed to return ys_size_type. template int GetSize(const T &obj) { return obj.size(); } inline int GetSize(RTLIL::Wire *wire); From a6247cba42d126fe429dba37c62145b24ac8f500 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Mon, 2 Oct 2023 11:24:53 -0700 Subject: [PATCH 063/240] Fix compiler warnings from GCC. --- kernel/yosys.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/kernel/yosys.h b/kernel/yosys.h index 99edfb70036..97a79861e15 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -316,7 +316,9 @@ inline std::string vstringf(const char *fmt, va_list ap) #endif } -inline std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2)) +std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2)); + +inline std::string stringf(const char *fmt, ...) { std::string string; va_list ap; From c1745970147bb17d65943297c8b9369cacec2bd3 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 3 Oct 2023 11:46:43 +0200 Subject: [PATCH 064/240] Fix sva_value_change_changed test for updated verific --- tests/sva/sva_value_change_changed.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/sva/sva_value_change_changed.sv b/tests/sva/sva_value_change_changed.sv index 8f3a05a2f2e..3ce2078500c 100644 --- a/tests/sva/sva_value_change_changed.sv +++ b/tests/sva/sva_value_change_changed.sv @@ -8,9 +8,11 @@ module top ( $changed(b) ); + wire x = 'x; + `ifndef FAIL assume property ( - b !== 'x ##1 $changed(b) + b !== x ##1 $changed(b) ); `endif From 563a56d9ff07cadd93b8b64977d1b8b83f94170d Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 3 Oct 2023 15:52:01 +0200 Subject: [PATCH 065/240] verific: Improve interaction between -L, -work and bind statements --- frontends/verific/verific.cc | 40 +++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 310e3918015..9138bb63c03 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3063,6 +3063,7 @@ struct VerificPass : public Pass { int argidx = 1; std::string work = "work"; bool is_work_set = false; + (void)is_work_set; veri_file::RegisterCallBackVerificStream(&verific_read_cb); if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" || @@ -3140,7 +3141,20 @@ struct VerificPass : public Pass { } veri_file::RemoveAllLOptions(); - veri_file::AddLOption("work"); + for (int i = argidx; i < GetSize(args); i++) + { + if (args[i] == "-work" && i+1 < GetSize(args)) { + work = args[++i]; + is_work_set = true; + continue; + } + if (args[i] == "-L" && i+1 < GetSize(args)) { + ++i; + continue; + } + break; + } + veri_file::AddLOption(work.c_str()); for (int i = argidx; i < GetSize(args); i++) { if (args[i] == "-work" && i+1 < GetSize(args)) { @@ -3148,7 +3162,7 @@ struct VerificPass : public Pass { continue; } if (args[i] == "-L" && i+1 < GetSize(args)) { - if (args[++i] == "work") + if (args[++i] == work) veri_file::RemoveAllLOptions(); continue; } @@ -3641,7 +3655,7 @@ struct VerificPass : public Pass { if (module_name && module_name->IsHierName()) { VeriName *prefix = module_name->GetPrefix() ; const char *lib_name = (prefix) ? prefix->GetName() : 0 ; - if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; + if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ; } if (lib && module_name) top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName()); @@ -3663,13 +3677,19 @@ struct VerificPass : public Pass { log_error("Can't find module/unit '%s'.\n", name); } - if (veri_lib) { - // Also elaborate all root modules since they may contain bind statements - MapIter mi; - VeriModule *veri_module; - FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { - if (!veri_module->IsRootModule()) continue; - veri_modules.InsertLast(veri_module); + + const char *lib_name = nullptr; + SetIter si; + FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) { + VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0); + if (veri_lib) { + // Also elaborate all root modules since they may contain bind statements + MapIter mi; + VeriModule *veri_module; + FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { + if (!veri_module->IsRootModule()) continue; + veri_modules.InsertLast(veri_module); + } } } From 7b454d4633c12dd7ee55f52911116524a3a6da41 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Tue, 3 Oct 2023 14:06:41 -0700 Subject: [PATCH 066/240] Revert changes to celltypes.h. --- kernel/celltypes.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 58c6907dc63..cad505d9afd 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -56,7 +56,7 @@ struct CellTypes setup_stdcells_mem(); } - void setup_type(const RTLIL::IdString& type, const pool &inputs, const pool &outputs, bool is_evaluable = false) + void setup_type(RTLIL::IdString type, const pool &inputs, const pool &outputs, bool is_evaluable = false) { CellType ct = {type, inputs, outputs, is_evaluable}; cell_types[ct.type] = ct; @@ -298,24 +298,24 @@ struct CellTypes cell_types.clear(); } - bool cell_known(const RTLIL::IdString& type) const + bool cell_known(RTLIL::IdString type) const { return cell_types.count(type) != 0; } - bool cell_output(const RTLIL::IdString& type, const RTLIL::IdString& port) const + bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.outputs.count(port) != 0; } - bool cell_input(const RTLIL::IdString& type, const RTLIL::IdString& port) const + bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.inputs.count(port) != 0; } - bool cell_evaluable(const RTLIL::IdString& type) const + bool cell_evaluable(RTLIL::IdString type) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.is_evaluable; From 8e0308b5e7b0c0bbe10c072123d2e7b945f4b6b0 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Tue, 3 Oct 2023 14:25:59 -0700 Subject: [PATCH 067/240] Revert changes to celltypes.h. Use dict instead of std::unordered_map and most hash function for uint64_t to hashlib.h to support this. --- kernel/hashlib.h | 6 ++++++ passes/opt/opt_merge.cc | 2 +- passes/sat/recover_names.cc | 9 +-------- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index be759fdf0a4..9cf43da6ca5 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -90,6 +90,12 @@ template<> struct hash_ops : hash_int_ops return a; } }; +template<> struct hash_ops : hash_int_ops +{ + static inline unsigned int hash(uint64_t a) { + return mkhash((unsigned int)(a), (unsigned int)(a >> 32)); + } +}; template<> struct hash_ops { static inline bool cmp(const std::string &a, const std::string &b) { diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 4bcd5a18947..87ad01f00ec 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -267,7 +267,7 @@ struct OptMergeWorker } did_something = false; - std::unordered_map sharemap; + dict sharemap; for (auto cell : cells) { if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known()) diff --git a/passes/sat/recover_names.cc b/passes/sat/recover_names.cc index 2d7e7f01cfa..4c30a363202 100644 --- a/passes/sat/recover_names.cc +++ b/passes/sat/recover_names.cc @@ -29,13 +29,6 @@ USING_YOSYS_NAMESPACE -template<> struct hashlib::hash_ops : hashlib::hash_int_ops -{ - static inline unsigned int hash(uint64_t a) { - return mkhash((unsigned int)(a), (unsigned int)(a >> 32)); - } -}; - PRIVATE_NAMESPACE_BEGIN // xorshift128 params @@ -453,7 +446,7 @@ struct RecoverNamesWorker { pool comb_whiteboxes, buffer_types; // class -> (gold, (gate, inverted)) - dict, dict>> cls2bits; + dict, dict>> cls2bits; void analyse_boxes() { From 57a2b4b0cd542f2053616bbc8ece614a28d72f3a Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Tue, 3 Oct 2023 15:02:02 -0700 Subject: [PATCH 068/240] Explicitly use uint64_t as the type of fingerprint to avoid type mismatch with some compilers. --- passes/opt/opt_merge.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 87ad01f00ec..248ba80913b 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -41,7 +41,6 @@ struct OptMergeWorker CellTypes ct; int total_count; - using FingerPrint = std::hash::result_type; static void sort_pmux_conn(dict &conn) { @@ -78,7 +77,7 @@ struct OptMergeWorker return str; } - FingerPrint hash_cell_parameters_and_connections(const RTLIL::Cell *cell) + uint64_t hash_cell_parameters_and_connections(const RTLIL::Cell *cell) { vector hash_conn_strings; std::string hash_string = cell->type.str() + "\n"; @@ -267,13 +266,13 @@ struct OptMergeWorker } did_something = false; - dict sharemap; + dict sharemap; for (auto cell : cells) { if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known()) continue; - FingerPrint hash = hash_cell_parameters_and_connections(cell); + uint64_t hash = hash_cell_parameters_and_connections(cell); auto r = sharemap.insert(std::make_pair(hash, cell)); if (!r.second) { if (compare_cell_parameters_and_connections(cell, r.first->second)) { From 294844137bb1fd8854a18cc2a0c703aa30726761 Mon Sep 17 00:00:00 2001 From: Lofty Date: Tue, 3 Oct 2023 10:32:18 +0100 Subject: [PATCH 069/240] gowin: fix abc9 attributes and specify blocks --- techlibs/gowin/cells_sim.v | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 86bd677e229..b268690803f 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -197,7 +197,7 @@ module DFFE (output reg Q, input D, CLK, CE); end endmodule // DFFE (positive clock edge; clock enable) -(* abc9_box, lib_whitebox *) +(* abc9_flop, lib_whitebox *) module DFFS (output reg Q, input D, CLK, SET); parameter [0:0] INIT = 1'b1; initial Q = INIT; @@ -216,7 +216,7 @@ module DFFS (output reg Q, input D, CLK, SET); end endmodule // DFFS (positive clock edge; synchronous set) -(* abc9_box, lib_whitebox *) +(* abc9_flop, lib_whitebox *) module DFFSE (output reg Q, input D, CLK, CE, SET); parameter [0:0] INIT = 1'b1; initial Q = INIT; @@ -282,7 +282,7 @@ module DFFP (output reg Q, input D, CLK, PRESET); specify (posedge CLK => (Q : D)) = (480, 660); - (posedge PRESET => (Q : 1'b1)) = (1800, 2679); + (PRESET => Q) = (1800, 2679); $setup(D, posedge CLK, 576); endspecify @@ -301,7 +301,7 @@ module DFFPE (output reg Q, input D, CLK, CE, PRESET); specify if (CE) (posedge CLK => (Q : D)) = (480, 660); - (posedge PRESET => (Q : 1'b1)) = (1800, 2679); + (PRESET => Q) = (1800, 2679); $setup(D, posedge CLK &&& CE, 576); $setup(CE, posedge CLK, 63); endspecify @@ -321,7 +321,7 @@ module DFFC (output reg Q, input D, CLK, CLEAR); specify (posedge CLK => (Q : D)) = (480, 660); - (posedge CLEAR => (Q : 1'b0)) = (1800, 2679); + (CLEAR => Q) = (1800, 2679); $setup(D, posedge CLK, 576); endspecify @@ -340,7 +340,7 @@ module DFFCE (output reg Q, input D, CLK, CE, CLEAR); specify if (CE) (posedge CLK => (Q : D)) = (480, 660); - (posedge CLEAR => (Q : 1'b0)) = (1800, 2679); + (CLEAR => Q) = (1800, 2679); $setup(D, posedge CLK &&& CE, 576); $setup(CE, posedge CLK, 63); endspecify @@ -384,7 +384,7 @@ module DFFNE (output reg Q, input D, CLK, CE); end endmodule // DFFNE (negative clock edge; clock enable) -(* abc9_box, lib_whitebox *) +(* abc9_flop, lib_whitebox *) module DFFNS (output reg Q, input D, CLK, SET); parameter [0:0] INIT = 1'b1; initial Q = INIT; @@ -403,7 +403,7 @@ module DFFNS (output reg Q, input D, CLK, SET); end endmodule // DFFNS (negative clock edge; synchronous set) -(* abc9_box, lib_whitebox *) +(* abc9_flop, lib_whitebox *) module DFFNSE (output reg Q, input D, CLK, CE, SET); parameter [0:0] INIT = 1'b1; initial Q = INIT; @@ -469,7 +469,7 @@ module DFFNP (output reg Q, input D, CLK, PRESET); specify (negedge CLK => (Q : D)) = (480, 660); - (posedge PRESET => (Q : 1'b1)) = (1800, 2679); + (PRESET => Q) = (1800, 2679); $setup(D, negedge CLK, 576); endspecify @@ -488,7 +488,7 @@ module DFFNPE (output reg Q, input D, CLK, CE, PRESET); specify if (CE) (negedge CLK => (Q : D)) = (480, 660); - (posedge PRESET => (Q : 1'b1)) = (1800, 2679); + (PRESET => Q) = (1800, 2679); $setup(D, negedge CLK &&& CE, 576); $setup(CE, negedge CLK, 63); endspecify @@ -508,7 +508,7 @@ module DFFNC (output reg Q, input D, CLK, CLEAR); specify (negedge CLK => (Q : D)) = (480, 660); - (posedge CLEAR => (Q : 1'b0)) = (1800, 2679); + (CLEAR => Q) = (1800, 2679); $setup(D, negedge CLK, 576); endspecify @@ -527,7 +527,7 @@ module DFFNCE (output reg Q, input D, CLK, CE, CLEAR); specify if (CE) (negedge CLK => (Q : D)) = (480, 660); - (posedge CLEAR => (Q : 1'b0)) = (1800, 2679); + (CLEAR => Q) = (1800, 2679); $setup(D, negedge CLK &&& CE, 576); $setup(CE, negedge CLK, 63); endspecify @@ -957,7 +957,7 @@ end endmodule - +(* abc9_flop, lib_whitebox *) module RAM16S1 (DO, DI, AD, WRE, CLK); parameter INIT_0 = 16'h0000; @@ -992,7 +992,7 @@ end endmodule - +(* abc9_flop, lib_whitebox *) module RAM16S2 (DO, DI, AD, WRE, CLK); parameter INIT_0 = 16'h0000; @@ -1031,7 +1031,7 @@ end endmodule - +(* abc9_flop, lib_whitebox *) module RAM16S4 (DO, DI, AD, WRE, CLK); parameter INIT_0 = 16'h0000; From f00d6f3c12071c741abe6248ff03a026f6509dae Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 4 Oct 2023 00:15:12 +0000 Subject: [PATCH 070/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index ce76fda9ac2..92b0a5d2e4e 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.33+103 +YOSYS_VER := 0.33+112 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 0434f9d3d1decc563877f73a3b963bc3d0cdef6a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 4 Oct 2023 23:21:40 +0200 Subject: [PATCH 071/240] booth: Fix vacancy check when summing down result In commit fedd12261 ("booth: Move away from explicit `Wire` pointers") a bug was introduced when checking for vacant slots in arrays holding some intermediate results. Non-wire SigBit values were taken to imply a vacant slot, but actually a constant one can make its way into those results, if the multiplier cell configuration is just right. Fix the vacancy check to address the bug. --- passes/techmap/booth.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 000dcff14ec..e1e6b360ab6 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -533,7 +533,7 @@ struct BoothPassWorker { // get the bits in this column. SigSpec column_bits; for (int row_ix = 0; row_ix < row_size; row_ix++) { - if (bits_to_reduce[row_ix][column_ix].wire) + if (bits_to_reduce[row_ix][column_ix] != State::S0) column_bits.append(bits_to_reduce[row_ix][column_ix]); } for (auto c : carry_bits_to_add_to_next_column) { @@ -750,7 +750,7 @@ struct BoothPassWorker { SigSpec first_csa_ips; // get the first 3 inputs, if possible for (var_ix = 0; var_ix < column_bits.size() && first_csa_ips.size() != 3; var_ix++) { - if (column_bits[var_ix].is_wire()) + if (column_bits[var_ix] != State::S0) first_csa_ips.append(column_bits[var_ix]); } @@ -782,7 +782,7 @@ struct BoothPassWorker { // get the next two variables to sum for (; var_ix <= column_bits.size() - 1 && csa_ips.size() < 2;) { // skip any empty bits - if (column_bits[var_ix].is_wire()) + if (column_bits[var_ix] != State::S0) csa_ips.append(column_bits[var_ix]); var_ix++; } From 4506e11d0fd1cd05a795203dc95a39f921c492b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 4 Oct 2023 23:29:40 +0200 Subject: [PATCH 072/240] booth: Extend test to catch bug from previous commit --- tests/techmap/booth.ys | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/tests/techmap/booth.ys b/tests/techmap/booth.ys index ab7efc7b7fd..55dfdb8e9cd 100644 --- a/tests/techmap/booth.ys +++ b/tests/techmap/booth.ys @@ -1 +1,15 @@ -test_cell -s 1694091355 -n 100 -script booth_map_script.ys_ $mul +read_verilog < Date: Thu, 5 Oct 2023 09:14:12 +0200 Subject: [PATCH 073/240] Release version 0.34 --- CHANGELOG | 19 ++++++++++++++++++- Makefile | 4 ++-- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index a662ba4dad3..60ad78b7265 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,13 +2,30 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.33 .. Yosys 0.34-dev +Yosys 0.33 .. Yosys 0.34 -------------------------- + * New commands and options + - Added option "-assert" to "sim" pass. + - Added option "-noinitstate" to "sim" pass. + - Added option "-dont_use" to "abc" pass. + - Added "dft_tag" pass to create tagging logic for data flow tracking. + - Added "future" pass to resolve future sampled value functions. + - Added "booth" pass to map $mul cells to Booth multipliers. + - Added option "-booth" to "synth" pass. * SystemVerilog - Added support for assignments within expressions, e.g., `x[y++] = z;` or `x = (y *= 2) - 1;`. + * Verific support + - "src" attribute contain full location info. + - module parameters are kept after import. + - accurate access order semantics in memory inference. + - better "bind" support for mixed language projects. + + * Various + - "show" command displays dot instead of box for wire aliases. + Yosys 0.32 .. Yosys 0.33 -------------------------- * Various diff --git a/Makefile b/Makefile index 92b0a5d2e4e..b9c10898150 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.33+112 +YOSYS_VER := 0.34 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -157,7 +157,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 2584903.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 2584903.. | wc -l`/;" Makefile # set 'ABCREV = default' to use abc/ as it is # From b88f7fc6e899ebed361b71efe12d095a8eeb61d2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 5 Oct 2023 09:16:05 +0200 Subject: [PATCH 074/240] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 60ad78b7265..ee5f6b43d25 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.34 .. Yosys 0.35-dev +-------------------------- + Yosys 0.33 .. Yosys 0.34 -------------------------- * New commands and options diff --git a/Makefile b/Makefile index b9c10898150..650e553c932 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.34 +YOSYS_VER := 0.34+0 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -157,7 +157,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: -# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 2584903.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 4a1b559.. | wc -l`/;" Makefile # set 'ABCREV = default' to use abc/ as it is # From 824fdaadf62fa58b81d268340a56bf847dc5724b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 5 Oct 2023 09:55:53 +0200 Subject: [PATCH 075/240] mingw build fix --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 650e553c932..688b5939ded 100644 --- a/Makefile +++ b/Makefile @@ -357,7 +357,7 @@ CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s LDLIBS := $(filter-out -lrt,$(LDLIBS)) ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" -ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)" +ABCMKARGS += LIBS="-lpthread -lshlwapi -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)" EXE = .exe else ifeq ($(CONFIG),msys2-64) @@ -368,7 +368,7 @@ CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s LDLIBS := $(filter-out -lrt,$(LDLIBS)) ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" -ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="x86_64-w64-mingw32-gcc" CXX="$(CXX)" +ABCMKARGS += LIBS="-lpthread -lshlwapi -s" ABC_USE_NO_READLINE=0 CC="x86_64-w64-mingw32-gcc" CXX="$(CXX)" EXE = .exe else ifneq ($(CONFIG),none) From 268fe92d22536525b3c88b1dc14fff2e4a319294 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 5 Oct 2023 11:22:40 +0200 Subject: [PATCH 076/240] verific: save original module name --- frontends/verific/verific.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9138bb63c03..85a685376ef 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1275,6 +1275,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma log("Importing module %s.\n", RTLIL::id2cstr(module->name)); } import_attributes(module->attributes, nl, nl); + module->set_string_attribute(ID::hdlname, nl->CellBaseName()); const char *param_name ; const char *param_value ; MapIter mi; From 23b9e61c477277b00cf34e593b8979f8f15a3600 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Thu, 5 Oct 2023 16:28:17 +0200 Subject: [PATCH 077/240] verific: Pass list of top modules to static elaboration --- frontends/verific/verific.cc | 139 ++++++++++++++++++++--------------- 1 file changed, 80 insertions(+), 59 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9138bb63c03..da449e2d718 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3595,15 +3595,16 @@ struct VerificPass : public Pass { std::set top_mod_names; + if (mode_all) + { + #ifdef YOSYSHQ_VERIFIC_EXTENSIONS - VerificExtensions::ElaborateAndRewrite(work, ¶meters); - verific_error_msg.clear(); + VerificExtensions::ElaborateAndRewrite(work, ¶meters); + verific_error_msg.clear(); #endif - if (!ppfile.empty()) - veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); + if (!ppfile.empty()) + veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); - if (mode_all) - { log("Running hier_tree::ElaborateAll().\n"); VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); @@ -3628,73 +3629,93 @@ struct VerificPass : public Pass { if (argidx == GetSize(args)) cmd_error(args, argidx, "No top module specified.\n"); - VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1); + Array *netlists = nullptr; + +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--) +#endif + { + + VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1); #ifdef VERIFIC_VHDL_SUPPORT - VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); + VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); #endif - Array veri_modules, vhdl_units; - for (; argidx < GetSize(args); argidx++) - { - const char *name = args[argidx].c_str(); - top_mod_names.insert(name); - - VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr; - if (veri_module) { - if (veri_module->IsConfiguration()) { - log("Adding Verilog configuration '%s' to elaboration queue.\n", name); - veri_modules.InsertLast(veri_module); - - top_mod_names.erase(name); - - VeriConfiguration *cfg = (VeriConfiguration*)veri_module; - VeriName *module_name; - int i; - FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) { - VeriLibrary *lib = veri_module->GetLibrary() ; - if (module_name && module_name->IsHierName()) { - VeriName *prefix = module_name->GetPrefix() ; - const char *lib_name = (prefix) ? prefix->GetName() : 0 ; - if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ; + Array veri_modules, vhdl_units; + for (int i = argidx; i < GetSize(args); i++) + { + const char *name = args[i].c_str(); + top_mod_names.insert(name); + + VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr; + if (veri_module) { + if (veri_module->IsConfiguration()) { + log("Adding Verilog configuration '%s' to elaboration queue.\n", name); + veri_modules.InsertLast(veri_module); + + top_mod_names.erase(name); + + VeriConfiguration *cfg = (VeriConfiguration*)veri_module; + VeriName *module_name; + int i; + FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) { + VeriLibrary *lib = veri_module->GetLibrary() ; + if (module_name && module_name->IsHierName()) { + VeriName *prefix = module_name->GetPrefix() ; + const char *lib_name = (prefix) ? prefix->GetName() : 0 ; + if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ; + } + if (lib && module_name) + top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName()); } - if (lib && module_name) - top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName()); + } else { + log("Adding Verilog module '%s' to elaboration queue.\n", name); + veri_modules.InsertLast(veri_module); } - } else { - log("Adding Verilog module '%s' to elaboration queue.\n", name); - veri_modules.InsertLast(veri_module); + continue; } - continue; - } #ifdef VERIFIC_VHDL_SUPPORT - VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr; - if (vhdl_unit) { - log("Adding VHDL unit '%s' to elaboration queue.\n", name); - vhdl_units.InsertLast(vhdl_unit); - continue; - } + VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr; + if (vhdl_unit) { + log("Adding VHDL unit '%s' to elaboration queue.\n", name); + vhdl_units.InsertLast(vhdl_unit); + continue; + } #endif - log_error("Can't find module/unit '%s'.\n", name); - } + log_error("Can't find module/unit '%s'.\n", name); + } +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + if (static_elaborate) { + VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, ¶meters); + verific_error_msg.clear(); +#endif + if (!ppfile.empty()) + veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); - const char *lib_name = nullptr; - SetIter si; - FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) { - VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0); - if (veri_lib) { - // Also elaborate all root modules since they may contain bind statements - MapIter mi; - VeriModule *veri_module; - FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { - if (!veri_module->IsRootModule()) continue; - veri_modules.InsertLast(veri_module); +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + continue; + } +#endif + const char *lib_name = nullptr; + SetIter si; + FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) { + VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0); + if (veri_lib) { + // Also elaborate all root modules since they may contain bind statements + MapIter mi; + VeriModule *veri_module; + FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { + if (!veri_module->IsRootModule()) continue; + veri_modules.InsertLast(veri_module); + } } } + + log("Running hier_tree::Elaborate().\n"); + netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, ¶meters); } - log("Running hier_tree::Elaborate().\n"); - Array *netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, ¶meters); Netlist *nl; int i; From 47a4b790f8162451d91cf8a04f23f2893e0a3824 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Thu, 5 Oct 2023 16:40:43 +0200 Subject: [PATCH 078/240] verific: Pass top modules to static elaboration when using hierarchy --- frontends/verific/verific.cc | 86 ++++++++++++++++++++++-------------- 1 file changed, 53 insertions(+), 33 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index da449e2d718..62307a45961 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2495,51 +2495,71 @@ std::string verific_import(Design *design, const std::mapGetModule(top.c_str(), 1); - if (veri_module) { - veri_modules.InsertLast(veri_module); - if (veri_module->IsConfiguration()) { - VeriConfiguration *cfg = (VeriConfiguration*)veri_module; - VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast(); - VeriLibrary *lib = veri_module->GetLibrary() ; - if (module_name && module_name->IsHierName()) { - VeriName *prefix = module_name->GetPrefix() ; - const char *lib_name = (prefix) ? prefix->GetName() : 0 ; - if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; + +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--) +#endif + { + Array veri_modules, vhdl_units; + + if (veri_lib) { + VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1); + if (veri_module) { + veri_modules.InsertLast(veri_module); + if (veri_module->IsConfiguration()) { + VeriConfiguration *cfg = (VeriConfiguration*)veri_module; + VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast(); + VeriLibrary *lib = veri_module->GetLibrary() ; + if (module_name && module_name->IsHierName()) { + VeriName *prefix = module_name->GetPrefix() ; + const char *lib_name = (prefix) ? prefix->GetName() : 0 ; + if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; + } + if (lib && module_name) + top = lib->GetModule(module_name->GetName(), 1)->GetName(); } - if (lib && module_name) - top = lib->GetModule(module_name->GetName(), 1)->GetName(); } - } - // Also elaborate all root modules since they may contain bind statements - MapIter mi; - FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { - if (!veri_module->IsRootModule()) continue; - veri_modules.InsertLast(veri_module); +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + if (!static_elaborate) +#endif + { + // Also elaborate all root modules since they may contain bind statements + MapIter mi; + FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { + if (!veri_module->IsRootModule()) continue; + veri_modules.InsertLast(veri_module); + } + } } - } #ifdef VERIFIC_VHDL_SUPPORT - if (vhdl_lib) { - VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str()); - if (vhdl_unit) - vhdl_units.InsertLast(vhdl_unit); - } + if (vhdl_lib) { + VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str()); + if (vhdl_unit) + vhdl_units.InsertLast(vhdl_unit); + } #endif - netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params); + +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + if (static_elaborate) { + VerificExtensions::ElaborateAndRewrite("work", &veri_modules, &vhdl_units, &verific_params); + verific_error_msg.clear(); + continue; + } +#endif + + netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params); + } } Netlist *nl; From 6ac43e49bc7db6a6c13b0ff302ef193db1fa7064 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 5 Oct 2023 19:21:52 +0200 Subject: [PATCH 079/240] sim: Change clocked read port suggestion to `memory_nordff` `memory_nordff` has the advantage that it can be called just ahead of the simulation step no matter whether the clocked read port has been inferred or was explicitly instantiated in a flow. --- passes/sat/sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 963c6481b16..31490591474 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -579,7 +579,7 @@ struct SimInstance Const data = Const(State::Sx, mem.width << port.wide_log2); if (port.clk_enable) - log_error("Memory %s.%s has clocked read ports. Run 'memory' with -nordff.\n", log_id(module), log_id(mem.memid)); + log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", log_id(module), log_id(mem.memid)); if (addr.is_fully_def()) { int addr_int = addr.as_int(); From a782b15aae8890c819c133566f77dc5ac8362b99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 5 Oct 2023 19:22:08 +0200 Subject: [PATCH 080/240] sim: s/instanced/instantiated/ --- passes/sat/sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 31490591474..9ce79973599 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -219,7 +219,7 @@ struct SimInstance log_assert(module); if (module->get_blackbox_attribute(true)) - log_error("Cannot simulate blackbox module %s (instanced at %s).\n", + log_error("Cannot simulate blackbox module %s (instantiated at %s).\n", log_id(module->name), hiername().c_str()); if (parent) { From c3fd88624a53c3778ea8ec1a43fc68d0686143ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 5 Oct 2023 19:23:48 +0200 Subject: [PATCH 081/240] sim: Bail on processes Instead of silently missimulating, error out when there are processes found in the simulation hierarchy. --- passes/sat/sim.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 9ce79973599..a8516470cfe 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -222,6 +222,10 @@ struct SimInstance log_error("Cannot simulate blackbox module %s (instantiated at %s).\n", log_id(module->name), hiername().c_str()); + if (module->has_processes()) + log_error("Found processes in simulation hierarchy (in module %s at %s). Run 'proc' first.\n", + log_id(module), hiername().c_str()); + if (parent) { log_assert(parent->children.count(instance) == 0); parent->children[instance] = this; From e38c9e01c901e0f5d0eb9fe18981a2c5c95ddf61 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Thu, 5 Oct 2023 15:24:26 -0700 Subject: [PATCH 082/240] Undo formatting changes in kernel/utils.h. --- kernel/utils.h | 42 ++++++++++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/kernel/utils.h b/kernel/utils.h index 4679a23f2b9..9b64ed8e114 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -31,30 +31,34 @@ YOSYS_NAMESPACE_BEGIN // A map-like container, but you can save and restore the state // ------------------------------------------------ -template > struct stackmap { - private: - std::vector> backup_state; +template> +struct stackmap +{ +private: + std::vector> backup_state; dict current_state; static T empty_tuple; - public: - stackmap() {} - stackmap(const dict &other) : current_state(other) {} +public: + stackmap() { } + stackmap(const dict &other) : current_state(other) { } - template stackmap &operator=(const Other &other) + template + void operator=(const Other &other) { - for (const auto &it : current_state) + for (auto &it : current_state) if (!backup_state.empty() && backup_state.back().count(it.first) == 0) backup_state.back()[it.first] = new T(it.second); current_state.clear(); - for (const auto &it : other) + for (auto &it : other) set(it.first, it.second); - - return *this; } - bool has(const Key &k) { return current_state.count(k) != 0; } + bool has(const Key &k) + { + return current_state.count(k) != 0; + } void set(const Key &k, const T &v) { @@ -79,7 +83,7 @@ template > struct stackma void reset(const Key &k) { - for (int i = GetSize(backup_state) - 1; i >= 0; i--) + for (int i = GetSize(backup_state)-1; i >= 0; i--) if (backup_state[i].count(k) != 0) { if (backup_state[i].at(k) == nullptr) current_state.erase(k); @@ -90,14 +94,20 @@ template > struct stackma current_state.erase(k); } - const dict &stdmap() { return current_state; } + const dict &stdmap() + { + return current_state; + } - void save() { backup_state.resize(backup_state.size() + 1); } + void save() + { + backup_state.resize(backup_state.size()+1); + } void restore() { log_assert(!backup_state.empty()); - for (const auto &it : backup_state.back()) + for (auto &it : backup_state.back()) if (it.second != nullptr) { current_state[it.first] = *it.second; delete it.second; From fd7bd420b3d9f1b031adced3add1f15f29048906 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Thu, 5 Oct 2023 15:26:29 -0700 Subject: [PATCH 083/240] Add back newline. --- kernel/utils.h | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/utils.h b/kernel/utils.h index 9b64ed8e114..255f875c3f8 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -123,6 +123,7 @@ struct stackmap } }; + // ------------------------------------------------ // A simple class for topological sorting // ------------------------------------------------ From 0a37c2a301f3518df0d3a9ced7b2b9477b4fe9a0 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Thu, 5 Oct 2023 17:01:42 -0700 Subject: [PATCH 084/240] Fix translation bug: The old code really checks for the presense of a node, not an edge in glift and flatten. Add back statement that inserts nodes in order in opt_expr.cc. --- kernel/utils.h | 8 +------- passes/cmds/glift.cc | 2 +- passes/opt/opt_expr.cc | 1 + passes/techmap/flatten.cc | 2 +- 4 files changed, 4 insertions(+), 9 deletions(-) diff --git a/kernel/utils.h b/kernel/utils.h index 255f875c3f8..5a1279ef01c 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -174,11 +174,7 @@ template , typename OPS = hash_ops> cla void edge(T left, T right) { edge(node(left), node(right)); } - bool has_edges(const T &node) - { - auto it = node_to_index.find(node); - return it == node_to_index.end() || !edges[it->second].empty(); - } + bool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); } bool sort() { @@ -192,8 +188,6 @@ template , typename OPS = hash_ops> cla std::vector marked_cells(edges.size(), false); std::vector active_cells(edges.size(), false); std::vector active_stack; - - marked_cells.reserve(edges.size()); sorted.reserve(edges.size()); for (const auto &it : node_to_index) diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index faa4289e3a9..8553b02a541 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -582,7 +582,7 @@ struct GliftPass : public Pass { for (auto cell : module->selected_cells()) { RTLIL::Module *tpl = design->module(cell->type); if (tpl != nullptr) { - if (!topo_modules.has_edges(tpl)) + if (!topo_modules.has_node(tpl)) worklist.push_back(tpl); topo_modules.edge(tpl, module); non_top_modules.insert(cell->type); diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 7331d72a6fd..3eadd35c6af 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -424,6 +424,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons for (auto &bit : sig) outbit_to_cell[bit].insert(cell); } + cells.node(cell); } // Build the graph for the topological sort. diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index f49589b826c..4ddc4aff1fa 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -312,7 +312,7 @@ struct FlattenPass : public Pass { for (auto cell : module->selected_cells()) { RTLIL::Module *tpl = design->module(cell->type); if (tpl != nullptr) { - if (!topo_modules.has_edges(tpl)) + if (!topo_modules.has_node(tpl)) worklist.insert(tpl); topo_modules.edge(tpl, module); } From fc815fdb478056247d46deee597e09df138a168d Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 6 Oct 2023 00:14:52 +0000 Subject: [PATCH 085/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 688b5939ded..c6b5706cc61 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.34+0 +YOSYS_VER := 0.34+7 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 6a5799cc2ed65a7481f9d1e9142b9039f78db188 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Thu, 5 Oct 2023 17:27:26 -0700 Subject: [PATCH 086/240] Add missing initialization of node_cmp_ member. --- kernel/utils.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/utils.h b/kernel/utils.h index 5a1279ef01c..31a8681f199 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -134,7 +134,7 @@ template , typename OPS = hash_ops> cla // We use this ordering of the edges in the adjacency matrix for // exact compatibility with an older implementation. struct IndirectCmp { - IndirectCmp(const std::vector &nodes) : nodes_(nodes) {} + IndirectCmp(const std::vector &nodes) : node_cmp_(), nodes_(nodes) {} bool operator()(int a, int b) const { log_assert(static_cast(a) < nodes_.size()); From 8367f06188edf750b32bd603552ba9d75995baf5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 5 Oct 2023 19:39:28 +0200 Subject: [PATCH 087/240] ast/simplify: Remove unused in_param code --- frontends/ast/simplify.cc | 5 ----- 1 file changed, 5 deletions(-) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index c5f0467041d..2a500b56bd3 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1749,13 +1749,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin bool const_fold_here = const_fold; int width_hint_here = width_hint; bool sign_hint_here = sign_hint; - bool in_param_here = in_param; if (i == 0 && (type == AST_REPLICATE || type == AST_WIRE)) const_fold_here = true; - if (i == 0 && (type == AST_GENIF || type == AST_GENCASE)) - in_param_here = true; - if (i == 1 && (type == AST_FOR || type == AST_GENFOR)) - in_param_here = true; if (type == AST_PARAMETER || type == AST_LOCALPARAM) const_fold_here = true; if (type == AST_BLOCK) { From 2ab7d1d0c85cf128f8711075584b76738e0d9b11 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 6 Oct 2023 16:05:44 +0200 Subject: [PATCH 088/240] Fix readline/editline memory leak --- kernel/yosys.cc | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 559ce872cad..4409dc91ddd 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1353,8 +1353,12 @@ void shell(RTLIL::Design *design) if ((command = fgets(command_buffer, 4096, stdin)) == NULL) break; #endif - if (command[strspn(command, " \t\r\n")] == 0) + if (command[strspn(command, " \t\r\n")] == 0) { +#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) + free(command); +#endif continue; + } #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) add_history(command); #endif @@ -1376,10 +1380,17 @@ void shell(RTLIL::Design *design) log_reset_stack(); } design->check(); +#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) + if (command) + free(command); +#endif } if (command == NULL) printf("exit\n"); - +#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) + else + free(command); +#endif recursion_counter--; log_cmd_error_throw = false; } From bc0df04e065d53f3f1e2053861a94de29eb9e013 Mon Sep 17 00:00:00 2001 From: Rasmus Munk Larsen Date: Fri, 6 Oct 2023 12:53:05 -0700 Subject: [PATCH 089/240] Get rid of double lookup in TopoSort::node(). This speeds up typical TopoSort time overall by ~10%. --- kernel/utils.h | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/kernel/utils.h b/kernel/utils.h index 31a8681f199..8fa223824da 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -159,15 +159,12 @@ template , typename OPS = hash_ops> cla int node(T n) { - auto it = node_to_index.find(n); - if (it == node_to_index.end()) { - int index = static_cast(nodes.size()); - node_to_index[n] = index; - nodes.push_back(n); - edges.push_back(std::set(indirect_cmp)); - return index; + auto rv = node_to_index.emplace(n, static_cast(nodes.size())); + if (rv.second) { + nodes.push_back(n); + edges.push_back(std::set(indirect_cmp)); } - return it->second; + return rv.first->second; } void edge(int l_index, int r_index) { edges[r_index].insert(l_index); } From 51e9b0882bf099ee28ba88d6cc14be1f877f6cff Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 7 Oct 2023 00:14:44 +0000 Subject: [PATCH 090/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index c6b5706cc61..907be74af0a 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.34+7 +YOSYS_VER := 0.34+9 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 0ca39e233b8d7aa4736830cad383bc59214da12b Mon Sep 17 00:00:00 2001 From: Marcus Comstedt Date: Sat, 7 Oct 2023 10:43:00 +0200 Subject: [PATCH 091/240] scc: Use hashlib instead of STL for deterministic behaviour --- passes/cmds/scc.cc | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 81881832cd7..197bd931966 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -27,7 +27,6 @@ #include "kernel/log.h" #include #include -#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -39,18 +38,18 @@ struct SccWorker SigMap sigmap; CellTypes ct, specifyCells; - std::set workQueue; - std::map> cellToNextCell; - std::map cellToPrevSig, cellToNextSig; + pool workQueue; + dict> cellToNextCell; + dict cellToPrevSig, cellToNextSig; - std::map> cellLabels; - std::map cellDepth; - std::set cellsOnStack; + dict> cellLabels; + dict cellDepth; + pool cellsOnStack; std::vector cellStack; int labelCounter; - std::map cell2scc; - std::vector> sccList; + dict cell2scc; + std::vector> sccList; void run(RTLIL::Cell *cell, int depth, int maxDepth) { @@ -85,7 +84,7 @@ struct SccWorker else { log("Found an SCC:"); - std::set scc; + pool scc; while (cellsOnStack.count(cell) > 0) { RTLIL::Cell *c = cellStack.back(); cellStack.pop_back(); @@ -199,11 +198,11 @@ struct SccWorker for (auto cell : workQueue) { - cellToNextCell[cell] = sigToNextCells.find(cellToNextSig[cell]); + sigToNextCells.find(cellToNextSig[cell], cellToNextCell[cell]); if (!nofeedbackMode && cellToNextCell[cell].count(cell)) { log("Found an SCC:"); - std::set scc; + pool scc; log(" %s", RTLIL::id2cstr(cell->name)); cell2scc[cell] = sccList.size(); scc.insert(cell); @@ -231,7 +230,7 @@ struct SccWorker { for (int i = 0; i < int(sccList.size()); i++) { - std::set &cells = sccList[i]; + pool &cells = sccList[i]; RTLIL::SigSpec prevsig, nextsig, sig; for (auto cell : cells) { @@ -295,7 +294,7 @@ struct SccPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { - std::map setAttr; + dict setAttr; bool allCellTypes = false; bool selectMode = false; bool nofeedbackMode = false; From c36cf9c5ac26ff6bdad8c505e0bcac677af25938 Mon Sep 17 00:00:00 2001 From: Wanda Date: Sun, 8 Oct 2023 01:11:30 +0200 Subject: [PATCH 092/240] write_verilog: avoid emitting empty cases. The Verilog grammar does not allow an empty case. Most synthesis tools are quite permissive about this, but Quartus is not. This causes problems for amaranth with Quartus (see amaranth-lang/amaranth#931). --- backends/verilog/verilog_backend.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 7099c18c349..735672a43b4 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2008,6 +2008,11 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw dump_case_body(f, indent + " ", *it); } + if (sw->cases.empty()) { + // Verilog does not allow empty cases. + f << stringf("%s default: ;\n", indent.c_str()); + } + f << stringf("%s" "endcase\n", indent.c_str()); } From 11b9deba9f05a107c70f66139fc988be46567719 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 9 Oct 2023 00:15:38 +0000 Subject: [PATCH 093/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 907be74af0a..0a9a7a2c32b 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.34+9 +YOSYS_VER := 0.34+14 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 4ed708836addfd406f290aa3f191bae3b471136f Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 10 Oct 2023 11:41:33 +0200 Subject: [PATCH 094/240] verific: Use CellBaseName to identify top modules --- frontends/verific/verific.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 804b6676b6b..716b4dc1317 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2573,7 +2573,7 @@ std::string verific_import(Design *design, const std::mapAddAtt(new Att(" \\top", NULL)); nl_todo.emplace(nl->CellBaseName(), nl); - cell_name = nl->Owner()->Name(); + cell_name = nl->CellBaseName(); } if (top.empty()) cell_name = top; @@ -2595,7 +2595,7 @@ std::string verific_import(Design *design, const std::mapfirst) == 0) { VerificImporter importer(false, false, false, false, false, false, false); nl_done[it->first] = it->second; - importer.import_netlist(design, nl, nl_todo, nl->Owner()->Name() == cell_name); + importer.import_netlist(design, nl, nl_todo, nl->CellBaseName() == cell_name); } nl_todo.erase(it); } @@ -3801,7 +3801,7 @@ struct VerificPass : public Pass { VerificImporter importer(mode_gates, mode_keep, mode_nosva, mode_names, mode_verific, mode_autocover, mode_fullinit); nl_done[it->first] = it->second; - importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->Owner()->Name())); + importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->CellBaseName())); } nl_todo.erase(it); } From 59fbee4009f02f807d3b60888ff5eca6670e3a7f Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 12 Oct 2023 00:13:29 +0000 Subject: [PATCH 095/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 0a9a7a2c32b..ebe9881430c 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.34+14 +YOSYS_VER := 0.34+23 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From d473a207a1692f6587516cc2b93d6f11aeff1d85 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 12 Oct 2023 09:17:06 +0200 Subject: [PATCH 096/240] Preserve VHDL architecture name in attribute --- frontends/verific/verific.cc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 716b4dc1317..115a42e332b 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -52,6 +52,7 @@ USING_YOSYS_NAMESPACE #ifdef VERIFIC_VHDL_SUPPORT #include "vhdl_file.h" #include "VhdlUnits.h" +#include "NameSpace.h" #endif #ifdef VERIFIC_EDIF_SUPPORT @@ -1276,6 +1277,13 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma } import_attributes(module->attributes, nl, nl); module->set_string_attribute(ID::hdlname, nl->CellBaseName()); +#ifdef VERIFIC_VHDL_SUPPORT + if (nl->IsFromVhdl()) { + NameSpace name_space(0); + char *architecture_name = name_space.ReName(nl->Name()) ; + module->set_string_attribute(ID(architecture), (architecture_name) ? architecture_name : nl->Name()); + } +#endif const char *param_name ; const char *param_value ; MapIter mi; From 62d63386886dcfec7d0087e10f52ff7c4a7796cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 12 Oct 2023 12:45:11 +0200 Subject: [PATCH 097/240] quicklogic: Fix pp3 `dffs` test Fix name confusion which was making the test look into the vendor's cell blackbox rather than into the synthesis results. --- tests/arch/quicklogic/dffs.ys | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/tests/arch/quicklogic/dffs.ys b/tests/arch/quicklogic/dffs.ys index 2e0a34540ec..e1fbef635d8 100644 --- a/tests/arch/quicklogic/dffs.ys +++ b/tests/arch/quicklogic/dffs.ys @@ -7,14 +7,27 @@ hierarchy -top my_dff proc equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dff # Constrain all select calls below inside the top module -select -assert-none t:* +cd my_dff # Constrain all select calls below inside the top module +select -assert-count 1 t:ckpad +select -assert-count 1 t:dffepc +select -assert-count 1 t:inpad +select -assert-count 1 t:logic_0 +select -assert-count 1 t:logic_1 +select -assert-count 1 t:outpad + +select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:logic_1 t:outpad %% t:* %D design -load read hierarchy -top my_dffe proc equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffe # Constrain all select calls below inside the top module +cd my_dffe # Constrain all select calls below inside the top module + +select -assert-count 1 t:ckpad +select -assert-count 1 t:dffepc +select -assert-count 2 t:inpad +select -assert-count 1 t:logic_0 +select -assert-count 1 t:outpad -select -assert-none t:* \ No newline at end of file +select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:outpad %% t:* %D From 69c252f2476e01f2ea95ecb2b2f218568638f370 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 13 Oct 2023 14:32:11 +0200 Subject: [PATCH 098/240] Update abc --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index ebe9881430c..6274e71a3a0 100644 --- a/Makefile +++ b/Makefile @@ -165,7 +165,7 @@ bumpversion: # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = daad9ed +ABCREV = 896e5e7 ABCPULL = 1 ABCURL ?= https://github.com/YosysHQ/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) From 7d30f716e82ff4782b653cb2c448062f7878c308 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 14 Oct 2023 00:14:36 +0000 Subject: [PATCH 099/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 6274e71a3a0..c75bb0c66b6 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.34+23 +YOSYS_VER := 0.34+27 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From a0c3be3aaeb2bbb87161432748aa349712e35dc1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 2 Aug 2023 13:52:40 +0200 Subject: [PATCH 100/240] peepopt: Drop unused 'initbits' code Drop code that was once used by the 'dffmux' pattern but now is unused after that pattern has been obsoleted by the 'opt_dff' pass. --- passes/pmgen/peepopt.cc | 39 --------------------------------------- 1 file changed, 39 deletions(-) diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index 9a497c91441..1d27d77a0f2 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -24,8 +24,6 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN bool did_something; -dict initbits; -pool rminitbits; #include "passes/pmgen/peepopt_pm.h" #include "generate.h" @@ -60,9 +58,6 @@ struct PeepoptPass : public Pass { if (!genmode.empty()) { - initbits.clear(); - rminitbits.clear(); - if (genmode == "shiftmul") GENERATE_PATTERN(peepopt_pm, shiftmul); else if (genmode == "muldiv") @@ -79,47 +74,13 @@ struct PeepoptPass : public Pass { while (did_something) { did_something = false; - initbits.clear(); - rminitbits.clear(); peepopt_pm pm(module); - for (auto w : module->wires()) { - auto it = w->attributes.find(ID::init); - if (it != w->attributes.end()) { - SigSpec sig = pm.sigmap(w); - Const val = it->second; - int len = std::min(GetSize(sig), GetSize(val)); - for (int i = 0; i < len; i++) { - if (sig[i].wire == nullptr) - continue; - if (val[i] != State::S0 && val[i] != State::S1) - continue; - initbits[sig[i]] = val[i]; - } - } - } - pm.setup(module->selected_cells()); pm.run_shiftmul(); pm.run_muldiv(); - - for (auto w : module->wires()) { - auto it = w->attributes.find(ID::init); - if (it != w->attributes.end()) { - SigSpec sig = pm.sigmap(w); - Const &val = it->second; - int len = std::min(GetSize(sig), GetSize(val)); - for (int i = 0; i < len; i++) { - if (rminitbits.count(sig[i])) - val[i] = State::Sx; - } - } - } - - initbits.clear(); - rminitbits.clear(); } } } From bd8a81a907f0307254387a2b74aa1d1ebc582505 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 2 Aug 2023 15:44:41 +0200 Subject: [PATCH 101/240] peepopt: Clean up 'shiftmul' a bit No functional change intended. --- passes/pmgen/peepopt_shiftmul.pmg | 66 +++++++++++++++++-------------- 1 file changed, 36 insertions(+), 30 deletions(-) diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg index d71fbf74449..92e902d3ea6 100644 --- a/passes/pmgen/peepopt_shiftmul.pmg +++ b/passes/pmgen/peepopt_shiftmul.pmg @@ -3,61 +3,67 @@ pattern shiftmul // Optimize mul+shift pairs that result from expressions such as foo[s*W+:W] // -state shamt - match shift select shift->type.in($shift, $shiftx, $shr) + filter !port(shift, \B).empty() endmatch -code shamt - shamt = port(shift, \B); - if (shamt.empty()) - reject; - if (shamt[GetSize(shamt)-1] == State::S0) { - do { - shamt.remove(GetSize(shamt)-1); - if (shamt.empty()) - reject; - } while (shamt[GetSize(shamt)-1] == State::S0); - } else - if (shift->type.in($shift, $shiftx) && param(shift, \B_SIGNED).as_bool()) { +state shift_amount + +code shift_amount + shift_amount = port(shift, \B); + if (shift->type.in($shr) || !param(shift, \B_SIGNED).as_bool()) + shift_amount.append(State::S0); + + // at this point shift_amount is signed, make + // sure we can never go negative + if (shift_amount.bits().back() != State::S0) reject; + + while (shift_amount.bits().back() == State::S0) { + shift_amount.remove(GetSize(shift_amount) - 1); + if (shift_amount.empty()) reject; } - if (GetSize(shamt) > 20) + + if (GetSize(shift_amount) > 20) reject; endcode +state mul_din +state mul_const + match mul select mul->type.in($mul) - select port(mul, \A).is_fully_const() || port(mul, \B).is_fully_const() - index port(mul, \Y) === shamt + index port(mul, \Y) === shift_amount filter !param(mul, \A_SIGNED).as_bool() + + choice constport {\A, \B} + filter port(mul, constport).is_fully_const() + + define varport (constport == \A ? \B : \A) + set mul_const port(mul, constport).as_const() + set mul_din port(mul, varport) endmatch code { - IdString const_factor_port = port(mul, \A).is_fully_const() ? \A : \B; - Const const_factor_cnst = port(mul, const_factor_port).as_const(); - int const_factor = const_factor_cnst.as_int(); - - if (GetSize(const_factor_cnst) == 0) + if (mul_const.empty() || GetSize(mul_const) > 20) reject; - if (GetSize(const_factor_cnst) > 20) + // make sure there's no overlap in the signal + // selections by the shiftmul pattern + if (GetSize(port(shift, \Y)) > mul_const.as_int()) reject; - if (GetSize(port(shift, \Y)) > const_factor) - reject; - - int factor_bits = ceil_log2(const_factor); - SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A); - - if (GetSize(shamt) < factor_bits+GetSize(mul_din)) + int factor_bits = ceil_log2(mul_const.as_int()); + // make sure the multiplication never wraps around + if (GetSize(shift_amount) < factor_bits + GetSize(mul_din)) reject; did_something = true; log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); + int const_factor = mul_const.as_int(); int new_const_factor = 1 << factor_bits; SigSpec padding(State::Sx, new_const_factor-const_factor); SigSpec old_a = port(shift, \A), new_a; From dd1a8ae49a54b00407afef92f5dac1b36e7efefa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 2 Aug 2023 15:46:50 +0200 Subject: [PATCH 102/240] peepopt: Try to use original wires --- passes/pmgen/peepopt_shiftmul.pmg | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg index 92e902d3ea6..177d97371b4 100644 --- a/passes/pmgen/peepopt_shiftmul.pmg +++ b/passes/pmgen/peepopt_shiftmul.pmg @@ -42,7 +42,11 @@ match mul define varport (constport == \A ? \B : \A) set mul_const port(mul, constport).as_const() - set mul_din port(mul, varport) + // get mul_din unmapped (so no `port()` shorthand) + // because we will be using it to set the \A port + // on the shift cell, and we want to stay close + // to the original design + set mul_din mul->getPort(varport) endmatch code From 038a5e1ed4d31a1ad1fde63971939abd8885fe2b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 2 Aug 2023 16:10:27 +0200 Subject: [PATCH 103/240] peepopt: Support shift amounts zero-padded from below The `opt_expr` pass running before `peepopt` can interfere with the detection of a shiftmul pattern due to some of the bottom bits of the shift amount being replaced with constant zero. Extend the detection to cover those situations as well. --- passes/pmgen/peepopt_shiftmul.pmg | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg index 177d97371b4..4808430b4d3 100644 --- a/passes/pmgen/peepopt_shiftmul.pmg +++ b/passes/pmgen/peepopt_shiftmul.pmg @@ -8,9 +8,13 @@ match shift filter !port(shift, \B).empty() endmatch +// the right shift amount state shift_amount +// log2 scale factor in interpreting of shift_amount +// due to zero padding on the shift cell's B port +state log2scale -code shift_amount +code shift_amount log2scale shift_amount = port(shift, \B); if (shift->type.in($shr) || !param(shift, \B_SIGNED).as_bool()) shift_amount.append(State::S0); @@ -25,6 +29,13 @@ code shift_amount if (shift_amount.empty()) reject; } + log2scale = 0; + while (shift_amount[0] == State::S0) { + shift_amount.remove(0); + if (shift_amount.empty()) reject; + log2scale++; + } + if (GetSize(shift_amount) > 20) reject; endcode @@ -41,7 +52,7 @@ match mul filter port(mul, constport).is_fully_const() define varport (constport == \A ? \B : \A) - set mul_const port(mul, constport).as_const() + set mul_const SigSpec({port(mul, constport), SigSpec(State::S0, log2scale)}).as_const() // get mul_din unmapped (so no `port()` shorthand) // because we will be using it to set the \A port // on the shift cell, and we want to stay close @@ -61,7 +72,7 @@ code int factor_bits = ceil_log2(mul_const.as_int()); // make sure the multiplication never wraps around - if (GetSize(shift_amount) < factor_bits + GetSize(mul_din)) + if (GetSize(shift_amount) + log2scale < factor_bits + GetSize(mul_din)) reject; did_something = true; From aa9b86aeec1b1b2ea2d3344098963300b4f624f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 2 Aug 2023 18:04:54 +0200 Subject: [PATCH 104/240] peepopt: Add left-shift 'shiftmul' variant Add a separate shiftmul pattern to match on left shifts which implement demuxing. This mirrors the right shift pattern matcher but is probably best kept separate instead of merging the two into a single matcher. In any case the diff of the two matchers should be easily readable. --- passes/pmgen/Makefile.inc | 3 +- passes/pmgen/peepopt.cc | 5 +- passes/pmgen/peepopt_shiftmul_left.pmg | 160 ++++++++++++++++++ ...hiftmul.pmg => peepopt_shiftmul_right.pmg} | 4 +- 4 files changed, 167 insertions(+), 5 deletions(-) create mode 100644 passes/pmgen/peepopt_shiftmul_left.pmg rename passes/pmgen/{peepopt_shiftmul.pmg => peepopt_shiftmul_right.pmg} (95%) diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index a7ef642825c..c2257b72083 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -42,7 +42,8 @@ GENFILES += passes/pmgen/peepopt_pm.h passes/pmgen/peepopt.o: passes/pmgen/peepopt_pm.h $(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h)) -PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul.pmg +PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul_right.pmg +PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftmul_left.pmg PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN) diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index 1d27d77a0f2..2b225623dba 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -59,7 +59,7 @@ struct PeepoptPass : public Pass { if (!genmode.empty()) { if (genmode == "shiftmul") - GENERATE_PATTERN(peepopt_pm, shiftmul); + GENERATE_PATTERN(peepopt_pm, shiftmul_right); else if (genmode == "muldiv") GENERATE_PATTERN(peepopt_pm, muldiv); else @@ -79,7 +79,8 @@ struct PeepoptPass : public Pass { pm.setup(module->selected_cells()); - pm.run_shiftmul(); + pm.run_shiftmul_right(); + pm.run_shiftmul_left(); pm.run_muldiv(); } } diff --git a/passes/pmgen/peepopt_shiftmul_left.pmg b/passes/pmgen/peepopt_shiftmul_left.pmg new file mode 100644 index 00000000000..607f8368c53 --- /dev/null +++ b/passes/pmgen/peepopt_shiftmul_left.pmg @@ -0,0 +1,160 @@ +pattern shiftmul_left +// +// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W] +// + +match shift + select shift->type.in($shift, $shiftx, $shl) + select shift->type.in($shl) || param(shift, \B_SIGNED).as_bool() + filter !port(shift, \B).empty() +endmatch + +match neg + if shift->type.in($shift, $shiftx) + select neg->type == $neg + index port(neg, \Y) === port(shift, \B) + filter !port(shift, \A).empty() +endmatch + +// the left shift amount +state shift_amount +// log2 scale factor in interpreting of shift_amount +// due to zero padding on the shift cell's B port +state log2scale + +code shift_amount log2scale + if (neg) { + // case of `$shift`, `$shiftx` + shift_amount = port(neg, \A); + if (!param(neg, \A_SIGNED).as_bool()) + shift_amount.append(State::S0); + } else { + // case of `$shl` + shift_amount = port(shift, \B); + if (!param(shift, \B_SIGNED).as_bool()) + shift_amount.append(State::S0); + } + + // at this point shift_amount is signed, make + // sure we can never go negative + if (shift_amount.bits().back() != State::S0) + reject; + + while (shift_amount.bits().back() == State::S0) { + shift_amount.remove(GetSize(shift_amount) - 1); + if (shift_amount.empty()) reject; + } + + log2scale = 0; + while (shift_amount[0] == State::S0) { + shift_amount.remove(0); + if (shift_amount.empty()) reject; + log2scale++; + } + + if (GetSize(shift_amount) > 20) + reject; +endcode + +state mul_din +state mul_const + +match mul + select mul->type.in($mul) + index port(mul, \Y) === shift_amount + filter !param(mul, \A_SIGNED).as_bool() + + choice constport {\A, \B} + filter port(mul, constport).is_fully_const() + + define varport (constport == \A ? \B : \A) + set mul_const SigSpec({port(mul, constport), SigSpec(State::S0, log2scale)}).as_const() + // get mul_din unmapped (so no `port()` shorthand) + // because we will be using it to set the \A port + // on the shift cell, and we want to stay close + // to the original design + set mul_din mul->getPort(varport) +endmatch + +code +{ + if (mul_const.empty() || GetSize(mul_const) > 20) + reject; + + // make sure there's no overlap in the signal + // selections by the shiftmul pattern + if (GetSize(port(shift, \A)) > mul_const.as_int()) + reject; + + int factor_bits = ceil_log2(mul_const.as_int()); + // make sure the multiplication never wraps around + if (GetSize(shift_amount) < factor_bits + GetSize(mul_din)) + reject; + + if (neg) { + // make sure the negation never wraps around + if (GetSize(port(shift, \B)) < factor_bits + GetSize(mul_din) + + log2scale + 1) + reject; + } + + did_something = true; + log("left shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); + + int const_factor = mul_const.as_int(); + int new_const_factor = 1 << factor_bits; + SigSpec padding(State::Sm, new_const_factor-const_factor); + SigSpec old_y = port(shift, \Y), new_y; + int trunc = 0; + + if (GetSize(old_y) % const_factor != 0) { + trunc = const_factor - GetSize(old_y) % const_factor; + old_y.append(SigSpec(State::Sm, trunc)); + } + + for (int i = 0; i*const_factor < GetSize(old_y); i++) { + SigSpec slice = old_y.extract(i*const_factor, const_factor); + new_y.append(slice); + new_y.append(padding); + } + + if (trunc > 0) + new_y.remove(GetSize(new_y)-trunc, trunc); + + { + // Now replace occurences of Sm in new_y with bits + // of a dummy wire + int padbits = 0; + for (auto bit : new_y) + if (bit == SigBit(State::Sm)) + padbits++; + + SigSpec padwire = module->addWire(NEW_ID, padbits); + + for (int i = new_y.size() - 1; i >= 0; i--) + if (new_y[i] == SigBit(State::Sm)) { + new_y[i] = padwire.bits().back(); + padwire.remove(padwire.size() - 1); + } + } + + SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)}; + + shift->setPort(\Y, new_y); + shift->setParam(\Y_WIDTH, GetSize(new_y)); + if (shift->type == $shl) { + if (param(shift, \B_SIGNED).as_bool()) + new_b.append(State::S0); + shift->setPort(\B, new_b); + shift->setParam(\B_WIDTH, GetSize(new_b)); + } else { + SigSpec b_neg = module->addWire(NEW_ID, GetSize(new_b) + 1); + module->addNeg(NEW_ID, new_b, b_neg); + shift->setPort(\B, b_neg); + shift->setParam(\B_WIDTH, GetSize(b_neg)); + } + + blacklist(shift); + accept; +} +endcode diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul_right.pmg similarity index 95% rename from passes/pmgen/peepopt_shiftmul.pmg rename to passes/pmgen/peepopt_shiftmul_right.pmg index 4808430b4d3..71e0980234a 100644 --- a/passes/pmgen/peepopt_shiftmul.pmg +++ b/passes/pmgen/peepopt_shiftmul_right.pmg @@ -1,4 +1,4 @@ -pattern shiftmul +pattern shiftmul_right // // Optimize mul+shift pairs that result from expressions such as foo[s*W+:W] // @@ -76,7 +76,7 @@ code reject; did_something = true; - log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); + log("right shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); int const_factor = mul_const.as_int(); int new_const_factor = 1 << factor_bits; From 5c0c8251c38f103aa63e5cf1e689c64803ba7e16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 16 Oct 2023 13:54:17 +0200 Subject: [PATCH 105/240] peepopt: Remove broken `-generate` option --- passes/pmgen/peepopt.cc | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index 2b225623dba..f0349525472 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -26,7 +26,6 @@ PRIVATE_NAMESPACE_BEGIN bool did_something; #include "passes/pmgen/peepopt_pm.h" -#include "generate.h" struct PeepoptPass : public Pass { PeepoptPass() : Pass("peepopt", "collection of peephole optimizers") { } @@ -41,32 +40,15 @@ struct PeepoptPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { - std::string genmode; - log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-generate" && argidx+1 < args.size()) { - genmode = args[++argidx]; - continue; - } break; } extra_args(args, argidx, design); - if (!genmode.empty()) - { - if (genmode == "shiftmul") - GENERATE_PATTERN(peepopt_pm, shiftmul_right); - else if (genmode == "muldiv") - GENERATE_PATTERN(peepopt_pm, muldiv); - else - log_abort(); - return; - } - for (auto module : design->selected_modules()) { did_something = true; From 660be4a31e58f7d348fea9b3fe41553ac061f26a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 16 Oct 2023 14:08:42 +0200 Subject: [PATCH 106/240] peepopt: Describe rules in help message --- passes/pmgen/peepopt.cc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index f0349525472..aef464d79c9 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -37,6 +37,17 @@ struct PeepoptPass : public Pass { log("\n"); log("This pass applies a collection of peephole optimizers to the current design.\n"); log("\n"); + log("This pass employs the following rules:\n"); + log("\n"); + log(" * muldiv - Replace (A*B)/B with A\n"); + log("\n"); + log(" * shiftmul - Replace A>>(B*C) with A'>>(B< args, RTLIL::Design *design) override { From d6d1cc705e524264361bfc16f7a2ef5a96b0b717 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 16 Oct 2023 14:16:36 +0200 Subject: [PATCH 107/240] pmgen: Fix sample syntax --- passes/pmgen/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md index 39560839f0f..3205be1b55e 100644 --- a/passes/pmgen/README.md +++ b/passes/pmgen/README.md @@ -212,7 +212,7 @@ second argument, and the matcher will iterate over those options: index port(eq, BA) === bar set eq_ab AB set eq_ba BA - generate + endmatch Notice how `define` can be used to define additional local variables similar to the loop variables defined by `slice` and `choice`. From a5c04dd72e3d02d36dadf1c60ae76bb149969970 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 17 Oct 2023 00:15:28 +0000 Subject: [PATCH 108/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index c75bb0c66b6..b89c87ae943 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.34+27 +YOSYS_VER := 0.34+43 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 1b6d1e941950576f16140e43a53c1694cddb1092 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Thu, 19 Oct 2023 19:12:36 +0200 Subject: [PATCH 109/240] memory_libmap: look for ram_style attributes on surrounding signals --- kernel/constids.inc | 1 + kernel/mem.cc | 6 +++ passes/memory/memory_libmap.cc | 44 ++++++++++++++++--- tests/memlib/generate.py | 22 ++++++++++ tests/verific/rom_case.ys | 78 ++++++++++++++++++++++++++++++++++ 5 files changed, 146 insertions(+), 5 deletions(-) create mode 100644 tests/verific/rom_case.ys diff --git a/kernel/constids.inc b/kernel/constids.inc index 93101282a0b..480e2afc6fa 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -140,6 +140,7 @@ X(nomem2reg) X(nomeminit) X(nosync) X(nowrshmsk) +X(no_ram) X(no_rw_check) X(O) X(OFFSET) diff --git a/kernel/mem.cc b/kernel/mem.cc index 269a476a125..40345b81df1 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -148,6 +148,8 @@ void Mem::emit() { for (int j = 0; j < (1 << wr_ports[i].wide_log2); j++) wr_port_xlat.push_back(i); for (auto &port : rd_ports) { + for (auto attr: port.attributes) + cell->attributes.insert(attr); if (port.cell) { module->remove(port.cell); port.cell = nullptr; @@ -210,6 +212,8 @@ void Mem::emit() { cell->setPort(ID::RD_ADDR, rd_addr); cell->setPort(ID::RD_DATA, rd_data); for (auto &port : wr_ports) { + for (auto attr: port.attributes) + cell->attributes.insert(attr); if (port.cell) { module->remove(port.cell); port.cell = nullptr; @@ -246,6 +250,8 @@ void Mem::emit() { cell->setPort(ID::WR_ADDR, wr_addr); cell->setPort(ID::WR_DATA, wr_data); for (auto &init : inits) { + for (auto attr: init.attributes) + cell->attributes.insert(attr); if (init.cell) { module->remove(init.cell); init.cell = nullptr; diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index f8b0eec1d8d..e39a518b761 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -481,18 +481,49 @@ void MemMapping::dump_config(MemConfig &cfg) { } } +std::pair search_for_attribute(Mem mem, IdString attr) { + if (mem.has_attribute(attr)) + return std::make_pair(true, mem.attributes.at(attr)); + for (auto &port: mem.rd_ports){ + if (port.has_attribute(attr)) + return std::make_pair(true, port.attributes.at(attr)); + log_debug("looking for attribute %s on signal %s\n", log_id(attr), log_signal(port.data)); + for (SigBit bit: port.data) + if (bit.is_wire() && bit.wire->has_attribute(attr)) + return std::make_pair(true, bit.wire->attributes.at(attr)); + log_debug("looking for attribute %s on signal %s\n", log_id(attr), log_signal(port.data)); + for (SigBit bit: port.addr) + if (bit.is_wire() && bit.wire->has_attribute(attr)) + return std::make_pair(true, bit.wire->attributes.at(attr)); + } + for (auto &port: mem.wr_ports){ + if (port.has_attribute(attr)) + return std::make_pair(true, port.attributes.at(attr)); + log_debug("looking for attribute %s on signal %s\n", log_id(attr), log_signal(port.data)); + for (SigBit bit: port.data) + if (bit.is_wire() && bit.wire->has_attribute(attr)) + return std::make_pair(true, bit.wire->attributes.at(attr)); + for (SigBit bit: port.addr) + if (bit.is_wire() && bit.wire->has_attribute(attr)) + return std::make_pair(true, bit.wire->attributes.at(attr)); + } + return std::make_pair(false, Const()); +} + // Go through memory attributes to determine user-requested mapping style. void MemMapping::determine_style() { kind = RamKind::Auto; style = ""; - if (mem.get_bool_attribute(ID::lram)) { + auto find_attr = search_for_attribute(mem, ID::lram); + if (find_attr.first && find_attr.second.as_bool()) { kind = RamKind::Huge; log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", log_id(mem.module->name), log_id(mem.memid)); return; } for (auto attr: {ID::ram_block, ID::rom_block, ID::ram_style, ID::rom_style, ID::ramstyle, ID::romstyle, ID::syn_ramstyle, ID::syn_romstyle}) { - if (mem.has_attribute(attr)) { - Const val = mem.attributes.at(attr); + find_attr = search_for_attribute(mem, attr); + if (find_attr.first) { + Const val = find_attr.second; if (val == 1) { kind = RamKind::NotLogic; log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", log_id(attr), log_id(mem.module->name), log_id(mem.memid)); @@ -526,8 +557,11 @@ void MemMapping::determine_style() { return; } } - if (mem.get_bool_attribute(ID::logic_block)) - kind = RamKind::Logic; + for (auto attr: {ID::logic_block, ID::no_ram}){ + find_attr = search_for_attribute(mem, attr); + if (find_attr.first && find_attr.second.as_bool()) + kind = RamKind::Logic; + } } // Determine whether the memory can be mapped entirely to soft logic. diff --git a/tests/memlib/generate.py b/tests/memlib/generate.py index f40210501db..46eff6b43e3 100644 --- a/tests/memlib/generate.py +++ b/tests/memlib/generate.py @@ -1513,6 +1513,28 @@ def __init__(self, name, src, libs, defs, cells): ["block_sp_full"], defs, {"RAM_BLOCK_SP": 1, "$*": add_logic} )) + +ROM_CASE = """ +module rom(input clk, input [2:0] addr, {attr}output reg [7:0] data); + +always @(posedge clk) begin + case (addr) + 3'b000: data <= 8'h12; + 3'b001: data <= 8'hAB; + 3'b010: data <= 8'h42; + 3'b011: data <= 8'h23; + 3'b100: data <= 8'h66; + 3'b101: data <= 8'hC0; + 3'b110: data <= 8'h3F; + 3'b111: data <= 8'h95; + endcase +end + +endmodule +""" + +TESTS.append(Test("rom_case", ROM_CASE.format(attr=""), ["block_sdp"], [], {"RAM_BLOCK_SDP" : 0})) +TESTS.append(Test("rom_case_block", ROM_CASE.format(attr="(* rom_style = \"block\" *) "), ["block_sdp"], [], {"RAM_BLOCK_SDP" : 1})) with open("run-test.mk", "w") as mf: mf.write("ifneq ($(strip $(SEED)),)\n") diff --git a/tests/verific/rom_case.ys b/tests/verific/rom_case.ys new file mode 100644 index 00000000000..171c16db766 --- /dev/null +++ b/tests/verific/rom_case.ys @@ -0,0 +1,78 @@ +verific -sv < data <= X"12"; + when "001" => data <= X"AB"; + when "010" => data <= X"42"; + when "011" => data <= X"23"; + when "100" => data <= X"66"; + when "101" => data <= X"C0"; + when "110" => data <= X"3F"; + when others => data <= X"95"; + end case; + end if; + end process p_rom; + +end architecture rtl; +EOF +hierarchy -top rom +proc +opt +opt -full +memory -nomap +dump +memory_libmap -lib ../memlib/memlib_block_sdp.txt +memory_map +stat +select -assert-count 1 t:RAM_BLOCK_SDP \ No newline at end of file From 833b67af80a748b7c1f8a775c5721b2815151f34 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Fri, 20 Oct 2023 18:31:41 +0200 Subject: [PATCH 110/240] verific: import attributes on ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Miodrag Milanović --- frontends/verific/verific.cc | 7 ++++++- tests/verific/memory_semantics.ys | 4 ++-- tests/verific/rom_case.ys | 4 ++-- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 115a42e332b..5ac8f8b393c 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1345,7 +1345,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex()); wire->upto = portbus->IsUp(); import_attributes(wire->attributes, portbus, nl); - + SetIter si ; + Port *port ; + FOREACH_PORT_OF_PORTBUS(portbus, si, port) { + import_attributes(wire->attributes, port->GetNet(), nl); + break; + } bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN; if (portbus_input) wire->port_input = true; diff --git a/tests/verific/memory_semantics.ys b/tests/verific/memory_semantics.ys index 92f4fd2dc44..adcd3a4ca7c 100644 --- a/tests/verific/memory_semantics.ys +++ b/tests/verific/memory_semantics.ys @@ -26,9 +26,9 @@ reg [DEPTH_LOG2-1:0] counter = 0; reg done = 1'b0; always @(posedge clk) begin if (!done) - counter = counter + 1; + counter = counter + 1'b1; if (counter == 0) - done = 1; + done = 1'b1; end wire [WIDTH-1:0] old_data = PRIME1 * counter; diff --git a/tests/verific/rom_case.ys b/tests/verific/rom_case.ys index 171c16db766..253cc0766ef 100644 --- a/tests/verific/rom_case.ys +++ b/tests/verific/rom_case.ys @@ -30,7 +30,7 @@ select -assert-count 1 t:RAM_BLOCK_SDP design -reset -verific -vhdl << +verific -vhdl < Date: Tue, 24 Oct 2023 13:55:45 +0200 Subject: [PATCH 111/240] memory_libmap: update search order for attributes --- passes/memory/memory_libmap.cc | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index e39a518b761..ec181a142c4 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -482,31 +482,40 @@ void MemMapping::dump_config(MemConfig &cfg) { } std::pair search_for_attribute(Mem mem, IdString attr) { + // priority of attributes: + // 1. attributes on memory itself + // 2. attributes on a read or write port + // 3. attributes on data signal of a read or write port + // 4. attributes on address signal of a read or write port + if (mem.has_attribute(attr)) return std::make_pair(true, mem.attributes.at(attr)); - for (auto &port: mem.rd_ports){ + + for (auto &port: mem.rd_ports) + if (port.has_attribute(attr)) + return std::make_pair(true, port.attributes.at(attr)); + for (auto &port: mem.wr_ports) if (port.has_attribute(attr)) return std::make_pair(true, port.attributes.at(attr)); - log_debug("looking for attribute %s on signal %s\n", log_id(attr), log_signal(port.data)); + + for (auto &port: mem.rd_ports) for (SigBit bit: port.data) if (bit.is_wire() && bit.wire->has_attribute(attr)) return std::make_pair(true, bit.wire->attributes.at(attr)); - log_debug("looking for attribute %s on signal %s\n", log_id(attr), log_signal(port.data)); - for (SigBit bit: port.addr) + for (auto &port: mem.wr_ports) + for (SigBit bit: port.data) if (bit.is_wire() && bit.wire->has_attribute(attr)) return std::make_pair(true, bit.wire->attributes.at(attr)); - } - for (auto &port: mem.wr_ports){ - if (port.has_attribute(attr)) - return std::make_pair(true, port.attributes.at(attr)); - log_debug("looking for attribute %s on signal %s\n", log_id(attr), log_signal(port.data)); - for (SigBit bit: port.data) + + for (auto &port: mem.rd_ports) + for (SigBit bit: port.addr) if (bit.is_wire() && bit.wire->has_attribute(attr)) return std::make_pair(true, bit.wire->attributes.at(attr)); + for (auto &port: mem.wr_ports) for (SigBit bit: port.addr) if (bit.is_wire() && bit.wire->has_attribute(attr)) return std::make_pair(true, bit.wire->attributes.at(attr)); - } + return std::make_pair(false, Const()); } From 6ffc3159360d8d7992af02cbc483718dd07c812e Mon Sep 17 00:00:00 2001 From: Catherine Date: Mon, 9 Oct 2023 11:45:12 +0000 Subject: [PATCH 112/240] cxxrtl: export wire attributes through the C API. Co-authored-by: Charlotte --- backends/cxxrtl/cxxrtl.h | 48 +++++++++++++--- backends/cxxrtl/cxxrtl_backend.cc | 91 ++++++++++++++++++++----------- backends/cxxrtl/cxxrtl_capi.cc | 43 +++++++++++++++ backends/cxxrtl/cxxrtl_capi.h | 65 ++++++++++++++++++++++ 4 files changed, 207 insertions(+), 40 deletions(-) diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h index 8f5e4035a34..b2871ee19df 100644 --- a/backends/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/cxxrtl.h @@ -1019,14 +1019,14 @@ struct metadata { // In debug mode, using the wrong .as_*() function will assert. // In release mode, using the wrong .as_*() function will safely return a default value. - const unsigned uint_value = 0; - const signed sint_value = 0; + const uint64_t uint_value = 0; + const int64_t sint_value = 0; const std::string string_value = ""; const double double_value = 0.0; metadata() : value_type(MISSING) {} - metadata(unsigned value) : value_type(UINT), uint_value(value) {} - metadata(signed value) : value_type(SINT), sint_value(value) {} + metadata(uint64_t value) : value_type(UINT), uint_value(value) {} + metadata(int64_t value) : value_type(SINT), sint_value(value) {} metadata(const std::string &value) : value_type(STRING), string_value(value) {} metadata(const char *value) : value_type(STRING), string_value(value) {} metadata(double value) : value_type(DOUBLE), double_value(value) {} @@ -1034,12 +1034,12 @@ struct metadata { metadata(const metadata &) = default; metadata &operator=(const metadata &) = delete; - unsigned as_uint() const { + uint64_t as_uint() const { assert(value_type == UINT); return uint_value; } - signed as_sint() const { + int64_t as_sint() const { assert(value_type == SINT); return sint_value; } @@ -1068,6 +1068,9 @@ using debug_outline = ::_cxxrtl_outline; // // To avoid violating strict aliasing rules, this structure has to be a subclass of the one used // in the C API, or it would not be possible to cast between the pointers to these. +// +// The `attrs` member cannot be owned by this structure because a `cxxrtl_object` can be created +// from external C code. struct debug_item : ::cxxrtl_object { // Object types. enum : uint32_t { @@ -1103,6 +1106,7 @@ struct debug_item : ::cxxrtl_object { curr = item.data; next = item.data; outline = nullptr; + attrs = nullptr; } template @@ -1118,6 +1122,7 @@ struct debug_item : ::cxxrtl_object { curr = const_cast(item.data); next = nullptr; outline = nullptr; + attrs = nullptr; } template @@ -1134,6 +1139,7 @@ struct debug_item : ::cxxrtl_object { curr = item.curr.data; next = item.next.data; outline = nullptr; + attrs = nullptr; } template @@ -1149,6 +1155,7 @@ struct debug_item : ::cxxrtl_object { curr = item.data ? item.data[0].data : nullptr; next = nullptr; outline = nullptr; + attrs = nullptr; } template @@ -1164,6 +1171,7 @@ struct debug_item : ::cxxrtl_object { curr = const_cast(item.data); next = nullptr; outline = nullptr; + attrs = nullptr; } template @@ -1180,6 +1188,7 @@ struct debug_item : ::cxxrtl_object { curr = const_cast(item.curr.data); next = nullptr; outline = nullptr; + attrs = nullptr; } template @@ -1195,6 +1204,7 @@ struct debug_item : ::cxxrtl_object { curr = const_cast(item.data); next = nullptr; outline = &group; + attrs = nullptr; } template @@ -1215,10 +1225,28 @@ struct debug_item : ::cxxrtl_object { }; static_assert(std::is_standard_layout::value, "debug_item is not compatible with C layout"); +} // namespace cxxrtl + +typedef struct _cxxrtl_attr_set { + cxxrtl::metadata_map map; +} *cxxrtl_attr_set; + +namespace cxxrtl { + +// Representation of an attribute set in the C++ interface. +using debug_attrs = ::_cxxrtl_attr_set; + struct debug_items { std::map> table; - - void add(const std::string &name, debug_item &&item) { + std::map> attrs_table; + + void add(const std::string &name, debug_item &&item, metadata_map &&item_attrs = {}) { + std::unique_ptr &attrs = attrs_table[name]; + if (attrs.get() == nullptr) + attrs = std::unique_ptr(new debug_attrs); + for (auto attr : item_attrs) + attrs->map.insert(attr); + item.attrs = attrs.get(); std::vector &parts = table[name]; parts.emplace_back(item); std::sort(parts.begin(), parts.end(), @@ -1246,6 +1274,10 @@ struct debug_items { const debug_item &operator [](const std::string &name) const { return at(name); } + + const metadata_map &attrs(const std::string &name) const { + return attrs_table.at(name)->map; + } }; // Tag class to disambiguate the default constructor used by the toplevel module that calls reset(), diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 7696ae5747c..3fd4857bd51 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -2120,6 +2120,46 @@ struct CxxrtlWorker { dec_indent(); } + void dump_metadata_map(const dict &metadata_map) + { + if (metadata_map.empty()) { + f << "metadata_map()"; + return; + } + f << "metadata_map({\n"; + inc_indent(); + for (auto metadata_item : metadata_map) { + if (!metadata_item.first.isPublic()) + continue; + if (metadata_item.second.size() > 64 && (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) == 0) { + f << indent << "/* attribute " << metadata_item.first.str().substr(1) << " is over 64 bits wide */"; + continue; + } + f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", "; + // In Yosys, a real is a type of string. + if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) { + f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint; + } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) { + f << escape_cxx_string(metadata_item.second.decode_string()); + } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED) { + f << "INT64_C(" << metadata_item.second.as_int(/*is_signed=*/true) << ")"; + } else { + f << "UINT64_C(" << metadata_item.second.as_int(/*is_signed=*/false) << ")"; + } + f << " },\n"; + } + dec_indent(); + f << indent << "})"; + } + + void dump_debug_attrs(const RTLIL::AttrObject *object) + { + dict attributes = object->attributes; + // Inherently necessary to get access to the object, so a waste of space to emit. + attributes.erase(ID::hdlname); + dump_metadata_map(attributes); + } + void dump_debug_info_method(RTLIL::Module *module) { size_t count_public_wires = 0; @@ -2205,7 +2245,9 @@ struct CxxrtlWorker { } f << "debug_item::" << flag; } - f << "));\n"; + f << "), "; + dump_debug_attrs(wire); + f << ");\n"; count_member_wires++; break; } @@ -2220,7 +2262,9 @@ struct CxxrtlWorker { f << "debug_eval_outline"; else f << "debug_alias()"; - f << ", " << mangle(aliasee) << ", " << wire->start_offset << "));\n"; + f << ", " << mangle(aliasee) << ", " << wire->start_offset << "), "; + dump_debug_attrs(aliasee); + f << ");\n"; count_alias_wires++; break; } @@ -2230,14 +2274,18 @@ struct CxxrtlWorker { dump_const(debug_wire_type.sig_subst.as_const()); f << ";\n"; f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire)); - f << ", debug_item(const_" << mangle(wire) << ", " << wire->start_offset << "));\n"; + f << ", debug_item(const_" << mangle(wire) << ", " << wire->start_offset << "), "; + dump_debug_attrs(wire); + f << ");\n"; count_const_wires++; break; } case WireType::OUTLINE: { // Localized or inlined, but rematerializable wire f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire)); - f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", " << wire->start_offset << "));\n"; + f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", " << wire->start_offset << "), "; + dump_debug_attrs(wire); + f << ");\n"; count_inline_wires++; break; } @@ -2254,7 +2302,13 @@ struct CxxrtlWorker { continue; f << indent << "items.add(path + " << escape_cxx_string(mem.packed ? get_hdl_name(mem.cell) : get_hdl_name(mem.mem)); f << ", debug_item(" << mangle(&mem) << ", "; - f << mem.start_offset << "));\n"; + f << mem.start_offset << "), "; + if (mem.packed) { + dump_debug_attrs(mem.cell); + } else { + dump_debug_attrs(mem.mem); + } + f << ");\n"; } for (auto cell : module->cells()) { if (is_internal_cell(cell->type)) @@ -2282,33 +2336,6 @@ struct CxxrtlWorker { } } - void dump_metadata_map(const dict &metadata_map) - { - if (metadata_map.empty()) { - f << "metadata_map()"; - return; - } - f << "metadata_map({\n"; - inc_indent(); - for (auto metadata_item : metadata_map) { - if (!metadata_item.first.begins_with("\\")) - continue; - f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", "; - if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) { - f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint; - } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) { - f << escape_cxx_string(metadata_item.second.decode_string()); - } else { - f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED); - if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED)) - f << "u"; - } - f << " },\n"; - } - dec_indent(); - f << indent << "})"; - } - void dump_module_intf(RTLIL::Module *module) { dump_attrs(module); diff --git a/backends/cxxrtl/cxxrtl_capi.cc b/backends/cxxrtl/cxxrtl_capi.cc index 227173ba87f..d50ddcd6941 100644 --- a/backends/cxxrtl/cxxrtl_capi.cc +++ b/backends/cxxrtl/cxxrtl_capi.cc @@ -90,3 +90,46 @@ void cxxrtl_enum(cxxrtl_handle handle, void *data, void cxxrtl_outline_eval(cxxrtl_outline outline) { outline->eval(); } + +int cxxrtl_attr_type(cxxrtl_attr_set attrs_, const char *name) { + auto attrs = (cxxrtl::metadata_map*)attrs_; + if (!attrs->count(name)) + return CXXRTL_ATTR_NONE; + switch (attrs->at(name).value_type) { + case cxxrtl::metadata::UINT: + return CXXRTL_ATTR_UNSIGNED_INT; + case cxxrtl::metadata::SINT: + return CXXRTL_ATTR_SIGNED_INT; + case cxxrtl::metadata::STRING: + return CXXRTL_ATTR_STRING; + case cxxrtl::metadata::DOUBLE: + return CXXRTL_ATTR_DOUBLE; + default: + // Present unsupported attribute type the same way as no attribute at all. + return CXXRTL_ATTR_NONE; + } +} + +uint64_t cxxrtl_attr_get_unsigned_int(cxxrtl_attr_set attrs_, const char *name) { + auto &attrs = *(cxxrtl::metadata_map*)attrs_; + assert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::UINT); + return attrs[name].as_uint(); +} + +int64_t cxxrtl_attr_get_signed_int(cxxrtl_attr_set attrs_, const char *name) { + auto &attrs = *(cxxrtl::metadata_map*)attrs_; + assert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::SINT); + return attrs[name].as_sint(); +} + +const char *cxxrtl_attr_get_string(cxxrtl_attr_set attrs_, const char *name) { + auto &attrs = *(cxxrtl::metadata_map*)attrs_; + assert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::STRING); + return attrs[name].as_string().c_str(); +} + +double cxxrtl_attr_get_double(cxxrtl_attr_set attrs_, const char *name) { + auto &attrs = *(cxxrtl::metadata_map*)attrs_; + assert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::DOUBLE); + return attrs[name].as_double(); +} diff --git a/backends/cxxrtl/cxxrtl_capi.h b/backends/cxxrtl/cxxrtl_capi.h index 2df2b7287f4..e5c84bf656a 100644 --- a/backends/cxxrtl/cxxrtl_capi.h +++ b/backends/cxxrtl/cxxrtl_capi.h @@ -249,6 +249,15 @@ struct cxxrtl_object { // this field to NULL. struct _cxxrtl_outline *outline; + // Opaque reference to an attribute set. + // + // See the documentation of `cxxrtl_attr_set` for details. When creating a `cxxrtl_object`, set + // this field to NULL. + // + // The lifetime of the pointers returned by `cxxrtl_attr_*` family of functions is the same as + // the lifetime of this structure. + struct _cxxrtl_attr_set *attrs; + // More description fields may be added in the future, but the existing ones will never change. }; @@ -304,6 +313,62 @@ typedef struct _cxxrtl_outline *cxxrtl_outline; // re-evaluated, otherwise the bits read from that object are meaningless. void cxxrtl_outline_eval(cxxrtl_outline outline); +// Opaque reference to an attribute set. +// +// An attribute set is a map between attribute names (always strings) and values (which may have +// several different types). To find out the type of an attribute, use `cxxrtl_attr_type`, and +// to retrieve the value of an attribute, use `cxxrtl_attr_as_string`. +typedef struct _cxxrtl_attr_set *cxxrtl_attr_set; + +// Type of an attribute. +enum cxxrtl_attr_type { + // Attribute is not present. + CXXRTL_ATTR_NONE = 0, + + // Attribute has an unsigned integer value. + CXXRTL_ATTR_UNSIGNED_INT = 1, + + // Attribute has an unsigned integer value. + CXXRTL_ATTR_SIGNED_INT = 2, + + // Attribute has a string value. + CXXRTL_ATTR_STRING = 3, + + // Attribute has a double precision floating point value. + CXXRTL_ATTR_DOUBLE = 4, + + // More attribute types may be defined in the future, but the existing values will never change. +}; + +// Determine the presence and type of an attribute in an attribute set. +// +// This function returns one of the possible `cxxrtl_attr_type` values. +int cxxrtl_attr_type(cxxrtl_attr_set attrs, const char *name); + +// Retrieve an unsigned integer valued attribute from an attribute set. +// +// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_UNSIGNED_INT`. +// If assertions are disabled, returns 0 if the attribute is missing or has an incorrect type. +uint64_t cxxrtl_attr_get_unsigned_int(cxxrtl_attr_set attrs, const char *name); + +// Retrieve a signed integer valued attribute from an attribute set. +// +// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_SIGNED_INT`. +// If assertions are disabled, returns 0 if the attribute is missing or has an incorrect type. +int64_t cxxrtl_attr_get_signed_int(cxxrtl_attr_set attrs, const char *name); + +// Retrieve a string valued attribute from an attribute set. The returned string is zero-terminated. +// +// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_STRING`. If assertions +// are disabled, returns NULL if the attribute is missing or has an incorrect type. +const char *cxxrtl_attr_get_string(cxxrtl_attr_set attrs, const char *name); + +// Retrieve a double precision floating point valued attribute from an attribute set. +// +// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_DOUBLE`. If assertions +// are disabled, returns NULL if the attribute is missing or has an incorrect type. +double cxxrtl_attr_get_double(cxxrtl_attr_set attrs, const char *name); + #ifdef __cplusplus } #endif From 672375ed02be68733856e616a5f4fbf281fe7733 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 26 Oct 2023 00:14:46 +0000 Subject: [PATCH 113/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b89c87ae943..670d44d32d7 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.34+43 +YOSYS_VER := 0.34+55 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From f9ab6e147a2c70eb826119235ee34fbe713624d8 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 30 Oct 2023 16:30:34 +0100 Subject: [PATCH 114/240] mem: only import attributes from ports if the memory doesn't have them yet --- kernel/mem.cc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/kernel/mem.cc b/kernel/mem.cc index 40345b81df1..01c866770f5 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -149,7 +149,8 @@ void Mem::emit() { wr_port_xlat.push_back(i); for (auto &port : rd_ports) { for (auto attr: port.attributes) - cell->attributes.insert(attr); + if (!cell->has_attribute(attr.first)) + cell->attributes.insert(attr); if (port.cell) { module->remove(port.cell); port.cell = nullptr; @@ -213,7 +214,8 @@ void Mem::emit() { cell->setPort(ID::RD_DATA, rd_data); for (auto &port : wr_ports) { for (auto attr: port.attributes) - cell->attributes.insert(attr); + if (!cell->has_attribute(attr.first)) + cell->attributes.insert(attr); if (port.cell) { module->remove(port.cell); port.cell = nullptr; @@ -251,7 +253,8 @@ void Mem::emit() { cell->setPort(ID::WR_DATA, wr_data); for (auto &init : inits) { for (auto attr: init.attributes) - cell->attributes.insert(attr); + if (!cell->has_attribute(attr.first)) + cell->attributes.insert(attr); if (init.cell) { module->remove(init.cell); init.cell = nullptr; From 4eb18e1f07cc24a7beabac83e862e0f236afbf97 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 1 Nov 2023 08:13:27 +0100 Subject: [PATCH 115/240] change verific log callback api --- frontends/verific/verific.cc | 4 ++-- kernel/log.cc | 2 +- kernel/log.h | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 115a42e332b..cc9b35e39bc 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -115,7 +115,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil if (log_verific_callback) { string full_message = stringf("%s%s\n", message_prefix.c_str(), message.c_str()); - log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), LineFile::GetLineNo(linefile), full_message.c_str()); + log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), linefile->GetLeftLine(), linefile->GetLeftCol(), linefile->GetRightLine(), linefile->GetRightCol(), full_message.c_str()); } else { if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR) log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str()); @@ -126,7 +126,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil verific_error_msg = message; } -void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg)) +void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)) { Message::SetConsoleOutput(0); Message::RegisterCallBackMsg(msg_func); diff --git a/kernel/log.cc b/kernel/log.cc index 73e7f16eca5..9a61e8f08b3 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -59,7 +59,7 @@ bool log_quiet_warnings = false; int log_verbose_level; string log_last_error; void (*log_error_atexit)() = NULL; -void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg) = NULL; +void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg) = NULL; int log_make_debug = 0; int log_force_debug = 0; diff --git a/kernel/log.h b/kernel/log.h index 78a2e434c7a..e4f06c69d19 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -131,8 +131,8 @@ void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(for void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); -void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg)); -extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg); +void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)); +extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg); // Log with filename to report a problem in a source file. void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); From f06d56d2243272d5f56813f9d07125bfb4d4ab7c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 3 Nov 2023 08:06:16 +0100 Subject: [PATCH 116/240] Handling non-existing location in verific logs --- frontends/verific/verific.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index cc9b35e39bc..3e73462f120 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -115,7 +115,9 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil if (log_verific_callback) { string full_message = stringf("%s%s\n", message_prefix.c_str(), message.c_str()); - log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), linefile->GetLeftLine(), linefile->GetLeftCol(), linefile->GetRightLine(), linefile->GetRightCol(), full_message.c_str()); + log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), + linefile ? linefile->GetLeftLine() : 0, linefile ? linefile->GetLeftCol() : 0, + linefile ? linefile->GetRightLine() : 0, linefile ? linefile->GetRightCol() : 0, full_message.c_str()); } else { if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR) log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str()); From 32082477b50aaeb89101249daa52d9de48d3237b Mon Sep 17 00:00:00 2001 From: Lofty Date: Thu, 2 Nov 2023 19:05:41 +0000 Subject: [PATCH 117/240] ice40, ecp5: enable ABC9 by default --- techlibs/ecp5/synth_ecp5.cc | 12 ++++++++---- techlibs/ice40/synth_ice40.cc | 12 ++++++++---- tests/arch/ecp5/add_sub.ys | 7 +++++-- tests/arch/ecp5/counter.ys | 3 ++- tests/arch/ice40/add_sub.ys | 2 +- tests/arch/ice40/mux.ys | 8 ++++---- 6 files changed, 28 insertions(+), 16 deletions(-) diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index fdc36e55267..f6215987f7f 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -93,8 +93,8 @@ struct SynthEcp5Pass : public ScriptPass log(" -abc2\n"); log(" run two passes of 'abc' for slightly improved logic density\n"); log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log(" -noabc9\n"); + log(" disable use of new ABC9 flow\n"); log("\n"); log(" -vpr\n"); log(" generate an output netlist (and BLIF file) suitable for VPR\n"); @@ -137,7 +137,7 @@ struct SynthEcp5Pass : public ScriptPass retime = false; abc2 = false; vpr = false; - abc9 = false; + abc9 = true; iopad = false; nodsp = false; no_rw_check = false; @@ -224,7 +224,11 @@ struct SynthEcp5Pass : public ScriptPass continue; } if (args[argidx] == "-abc9") { - abc9 = true; + // removed, ABC9 is on by default. + continue; + } + if (args[argidx] == "-noabc9") { + abc9 = false; continue; } if (args[argidx] == "-iopad") { diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 2ae859efe32..a9982649b35 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -106,8 +106,8 @@ struct SynthIce40Pass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log(" -noabc9\n"); + log(" disable use of new ABC9 flow\n"); log("\n"); log(" -flowmap\n"); log(" use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n"); @@ -144,7 +144,7 @@ struct SynthIce40Pass : public ScriptPass noabc = false; abc2 = false; vpr = false; - abc9 = false; + abc9 = true; flowmap = false; device_opt = "hx"; no_rw_check = false; @@ -235,7 +235,11 @@ struct SynthIce40Pass : public ScriptPass continue; } if (args[argidx] == "-abc9") { - abc9 = true; + // removed, ABC9 is on by default. + continue; + } + if (args[argidx] == "-noabc9") { + abc9 = false; continue; } if (args[argidx] == "-dff") { diff --git a/tests/arch/ecp5/add_sub.ys b/tests/arch/ecp5/add_sub.ys index d85ce792ee6..c3ce8c56dae 100644 --- a/tests/arch/ecp5/add_sub.ys +++ b/tests/arch/ecp5/add_sub.ys @@ -4,6 +4,9 @@ proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:LUT4 -select -assert-none t:LUT4 %% t:* %D +select -assert-min 25 t:LUT4 +select -assert-max 26 t:LUT4 +select -assert-count 10 t:PFUMX +select -assert-count 6 t:L6MUX21 +select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D diff --git a/tests/arch/ecp5/counter.ys b/tests/arch/ecp5/counter.ys index e46001ffede..e3f713228c3 100644 --- a/tests/arch/ecp5/counter.ys +++ b/tests/arch/ecp5/counter.ys @@ -5,6 +5,7 @@ flatten equiv_opt -assert -multiclock -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 select -assert-count 4 t:CCU2C select -assert-count 8 t:TRELLIS_FF -select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D +select -assert-none t:LUT4 t:CCU2C t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/ice40/add_sub.ys b/tests/arch/ice40/add_sub.ys index 578ec080380..74b83b8ee91 100644 --- a/tests/arch/ice40/add_sub.ys +++ b/tests/arch/ice40/add_sub.ys @@ -3,7 +3,7 @@ hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 11 t:SB_LUT4 +select -assert-count 10 t:SB_LUT4 select -assert-count 6 t:SB_CARRY select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys index 2b661fd6b1a..977d6975063 100644 --- a/tests/arch/ice40/mux.ys +++ b/tests/arch/ice40/mux.ys @@ -15,7 +15,7 @@ proc equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 2 t:SB_LUT4 +select -assert-count 3 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D @@ -25,7 +25,7 @@ proc equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 5 t:SB_LUT4 +select -assert-count 6 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D @@ -35,7 +35,7 @@ proc equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-min 11 t:SB_LUT4 -select -assert-max 12 t:SB_LUT4 +select -assert-min 13 t:SB_LUT4 +select -assert-max 14 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D From ea91f189a3db214fbb5c747ca1e6a24b7c3e5494 Mon Sep 17 00:00:00 2001 From: anonkey <6380129+anonkey@users.noreply.github.com> Date: Mon, 2 Oct 2023 17:18:33 +0200 Subject: [PATCH 118/240] cli(tcl): add ability to pass argument to tcl script from cli --- CHANGELOG | 4 ++++ kernel/driver.cc | 52 ++++++++++++++++++++++++++++++++++-------------- 2 files changed, 41 insertions(+), 15 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index ee5f6b43d25..eac68b1ed6d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -4,6 +4,10 @@ List of major changes and improvements between releases Yosys 0.34 .. Yosys 0.35-dev -------------------------- +* New commands and options + - Added option "--" to pass arguments down to tcl when using -c option. + - Added ability on MacOS and Windows to pass options after arguments on cli. + Yosys 0.33 .. Yosys 0.34 -------------------------- diff --git a/kernel/driver.cc b/kernel/driver.cc index ef8e7792473..661400e7aff 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -49,39 +49,47 @@ # include #endif -#if !defined(_WIN32) || defined(__MINGW32__) -# include -#else char *optarg; -int optind = 1, optcur = 1; +int optind = 1, optcur = 1, optopt = 0; int getopt(int argc, char **argv, const char *optstring) { - if (optind >= argc || argv[optind][0] != '-') + if (optind >= argc) return -1; + if (argv[optind][0] != '-') { + optopt = 1; + optarg = argv[optind++]; + return optopt; + } + bool takes_arg = false; - int opt = argv[optind][optcur]; + optopt = argv[optind][optcur]; + + if (optopt == '-') { + ++optind; + return -1; + } + for (int i = 0; optstring[i]; i++) - if (opt == optstring[i] && optstring[i + 1] == ':') + if (optopt == optstring[i] && optstring[i + 1] == ':') takes_arg = true; if (!takes_arg) { if (argv[optind][++optcur] == 0) optind++, optcur = 1; - return opt; + return optopt; } if (argv[optind][++optcur]) { optarg = argv[optind++] + optcur; optcur = 1; - return opt; + return optopt; } optarg = argv[++optind]; optind++, optcur = 1; - return opt; + return optopt; } -#endif USING_YOSYS_NAMESPACE @@ -215,6 +223,7 @@ int main(int argc, char **argv) std::string backend_command = "auto"; std::vector vlog_defines; std::vector passes_commands; + std::vector frontend_files; std::vector plugin_filenames; std::string output_filename = ""; std::string scriptfile = ""; @@ -509,6 +518,9 @@ int main(int argc, char **argv) case 'C': run_tcl_shell = true; break; + case '\001': + frontend_files.push_back(optarg); + break; default: fprintf(stderr, "Run '%s -h' for help.\n", argv[0]); exit(1); @@ -561,17 +573,27 @@ int main(int argc, char **argv) run_pass(vdef_cmd); } - while (optind < argc) - if (run_frontend(argv[optind++], frontend_command)) + for (auto it = frontend_files.begin(); it != frontend_files.end(); ++it) { + if (run_frontend((*it).c_str(), frontend_command)) run_shell = false; + } if (!topmodule.empty()) run_pass("hierarchy -top " + topmodule); - if (!scriptfile.empty()) { if (scriptfile_tcl) { #ifdef YOSYS_ENABLE_TCL - if (Tcl_EvalFile(yosys_get_tcl_interp(), scriptfile.c_str()) != TCL_OK) + int tcl_argc = argc - optind; + std::vector script_args; + Tcl_Interp *interp = yosys_get_tcl_interp(); + for (int i = optind; i < argc; ++i) + script_args.push_back(Tcl_NewStringObj(argv[i], strlen(argv[i]))); + + Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argc", 4), NULL, Tcl_NewIntObj(tcl_argc), 0); + Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argv", 4), NULL, Tcl_NewListObj(tcl_argc, script_args.data()), 0); + Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argv0", 5), NULL, Tcl_NewStringObj(scriptfile.c_str(), scriptfile.length()), 0); + + if (Tcl_EvalFile(interp, scriptfile.c_str()) != TCL_OK) log_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(yosys_get_tcl_interp())); #else log_error("Can't exectue TCL script: this version of yosys is not built with TCL support enabled.\n"); From b8b47f7c6c191e14ce350c7fcd579a88fdc3fd26 Mon Sep 17 00:00:00 2001 From: Lofty Date: Fri, 3 Nov 2023 14:52:52 +0000 Subject: [PATCH 119/240] Revert "ice40, ecp5: enable ABC9 by default" --- techlibs/ecp5/synth_ecp5.cc | 12 ++++-------- techlibs/ice40/synth_ice40.cc | 12 ++++-------- tests/arch/ecp5/add_sub.ys | 7 ++----- tests/arch/ecp5/counter.ys | 3 +-- tests/arch/ice40/add_sub.ys | 2 +- tests/arch/ice40/mux.ys | 8 ++++---- 6 files changed, 16 insertions(+), 28 deletions(-) diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index f6215987f7f..fdc36e55267 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -93,8 +93,8 @@ struct SynthEcp5Pass : public ScriptPass log(" -abc2\n"); log(" run two passes of 'abc' for slightly improved logic density\n"); log("\n"); - log(" -noabc9\n"); - log(" disable use of new ABC9 flow\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); log(" -vpr\n"); log(" generate an output netlist (and BLIF file) suitable for VPR\n"); @@ -137,7 +137,7 @@ struct SynthEcp5Pass : public ScriptPass retime = false; abc2 = false; vpr = false; - abc9 = true; + abc9 = false; iopad = false; nodsp = false; no_rw_check = false; @@ -224,11 +224,7 @@ struct SynthEcp5Pass : public ScriptPass continue; } if (args[argidx] == "-abc9") { - // removed, ABC9 is on by default. - continue; - } - if (args[argidx] == "-noabc9") { - abc9 = false; + abc9 = true; continue; } if (args[argidx] == "-iopad") { diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index a9982649b35..2ae859efe32 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -106,8 +106,8 @@ struct SynthIce40Pass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); - log(" -noabc9\n"); - log(" disable use of new ABC9 flow\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); log(" -flowmap\n"); log(" use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n"); @@ -144,7 +144,7 @@ struct SynthIce40Pass : public ScriptPass noabc = false; abc2 = false; vpr = false; - abc9 = true; + abc9 = false; flowmap = false; device_opt = "hx"; no_rw_check = false; @@ -235,11 +235,7 @@ struct SynthIce40Pass : public ScriptPass continue; } if (args[argidx] == "-abc9") { - // removed, ABC9 is on by default. - continue; - } - if (args[argidx] == "-noabc9") { - abc9 = false; + abc9 = true; continue; } if (args[argidx] == "-dff") { diff --git a/tests/arch/ecp5/add_sub.ys b/tests/arch/ecp5/add_sub.ys index c3ce8c56dae..d85ce792ee6 100644 --- a/tests/arch/ecp5/add_sub.ys +++ b/tests/arch/ecp5/add_sub.ys @@ -4,9 +4,6 @@ proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-min 25 t:LUT4 -select -assert-max 26 t:LUT4 -select -assert-count 10 t:PFUMX -select -assert-count 6 t:L6MUX21 -select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D diff --git a/tests/arch/ecp5/counter.ys b/tests/arch/ecp5/counter.ys index e3f713228c3..e46001ffede 100644 --- a/tests/arch/ecp5/counter.ys +++ b/tests/arch/ecp5/counter.ys @@ -5,7 +5,6 @@ flatten equiv_opt -assert -multiclock -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:LUT4 select -assert-count 4 t:CCU2C select -assert-count 8 t:TRELLIS_FF -select -assert-none t:LUT4 t:CCU2C t:TRELLIS_FF %% t:* %D +select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/ice40/add_sub.ys b/tests/arch/ice40/add_sub.ys index 74b83b8ee91..578ec080380 100644 --- a/tests/arch/ice40/add_sub.ys +++ b/tests/arch/ice40/add_sub.ys @@ -3,7 +3,7 @@ hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:SB_LUT4 +select -assert-count 11 t:SB_LUT4 select -assert-count 6 t:SB_CARRY select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys index 977d6975063..2b661fd6b1a 100644 --- a/tests/arch/ice40/mux.ys +++ b/tests/arch/ice40/mux.ys @@ -15,7 +15,7 @@ proc equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 3 t:SB_LUT4 +select -assert-count 2 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D @@ -25,7 +25,7 @@ proc equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 6 t:SB_LUT4 +select -assert-count 5 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D @@ -35,7 +35,7 @@ proc equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-min 13 t:SB_LUT4 -select -assert-max 14 t:SB_LUT4 +select -assert-min 11 t:SB_LUT4 +select -assert-max 12 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D From 6f1ca68712e7713952440a36b25a9b6848f1a749 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 4 Nov 2023 00:14:46 +0000 Subject: [PATCH 120/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 670d44d32d7..ca822a58592 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.34+55 +YOSYS_VER := 0.34+60 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 72c6a01e6743d21937cf407abe19a75850f8a9d4 Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Mon, 6 Nov 2023 14:01:37 +0100 Subject: [PATCH 121/240] peepopt: Add initial `shiftadd` pattern --- passes/pmgen/Makefile.inc | 1 + passes/pmgen/peepopt.cc | 1 + passes/pmgen/peepopt_shiftadd.pmg | 116 ++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 passes/pmgen/peepopt_shiftadd.pmg diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index c2257b72083..884e1252224 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -44,6 +44,7 @@ $(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h)) PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul_right.pmg PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftmul_left.pmg +PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftadd.pmg PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN) diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index aef464d79c9..b4394dfd4b5 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -72,6 +72,7 @@ struct PeepoptPass : public Pass { pm.setup(module->selected_cells()); + pm.run_shiftadd(); pm.run_shiftmul_right(); pm.run_shiftmul_left(); pm.run_muldiv(); diff --git a/passes/pmgen/peepopt_shiftadd.pmg b/passes/pmgen/peepopt_shiftadd.pmg new file mode 100644 index 00000000000..1723104996f --- /dev/null +++ b/passes/pmgen/peepopt_shiftadd.pmg @@ -0,0 +1,116 @@ +pattern shiftadd +// +// Transforms add/sub+shift pairs that result from expressions such as data[s*W +C +:W2] +// specifically something like: out[W2-1:0] = data >> (s*W +C) +// will be transformed into: out[W2-1:0] = (data >> C) >> (s*W) +// this can then be optimized using peepopt_shiftmul_right.pmg +// + +match shift + select shift->type.in($shift, $shiftx, $shr) + filter !port(shift, \B).empty() +endmatch + +// the right shift amount +state shift_amount +// log2 scale factor in interpreting of shift_amount +// due to zero padding on the shift cell's B port +state log2scale +// zeros at the MSB position make it unsigned +state msb_zeros + +code shift_amount log2scale msb_zeros + shift_amount = port(shift, \B); + + log2scale = 0; + while (shift_amount[0] == State::S0) { + shift_amount.remove(0); + if (shift_amount.empty()) reject; + log2scale++; + } + + msb_zeros = 0; + while (shift_amount.bits().back() == State::S0) { + msb_zeros = true; + shift_amount.remove(GetSize(shift_amount) - 1); + if (shift_amount.empty()) reject; + } + + if (GetSize(shift_amount) > 20) + reject; +endcode + +state add_var +state add_const +state is_sub +state varport_A + +match add + // either data[var+c +:W1] or data[var-c +:W1] + select add->type.in($add, $sub) + index port(add, \Y) === shift_amount + + // one must be constant, the other is variable + choice constport {\A, \B} + filter port(add, constport).is_fully_const() + define varport (constport == \A ? \B : \A) + + set is_sub add->type.in($sub) + set varport_A (varport == \A) + + // (var+c)< (var<getPort(varport) +endmatch + +code +{ + log_debug("shiftadd candidate in %s: shift=%s, add/sub=%s\n", log_id(module), log_id(shift), log_id(add)); + if (add_const.empty() || GetSize(add_const) > 20) + reject; + + int offset = add_const.as_int() * ( (is_sub && varport_A) ? -1 : 1 ); + bool varport_signed = (varport_A && param(add, \A_SIGNED).as_bool()) \ + || (!varport_A && param(add, \B_SIGNED).as_bool()); + + // data[...-c +:W1] is fine for +/-var (pad at LSB, all data still accessible) + // data[...+c +:W1] is only fine for +var(add) and var unsigned + // (+c cuts lower C bits, making them inaccessible, a signed var could try to access them) + // -> data[c-var +:W1] is illegal + if (is_sub && !varport_A) + reject; + // -> data[var+c +:W1] (with var signed) is illegal + if ( (offset>0) && varport_signed ) + reject; + + did_something = true; + log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \ + log_id(module), log_id(shift), log_id(add), offset); + + SigSpec old_a = port(shift, \A), new_a; + if(offset<0) { + // data >> (...-c) transformed to {data, c'X} >> (...) + SigSpec padding( (shift->type.in($shiftx) ? State::Sx : State::S0), -offset ); + new_a.append(padding); + new_a.append(old_a); + } else { + // data >> (...+c) transformed to data[MAX:c] >> (...) + new_a.append(old_a.extract(offset, GetSize(old_a)-1-offset)); + + } + + SigSpec new_b = {add_var, SigSpec(State::S0, log2scale)}; + if (msb_zeros || !varport_signed) + new_b.append(State::S0); + + shift->setPort(\A, new_a); + shift->setParam(\A_WIDTH, GetSize(new_a)); + shift->setPort(\B, new_b); + shift->setParam(\B_WIDTH, GetSize(new_b)); + blacklist(add); + accept; +} +endcode From 9ca57d9f1312ccd8cd889031805afdb434ca46f2 Mon Sep 17 00:00:00 2001 From: phsauter Date: Mon, 6 Nov 2023 14:01:37 +0100 Subject: [PATCH 122/240] peepopt: fix and refactor `shiftadd` - moved all selection and filtering logic to the match block - applied less-verbose code suggestions - removed constraint on number of bits in shift-amount - added check for possible wrap-arround in the operation --- passes/pmgen/peepopt_shiftadd.pmg | 70 ++++++++++++++++--------------- 1 file changed, 37 insertions(+), 33 deletions(-) diff --git a/passes/pmgen/peepopt_shiftadd.pmg b/passes/pmgen/peepopt_shiftadd.pmg index 1723104996f..25f0756da8e 100644 --- a/passes/pmgen/peepopt_shiftadd.pmg +++ b/passes/pmgen/peepopt_shiftadd.pmg @@ -35,15 +35,12 @@ code shift_amount log2scale msb_zeros shift_amount.remove(GetSize(shift_amount) - 1); if (shift_amount.empty()) reject; } - - if (GetSize(shift_amount) > 20) - reject; endcode -state add_var -state add_const -state is_sub -state varport_A +state var_signed +state var_signal +// offset: signed constant value c in data[var+c +:W1] (constant shift-right amount) +state offset match add // either data[var+c +:W1] or data[var-c +:W1] @@ -52,39 +49,46 @@ match add // one must be constant, the other is variable choice constport {\A, \B} - filter port(add, constport).is_fully_const() + select !port(add, constport).empty() + select port(add, constport).is_fully_const() define varport (constport == \A ? \B : \A) - set is_sub add->type.in($sub) - set varport_A (varport == \A) + // if a value of var is able to wrap the output, the transformation might give wrong results + // an addition/substraction can at most flip one more bit than the largest operand (the carry bit) + // as long as the output can show this bit, no wrap should occur (assuming all signed-ness make sense) + select ( GetSize(port(add, \Y)) > max(GetSize(port(add, \A)), GetSize(port(add, \B))) ) - // (var+c)< (var< varport_A (varport == \A) + define is_sub add->type.in($sub) - // get add_var unmapped (so no `port()` shorthand) - // to attach it to the transformed shift cells \B port - set add_var add->getPort(varport) -endmatch - -code -{ - log_debug("shiftadd candidate in %s: shift=%s, add/sub=%s\n", log_id(module), log_id(shift), log_id(add)); - if (add_const.empty() || GetSize(add_const) > 20) - reject; - - int offset = add_const.as_int() * ( (is_sub && varport_A) ? -1 : 1 ); - bool varport_signed = (varport_A && param(add, \A_SIGNED).as_bool()) \ - || (!varport_A && param(add, \B_SIGNED).as_bool()); + define constport_signed param(add, !varport_A ? \A_SIGNED : \B_SIGNED).as_bool() + define varport_signed param(add, varport_A ? \A_SIGNED : \B_SIGNED).as_bool(); + define offset_negative ((port(add, constport).bits().back() == State::S1) ^ (is_sub && varport_A)) + // checking some value boundaries as well: // data[...-c +:W1] is fine for +/-var (pad at LSB, all data still accessible) // data[...+c +:W1] is only fine for +var(add) and var unsigned // (+c cuts lower C bits, making them inaccessible, a signed var could try to access them) - // -> data[c-var +:W1] is illegal - if (is_sub && !varport_A) - reject; + // either its an add or the variable port is A (it must be positive) + select (add->type.in($add) || varport == \A) + // -> data[var+c +:W1] (with var signed) is illegal - if ( (offset>0) && varport_signed ) + filter !(!offset_negative && varport_signed) + + // state-variables are assigned at the end only: + // shift the log2scale offset in-front of add to get true value: (var+c)< (var<getPort(varport) +endmatch + +code +{ + if (offset>0 && var_signed) { + log("I should not be here %x\n", var_signed); reject; + } did_something = true; log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \ @@ -98,12 +102,12 @@ code new_a.append(old_a); } else { // data >> (...+c) transformed to data[MAX:c] >> (...) - new_a.append(old_a.extract(offset, GetSize(old_a)-1-offset)); + new_a.append(old_a.extract_end(offset)); } - SigSpec new_b = {add_var, SigSpec(State::S0, log2scale)}; - if (msb_zeros || !varport_signed) + SigSpec new_b = {var_signal, SigSpec(State::S0, log2scale)}; + if (msb_zeros || !var_signed) new_b.append(State::S0); shift->setPort(\A, new_a); From b6df900bcc97beb190207f69475fdfada1d94229 Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Mon, 6 Nov 2023 14:01:37 +0100 Subject: [PATCH 123/240] peepopt: Describe `shiftadd` rule in help message --- passes/pmgen/peepopt.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index b4394dfd4b5..edd3b18a815 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -48,6 +48,9 @@ struct PeepoptPass : public Pass { log(" Analogously, replace A<<(B*C) with appropriate selection of\n"); log(" output bits from A<<(B<>(B+D) with (A'>>D)>>(B) where D is constant and\n"); + log(" A' is derived from A by padding or cutting inaccessible bits.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { From c3b8de54dae39a67046875dbc540da59bc45d342 Mon Sep 17 00:00:00 2001 From: phsauter Date: Mon, 6 Nov 2023 14:01:37 +0100 Subject: [PATCH 124/240] test: add tests for `shiftadd` and `shiftmul` This expands the part-select tests with one additional module. It specifically tests the different variants of the `peepopt` optimizations `shiftadd` and `shiftmul`. Not all these cases are actually transformed using `shiftadd`, including them also checks if the correct variants are rejected. --- tests/simple/partsel.v | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v index 5e9730d6bd1..722ed7b1bd9 100644 --- a/tests/simple/partsel.v +++ b/tests/simple/partsel.v @@ -110,3 +110,42 @@ module partsel_test007 ( dout[n+1] = din[n]; end endmodule + + +module partsel_test008 ( + input [127:0] din, + input [3:0] idx, + input [4:0] uoffset, + input signed [4:0] soffset, + output [ 7:0] dout0, + output [ 7:0] dout1, + output [ 7:0] dout2, + output [ 7:0] dout3, + output [ 3:0] dout4, + output [ 3:0] dout5, + output [ 3:0] dout6, + output [ 3:0] dout7, + output [ 3:0] dout8, + output [11:0] dout9, + output [11:0] dout10, + output [11:0] dout11 +); + +// common: block-select with offsets +assign dout0 = din[idx*8 +uoffset +:8]; +assign dout1 = din[idx*8 -uoffset +:8]; +assign dout2 = din[idx*8 +soffset +:8]; +assign dout3 = din[idx*8 -soffset +:8]; + +// only partial block used +assign dout4 = din[idx*8 +uoffset +:4]; +assign dout5 = din[idx*8 -uoffset +:4]; +assign dout6 = din[idx*8 +soffset +:4]; +assign dout7 = din[idx*8 -soffset +:4]; + +// uncommon: more than one block used +assign dout8 = din[idx*8 +uoffset +:12]; +assign dout9 = din[idx*8 -uoffset +:12]; +assign dout10 = din[idx*8 +soffset +:12]; +assign dout11 = din[idx*8 -soffset +:12]; +endmodule From 3618294bacbb5b3a2514e5ef69effb0f82c321af Mon Sep 17 00:00:00 2001 From: phsauter Date: Mon, 6 Nov 2023 16:35:00 +0100 Subject: [PATCH 125/240] peepopt: Add assert of consistent `shiftadd` data --- passes/pmgen/peepopt_shiftadd.pmg | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/passes/pmgen/peepopt_shiftadd.pmg b/passes/pmgen/peepopt_shiftadd.pmg index 25f0756da8e..f9c930eae3d 100644 --- a/passes/pmgen/peepopt_shiftadd.pmg +++ b/passes/pmgen/peepopt_shiftadd.pmg @@ -85,10 +85,11 @@ endmatch code { - if (offset>0 && var_signed) { - log("I should not be here %x\n", var_signed); - reject; - } + // positive constant offset with a signed variable (index) cannot be handled + // the above filter should get rid of this case but 'offset' is calculated differently + // due to limitations of state-variables in pmgen + // it should only differ if previous passes create invalid data + log_assert(!(offset>0 && var_signed)); did_something = true; log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \ From d415b4d98a0ac7d5177e3b5844477e8460bfa862 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 6 Nov 2023 16:40:13 +0100 Subject: [PATCH 126/240] cli: Cleanups for tcl argument handling * Keep the previous behavior when no tcl script is used * Do not treat "-" as a flag but as a positional argument * Keep including as it's also used for other functions (at least for the emscripten build) * Move the custom getopt implementation into the Yosys namespace to avoid potential collisions --- kernel/driver.cc | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index 661400e7aff..c779611e097 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -49,6 +49,12 @@ # include #endif +#if !defined(_WIN32) || defined(__MINGW32__) +# include +#endif + +USING_YOSYS_NAMESPACE + char *optarg; int optind = 1, optcur = 1, optopt = 0; int getopt(int argc, char **argv, const char *optstring) @@ -56,7 +62,7 @@ int getopt(int argc, char **argv, const char *optstring) if (optind >= argc) return -1; - if (argv[optind][0] != '-') { + if (argv[optind][0] != '-' || argv[optind][1] == 0) { optopt = 1; optarg = argv[optind++]; return optopt; @@ -91,9 +97,6 @@ int getopt(int argc, char **argv, const char *optstring) return optopt; } - -USING_YOSYS_NAMESPACE - #ifdef EMSCRIPTEN # include # include @@ -573,6 +576,12 @@ int main(int argc, char **argv) run_pass(vdef_cmd); } + if (scriptfile.empty() || !scriptfile_tcl) { + // Without a TCL script, arguments following '--' are also treated as frontend files + for (int i = optind; i < argc; ++i) + frontend_files.push_back(argv[i]); + } + for (auto it = frontend_files.begin(); it != frontend_files.end(); ++it) { if (run_frontend((*it).c_str(), frontend_command)) run_shell = false; From cc31c6ebc450f0dfe991663376c4e0b94944188b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 7 Nov 2023 08:45:31 +0100 Subject: [PATCH 127/240] Release version 0.35 --- CHANGELOG | 10 +++++++++- Makefile | 4 ++-- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index ee5f6b43d25..528ca2a32c0 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,8 +2,16 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.34 .. Yosys 0.35-dev +Yosys 0.34 .. Yosys 0.35 -------------------------- + * Various + - Improvements on "peepopt" shiftmul matcher. + - Improvements on "ram_style" attributes handling. + + * Verific support + - Improved static elaboration for VHDL and mixed HDL designs. + - Expose "hdlname" attribute with original module name. + - Expose "architecture" attribute with VHDL architecture name. Yosys 0.33 .. Yosys 0.34 -------------------------- diff --git a/Makefile b/Makefile index ca822a58592..0de05b62203 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.34+60 +YOSYS_VER := 0.35 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -157,7 +157,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 4a1b559.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 4a1b559.. | wc -l`/;" Makefile # set 'ABCREV = default' to use abc/ as it is # From 8808da243ba68af2fb22b311beef83111089ec77 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 7 Nov 2023 08:47:34 +0100 Subject: [PATCH 128/240] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 528ca2a32c0..57abcbab26e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.35 .. Yosys 0.36-dev +-------------------------- + Yosys 0.34 .. Yosys 0.35 -------------------------- * Various diff --git a/Makefile b/Makefile index 0de05b62203..83ea7a649e7 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.35 +YOSYS_VER := 0.35+0 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -157,7 +157,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: -# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 4a1b559.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline cc31c6e.. | wc -l`/;" Makefile # set 'ABCREV = default' to use abc/ as it is # From ee3a4ce14dce584afeba4003232e934488c2701b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 7 Nov 2023 16:21:39 +0100 Subject: [PATCH 129/240] synth_lattice: Merge NOT gates on DFF control signals `dfflegalize` will emit NOT gates to drive control signals on flip-flops when mapping to supported flip-flop polarities. Typically in a design this will produce a number of NOT gates driven by the same signal. For one reason or another ABC doesn't fully cancel this redundancy during LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis QoR. --- techlibs/lattice/synth_lattice.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index e2987d0259e..7ecfb95de7a 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -409,6 +409,7 @@ struct SynthLatticePass : public ScriptPass dfflegalize_args += " -cell $_DLATCH_?_ x"; } run("dfflegalize" + dfflegalize_args, "($_ALDFF_*_ only if -asyncprld, $_DLATCH_* only if not -asyncprld, $_*DFFE_* only if not -nodffe)"); + run("opt_merge"); if ((abc9 && dff) || help_mode) run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff)"); run("techmap -D NO_LUT -map +/lattice/cells_map.v"); From fed272099958bfc29dadec0ee366d20056171c00 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 7 Nov 2023 16:25:20 +0100 Subject: [PATCH 130/240] synth_lattice: Optimize flip-flop memories better After `memory_map` maps memories to flip-flops we need to let `opt` remove undef muxes, otherwise we block enable/reset signal inference by `opt_dff` which is in detriment to QoR. --- techlibs/lattice/synth_lattice.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index 7ecfb95de7a..738ef0334bd 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -373,7 +373,7 @@ struct SynthLatticePass : public ScriptPass { run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); - run("opt -undriven -fine"); + run("opt -undriven -fine -mux_undef"); } if (check_label("map_gates")) From 5691cd095848f89f9f84a29f267fdebe95bae832 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 8 Nov 2023 00:15:30 +0000 Subject: [PATCH 131/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 83ea7a649e7..3e6f05d4e48 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.35+0 +YOSYS_VER := 0.35+7 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 83d2f4f334708ae80592a13dfc71acc416fc1655 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 13 Nov 2023 16:29:52 +1300 Subject: [PATCH 132/240] techlibs: fix typo in help message --- techlibs/achronix/synth_achronix.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc index 9a0a7a3b57b..2b969182eaf 100644 --- a/techlibs/achronix/synth_achronix.cc +++ b/techlibs/achronix/synth_achronix.cc @@ -26,7 +26,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct SynthAchronixPass : public ScriptPass { - SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { } + SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Achronix Speedster22i FPGAs.") { } void help() override { From f7d4a855c66e53d082afc8477ddba46fe1d6d5b0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 13 Nov 2023 10:41:31 +0100 Subject: [PATCH 133/240] techlibs: Add `cmp2softlogic.v` to common --- techlibs/common/Makefile.inc | 1 + techlibs/common/cmp2softlogic.v | 117 ++++++++++++++++++++++++++++++++ 2 files changed, 118 insertions(+) create mode 100644 techlibs/common/cmp2softlogic.v diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index 47f1ed60456..6b377855e3e 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -34,3 +34,4 @@ $(eval $(call add_share_file,share,techlibs/common/abc9_model.v)) $(eval $(call add_share_file,share,techlibs/common/abc9_map.v)) $(eval $(call add_share_file,share,techlibs/common/abc9_unmap.v)) $(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v)) +$(eval $(call add_share_file,share,techlibs/common/cmp2softlogic.v)) diff --git a/techlibs/common/cmp2softlogic.v b/techlibs/common/cmp2softlogic.v new file mode 100644 index 00000000000..e480b4eee99 --- /dev/null +++ b/techlibs/common/cmp2softlogic.v @@ -0,0 +1,117 @@ +module constgtge(C, A, B, Y); +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; + +(* force_downto *) +input [A_WIDTH-1:0] A; +(* force_downto *) +input [B_WIDTH-1:0] B; +output Y; +input C; + +wire [A_WIDTH:0] ch; +genvar n; +generate + if (B_WIDTH > A_WIDTH) begin + // Fail + end else begin + assign ch[0] = C; + for (n = 0; n < A_WIDTH; n = n + 1) begin + if (n < B_WIDTH) begin + assign ch[n + 1] = B[n] ? (ch[n] && A[n]) : (ch[n] || A[n]); + end else begin + assign ch[n + 1] = ch[n] || A[n]; + end + end + assign Y = ch[A_WIDTH]; + end +endgenerate +endmodule + +module constltle(C, A, B, Y); +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; + +(* force_downto *) +input [A_WIDTH-1:0] A; +(* force_downto *) +input [B_WIDTH-1:0] B; +output Y; +input C; + +wire [A_WIDTH:0] ch; +genvar n; +generate + if (B_WIDTH > A_WIDTH) begin + // Fail + end else begin + assign ch[0] = C; + for (n = 0; n < A_WIDTH; n = n + 1) begin + if (n < B_WIDTH) begin + assign ch[n + 1] = !B[n] ? (ch[n] && !A[n]) : (ch[n] || !A[n]); + end else begin + assign ch[n + 1] = ch[n] && !A[n]; + end + end + assign Y = ch[A_WIDTH]; + end +endgenerate +endmodule + +(* techmap_celltype = "$ge $gt $le $lt" *) +module _map_const_cmp_(A, B, Y); +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; +parameter Y_WIDTH = 0; +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; + +(* force_downto *) +input [A_WIDTH-1:0] A; +(* force_downto *) +input [B_WIDTH-1:0] B; +(* force_downto *) +output [Y_WIDTH-1:0] Y; + +parameter _TECHMAP_CELLTYPE_ = ""; + +parameter _TECHMAP_CONSTMSK_A_ = 0; +parameter _TECHMAP_CONSTVAL_A_ = 0; +parameter _TECHMAP_CONSTMSK_B_ = 0; +parameter _TECHMAP_CONSTVAL_B_ = 0; + +wire [1023:0] _TECHMAP_DO_ = "opt -fast;"; + +wire [A_WIDTH:0] ch; + +genvar n; +generate + if (Y_WIDTH != 1 || A_SIGNED || B_SIGNED) + wire _TECHMAP_FAIL_ = 1; + else if (&_TECHMAP_CONSTMSK_A_) begin + if (A_WIDTH > B_WIDTH) + wire _TECHMAP_FAIL_ = 1; + else if (_TECHMAP_CELLTYPE_ == "$lt" || _TECHMAP_CELLTYPE_ == "$le") + constgtge #(.A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH)) + _TECHMAP_REPLACE_(.A(B), .B(A), .Y(Y), + .C(_TECHMAP_CELLTYPE_ == "$lt")); + else + constltle #(.A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH)) + _TECHMAP_REPLACE_(.A(B), .B(A), .Y(Y), + .C(_TECHMAP_CELLTYPE_ == "$gt")); + end else if (&_TECHMAP_CONSTMSK_B_) begin + if (B_WIDTH > A_WIDTH) + wire _TECHMAP_FAIL_ = 1; + else if (_TECHMAP_CELLTYPE_ == "$lt" || _TECHMAP_CELLTYPE_ == "$le") + constltle #(.A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH)) + _TECHMAP_REPLACE_(.A(A), .B(B), .Y(Y), + .C(_TECHMAP_CELLTYPE_ == "$le")); + else + constgtge #(.A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH)) + _TECHMAP_REPLACE_(.A(A), .B(B), .Y(Y), + .C(_TECHMAP_CELLTYPE_ == "$ge")); + end else + wire _TECHMAP_FAIL_ = 1; +endgenerate + +endmodule From 3ffa4b5e5d478b653dba2fd640d6b44f0b92f01c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 13 Nov 2023 10:41:54 +0100 Subject: [PATCH 134/240] synth_lattice: Wire up `cmp2softlogic` as an option --- techlibs/lattice/synth_lattice.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index e2987d0259e..ba39397c472 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -127,6 +127,10 @@ struct SynthLatticePass : public ScriptPass log(" read/write collision\" (same result as setting the no_rw_check\n"); log(" attribute on all memories).\n"); log("\n"); + log(" -cmp2softlogic\n"); + log(" implement constant comparisons in soft logic, do not involve\n"); + log(" hard carry chains\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -135,6 +139,7 @@ struct SynthLatticePass : public ScriptPass string top_opt, edif_file, json_file, family; bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp; + bool cmp2softlogic; string postfix, arith_map, brams_map, dsp_map; void clear_flags() override @@ -162,6 +167,7 @@ struct SynthLatticePass : public ScriptPass brams_map = ""; dsp_map = ""; have_dsp = false; + cmp2softlogic = false; } void execute(std::vector args, RTLIL::Design *design) override @@ -263,6 +269,10 @@ struct SynthLatticePass : public ScriptPass no_rw_check = true; continue; } + if (args[argidx] == "-cmp2softlogic") { + cmp2softlogic = true; + continue; + } break; } extra_args(args, argidx, design); @@ -343,6 +353,8 @@ struct SynthLatticePass : public ScriptPass run("peepopt"); run("opt_clean"); run("share"); + if (cmp2softlogic) + run("techmap -map +/cmp2softlogic.v"); run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); run("opt_expr"); run("opt_clean"); From 7ae4041e20c9ab794ceb4dbe68021ee11c13049d Mon Sep 17 00:00:00 2001 From: Lofty Date: Mon, 13 Nov 2023 15:12:23 +0000 Subject: [PATCH 135/240] ice40, ecp5, gowin: enable ABC9 by default --- techlibs/ecp5/synth_ecp5.cc | 12 ++++++++---- techlibs/gowin/synth_gowin.cc | 12 ++++++++---- techlibs/ice40/synth_ice40.cc | 10 +++++++--- tests/arch/ecp5/add_sub.ys | 7 +++++-- tests/arch/ecp5/counter.ys | 3 ++- tests/arch/gowin/counter.ys | 3 ++- tests/arch/gowin/init.ys | 2 +- tests/arch/gowin/mux.ys | 9 ++++++++- tests/arch/ice40/add_sub.ys | 2 +- tests/arch/ice40/mux.ys | 8 ++++---- 10 files changed, 46 insertions(+), 22 deletions(-) diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index fdc36e55267..f6215987f7f 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -93,8 +93,8 @@ struct SynthEcp5Pass : public ScriptPass log(" -abc2\n"); log(" run two passes of 'abc' for slightly improved logic density\n"); log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log(" -noabc9\n"); + log(" disable use of new ABC9 flow\n"); log("\n"); log(" -vpr\n"); log(" generate an output netlist (and BLIF file) suitable for VPR\n"); @@ -137,7 +137,7 @@ struct SynthEcp5Pass : public ScriptPass retime = false; abc2 = false; vpr = false; - abc9 = false; + abc9 = true; iopad = false; nodsp = false; no_rw_check = false; @@ -224,7 +224,11 @@ struct SynthEcp5Pass : public ScriptPass continue; } if (args[argidx] == "-abc9") { - abc9 = true; + // removed, ABC9 is on by default. + continue; + } + if (args[argidx] == "-noabc9") { + abc9 = false; continue; } if (args[argidx] == "-iopad") { diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 3b9d7424a7b..094bd4fc5b1 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -78,8 +78,8 @@ struct SynthGowinPass : public ScriptPass log(" -noalu\n"); log(" do not use ALU cells\n"); log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log(" -noabc9\n"); + log(" disable use of new ABC9 flow\n"); log("\n"); log(" -no-rw-check\n"); log(" marks all recognized read ports as \"return don't-care value on\n"); @@ -106,7 +106,7 @@ struct SynthGowinPass : public ScriptPass nodffe = false; nolutram = false; nowidelut = false; - abc9 = false; + abc9 = true; noiopads = false; noalu = false; no_rw_check = false; @@ -170,7 +170,11 @@ struct SynthGowinPass : public ScriptPass continue; } if (args[argidx] == "-abc9") { - abc9 = true; + // removed, ABC9 is on by default. + continue; + } + if (args[argidx] == "-abc9") { + abc9 = false; continue; } if (args[argidx] == "-noiopads") { diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 2ae859efe32..7632df73381 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -106,8 +106,8 @@ struct SynthIce40Pass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log(" -noabc9\n"); + log(" disable use of new ABC9 flow\n"); log("\n"); log(" -flowmap\n"); log(" use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n"); @@ -144,7 +144,7 @@ struct SynthIce40Pass : public ScriptPass noabc = false; abc2 = false; vpr = false; - abc9 = false; + abc9 = true; flowmap = false; device_opt = "hx"; no_rw_check = false; @@ -235,6 +235,10 @@ struct SynthIce40Pass : public ScriptPass continue; } if (args[argidx] == "-abc9") { + // removed, ABC9 is on by default. + continue; + } + if (args[argidx] == "-noabc9") { abc9 = true; continue; } diff --git a/tests/arch/ecp5/add_sub.ys b/tests/arch/ecp5/add_sub.ys index d85ce792ee6..c3ce8c56dae 100644 --- a/tests/arch/ecp5/add_sub.ys +++ b/tests/arch/ecp5/add_sub.ys @@ -4,6 +4,9 @@ proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:LUT4 -select -assert-none t:LUT4 %% t:* %D +select -assert-min 25 t:LUT4 +select -assert-max 26 t:LUT4 +select -assert-count 10 t:PFUMX +select -assert-count 6 t:L6MUX21 +select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D diff --git a/tests/arch/ecp5/counter.ys b/tests/arch/ecp5/counter.ys index e46001ffede..e3f713228c3 100644 --- a/tests/arch/ecp5/counter.ys +++ b/tests/arch/ecp5/counter.ys @@ -5,6 +5,7 @@ flatten equiv_opt -assert -multiclock -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 select -assert-count 4 t:CCU2C select -assert-count 8 t:TRELLIS_FF -select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D +select -assert-none t:LUT4 t:CCU2C t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/gowin/counter.ys b/tests/arch/gowin/counter.ys index bdbc7ee2432..ec6ca0f5ee2 100644 --- a/tests/arch/gowin/counter.ys +++ b/tests/arch/gowin/counter.ys @@ -6,10 +6,11 @@ equiv_opt -assert -multiclock -map +/gowin/cells_sim.v synth_gowin # equivalency design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT1 select -assert-count 8 t:DFFC select -assert-count 8 t:ALU select -assert-count 1 t:GND select -assert-count 1 t:VCC select -assert-count 2 t:IBUF select -assert-count 8 t:OBUF -select -assert-none t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT1 t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/gowin/init.ys b/tests/arch/gowin/init.ys index fba7c2fa583..d522801c63d 100644 --- a/tests/arch/gowin/init.ys +++ b/tests/arch/gowin/init.ys @@ -1,5 +1,5 @@ read_verilog init.v -read_verilog -lib +/gowin/cells_sim.v +read_verilog -lib -specify +/gowin/cells_sim.v design -save read proc diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index 33b092284fa..d5978f4ea5c 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -32,10 +32,17 @@ proc equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT1 +select -assert-count 10 t:LUT3 +select -assert-count 1 t:LUT4 +select -assert-count 5 t:MUX2_LUT5 +select -assert-count 2 t:MUX2_LUT6 +select -assert-count 1 t:MUX2_LUT7 select -assert-count 11 t:IBUF select -assert-count 1 t:OBUF +select -assert-count 1 t:GND -select -assert-none t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT* t:MUX2_LUT7 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF t:GND %% t:* %D design -load read hierarchy -top mux16 diff --git a/tests/arch/ice40/add_sub.ys b/tests/arch/ice40/add_sub.ys index 578ec080380..74b83b8ee91 100644 --- a/tests/arch/ice40/add_sub.ys +++ b/tests/arch/ice40/add_sub.ys @@ -3,7 +3,7 @@ hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 11 t:SB_LUT4 +select -assert-count 10 t:SB_LUT4 select -assert-count 6 t:SB_CARRY select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys index 2b661fd6b1a..977d6975063 100644 --- a/tests/arch/ice40/mux.ys +++ b/tests/arch/ice40/mux.ys @@ -15,7 +15,7 @@ proc equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 2 t:SB_LUT4 +select -assert-count 3 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D @@ -25,7 +25,7 @@ proc equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 5 t:SB_LUT4 +select -assert-count 6 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D @@ -35,7 +35,7 @@ proc equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-min 11 t:SB_LUT4 -select -assert-max 12 t:SB_LUT4 +select -assert-min 13 t:SB_LUT4 +select -assert-max 14 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D From 46408b5da3a6ca74dc27ddac339529485d3765b7 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 14 Nov 2023 00:15:32 +0000 Subject: [PATCH 136/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3e6f05d4e48..04b3a157ee3 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.35+7 +YOSYS_VER := 0.35+21 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 726c501e7ec8e913060fd48df1e07a7b998a179d Mon Sep 17 00:00:00 2001 From: Catherine Date: Tue, 14 Nov 2023 02:03:23 +0000 Subject: [PATCH 137/240] Update WASI compilation flags to include required libraries --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 04b3a157ee3..be0f8ca2e99 100644 --- a/Makefile +++ b/Makefile @@ -321,9 +321,9 @@ AR = $(WASI_SDK)/bin/ar RANLIB = $(WASI_SDK)/bin/ranlib WASIFLAGS := --sysroot $(WASI_SDK)/share/wasi-sysroot $(WASIFLAGS) endif -CXXFLAGS := $(WASIFLAGS) -std=$(CXXSTD) -Os $(filter-out -fPIC,$(CXXFLAGS)) +CXXFLAGS := $(WASIFLAGS) -std=$(CXXSTD) -Os -D_WASI_EMULATED_PROCESS_CLOCKS $(filter-out -fPIC,$(CXXFLAGS)) LDFLAGS := $(WASIFLAGS) -Wl,-z,stack-size=1048576 $(filter-out -rdynamic,$(LDFLAGS)) -LDLIBS := $(filter-out -lrt,$(LDLIBS)) +LDLIBS := -lwasi-emulated-process-clocks $(filter-out -lrt,$(LDLIBS)) ABCMKARGS += AR="$(AR)" RANLIB="$(RANLIB)" ABCMKARGS += ARCHFLAGS="$(WASIFLAGS) -DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING -DABC_NO_RLIMIT -Wno-c++11-narrowing" ABCMKARGS += OPTFLAGS="-Os" From c11744b4efb5fd372efeb90af1c8f5801047f445 Mon Sep 17 00:00:00 2001 From: Catherine Date: Tue, 14 Nov 2023 03:33:35 +0000 Subject: [PATCH 138/240] Fix WASI compilation flags for abc. --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index be0f8ca2e99..15e336b88ce 100644 --- a/Makefile +++ b/Makefile @@ -325,7 +325,7 @@ CXXFLAGS := $(WASIFLAGS) -std=$(CXXSTD) -Os -D_WASI_EMULATED_PROCESS_CLOCKS $(fi LDFLAGS := $(WASIFLAGS) -Wl,-z,stack-size=1048576 $(filter-out -rdynamic,$(LDFLAGS)) LDLIBS := -lwasi-emulated-process-clocks $(filter-out -lrt,$(LDLIBS)) ABCMKARGS += AR="$(AR)" RANLIB="$(RANLIB)" -ABCMKARGS += ARCHFLAGS="$(WASIFLAGS) -DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING -DABC_NO_RLIMIT -Wno-c++11-narrowing" +ABCMKARGS += ARCHFLAGS="$(WASIFLAGS) -D_WASI_EMULATED_PROCESS_CLOCKS -DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING -DABC_NO_RLIMIT -Wno-c++11-narrowing" ABCMKARGS += OPTFLAGS="-Os" EXE = .wasm From 5fb1264db5910dc8f0dc8bc20cf766ffce746584 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Tue, 14 Nov 2023 15:05:24 +0100 Subject: [PATCH 139/240] verific: don't try to import attributes from nullptr --- frontends/verific/verific.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5a6cd4044a0..9737fde89c2 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -264,6 +264,9 @@ static const std::string verific_unescape(const char *value) void VerificImporter::import_attributes(dict &attributes, DesignObj *obj, Netlist *nl) { + if (!obj) + return; + MapIter mi; Att *attr; From 309558767d7a67b7f17bfd40335036009017c055 Mon Sep 17 00:00:00 2001 From: Lofty Date: Tue, 14 Nov 2023 22:37:29 +0000 Subject: [PATCH 140/240] gowin: fix typo --- techlibs/gowin/synth_gowin.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 094bd4fc5b1..302ba76e5af 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -173,7 +173,7 @@ struct SynthGowinPass : public ScriptPass // removed, ABC9 is on by default. continue; } - if (args[argidx] == "-abc9") { + if (args[argidx] == "-noabc9") { abc9 = false; continue; } From 7eea047793afcfafe7507d828aeec574f56f8901 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 15 Nov 2023 00:15:49 +0000 Subject: [PATCH 141/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 15e336b88ce..187ebcd8717 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.35+21 +YOSYS_VER := 0.35+24 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From e319606ec98e40147dd20791f6a638be694a74de Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Thu, 16 Nov 2023 13:15:54 +0100 Subject: [PATCH 142/240] smtbmc: Add --incremental mode --- backends/smt2/smtbmc.py | 154 +++++++---- backends/smt2/smtbmc_incremental.py | 389 ++++++++++++++++++++++++++++ backends/smt2/witness.py | 23 +- backends/smt2/ywio.py | 10 +- 4 files changed, 512 insertions(+), 64 deletions(-) create mode 100644 backends/smt2/smtbmc_incremental.py diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py index 02e15a1b502..dd3f9ac48dc 100644 --- a/backends/smt2/smtbmc.py +++ b/backends/smt2/smtbmc.py @@ -17,7 +17,7 @@ # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # -import os, sys, getopt, re, bisect +import os, sys, getopt, re, bisect, json ##yosys-sys-path## from smtio import SmtIo, SmtOpts, MkVcd from ywio import ReadWitness, WriteWitness, WitnessValues @@ -56,6 +56,7 @@ keep_going = False check_witness = False detect_loops = False +incremental = None so = SmtOpts() @@ -185,6 +186,9 @@ def help(): check if states are unique in temporal induction counter examples (this feature is experimental and incomplete) + --incremental + run in incremental mode (experimental) + """ + so.helpmsg()) def usage(): @@ -196,7 +200,7 @@ def usage(): opts, args = getopt.getopt(sys.argv[1:], so.shortopts + "t:higcm:", so.longopts + ["help", "final-only", "assume-skipped=", "smtc=", "cex=", "aig=", "aig-noheader", "yw=", "btorwit=", "presat", "dump-vcd=", "dump-yw=", "dump-vlogtb=", "vlogtb-top=", "dump-smtc=", "dump-all", "noinfo", "append=", - "smtc-init", "smtc-top=", "noinit", "binary", "keep-going", "check-witness", "detect-loops"]) + "smtc-init", "smtc-top=", "noinit", "binary", "keep-going", "check-witness", "detect-loops", "incremental"]) except: usage() @@ -282,6 +286,9 @@ def usage(): check_witness = True elif o == "--detect-loops": detect_loops = True + elif o == "--incremental": + from smtbmc_incremental import Incremental + incremental = Incremental() elif so.handle(o, a): pass else: @@ -290,7 +297,7 @@ def usage(): if len(args) != 1: usage() -if sum([tempind, gentrace, covermode]) > 1: +if sum([tempind, gentrace, covermode, incremental is not None]) > 1: usage() constr_final_start = None @@ -444,8 +451,10 @@ def replace_netref(match): smt.produce_models = False def print_msg(msg): - print("%s %s" % (smt.timestamp(), msg)) - sys.stdout.flush() + if incremental: + incremental.print_msg(msg) + else: + print("%s %s" % (smt.timestamp(), msg), flush=True) print_msg("Solver: %s" % (so.solver)) @@ -640,10 +649,9 @@ def print_msg(msg): num_steps = max(num_steps, step+2) step += 1 -if inywfile is not None: - if not got_topt: - skip_steps = 0 - num_steps = 0 +def ywfile_constraints(inywfile, constr_assumes, map_steps=None, skip_x=False): + if map_steps is None: + map_steps = {} with open(inywfile, "r") as f: inyw = ReadWitness(f) @@ -662,10 +670,14 @@ def print_msg(msg): addr_re = re.compile(r'\\\[[0-9]+\]$') bits_re = re.compile(r'[01?]*$') + max_t = -1 + for t, step in inyw.steps(): present_signals, missing = step.present_signals(inyw.sigmap) for sig in present_signals: bits = step[sig] + if skip_x: + bits = bits.replace('x', '?') if not bits_re.match(bits): raise ValueError("unsupported bit value in Yosys witness file") @@ -684,7 +696,7 @@ def print_msg(msg): if common_end <= common_offset: continue - smt_expr = smt.witness_net_expr(topmod, f"s{t}", wire) + smt_expr = smt.witness_net_expr(topmod, f"s{map_steps.get(t, t)}", wire) if not smt_bool: slice_high = common_end - offset - 1 @@ -714,7 +726,7 @@ def print_msg(msg): for mem in smt_mems[sig.memory_path]: width, size, bv = mem["width"], mem["size"], mem["statebv"] - smt_expr = smt.net_expr(topmod, f"s{t}", mem["smtpath"]) + smt_expr = smt.net_expr(topmod, f"s{map_steps.get(t, t)}", mem["smtpath"]) if bv: word_low = sig.memory_addr * width @@ -738,11 +750,21 @@ def print_msg(msg): smt_constr = "(= %s #b%s)" % (smt_expr, bit_slice) constr_assumes[t].append((inywfile, smt_constr)) + max_t = t - if not got_topt: - if not check_witness: - skip_steps = max(skip_steps, t) - num_steps = max(num_steps, t+1) + return max_t + +if inywfile is not None: + if not got_topt: + skip_steps = 0 + num_steps = 0 + + max_t = ywfile_constraints(inywfile, constr_assumes) + + if not got_topt: + if not check_witness: + skip_steps = max(skip_steps, max_t) + num_steps = max(num_steps, max_t+1) if btorwitfile is not None: with open(btorwitfile, "r") as f: @@ -841,7 +863,7 @@ def print_msg(msg): skip_steps = step num_steps = step+1 -def collect_mem_trace_data(steps_start, steps_stop, vcd=None): +def collect_mem_trace_data(steps, vcd=None): mem_trace_data = dict() for mempath in sorted(smt.hiermems(topmod)): @@ -849,16 +871,16 @@ def collect_mem_trace_data(steps_start, steps_stop, vcd=None): expr_id = list() expr_list = list() - for i in range(steps_start, steps_stop): + for seq, i in enumerate(steps): for j in range(rports): - expr_id.append(('R', i-steps_start, j, 'A')) - expr_id.append(('R', i-steps_start, j, 'D')) + expr_id.append(('R', seq, j, 'A')) + expr_id.append(('R', seq, j, 'D')) expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dA" % j)) expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dD" % j)) for j in range(wports): - expr_id.append(('W', i-steps_start, j, 'A')) - expr_id.append(('W', i-steps_start, j, 'D')) - expr_id.append(('W', i-steps_start, j, 'M')) + expr_id.append(('W', seq, j, 'A')) + expr_id.append(('W', seq, j, 'D')) + expr_id.append(('W', seq, j, 'M')) expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dA" % j)) expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dD" % j)) expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dM" % j)) @@ -943,14 +965,14 @@ def collect_mem_trace_data(steps_start, steps_stop, vcd=None): netpath[-1] += "<%0*x>" % ((len(addr)+3) // 4, int_addr) vcd.add_net([topmod] + netpath, width) - for i in range(steps_start, steps_stop): + for seq, i in enumerate(steps): if i not in mem_trace_data: mem_trace_data[i] = list() - mem_trace_data[i].append((netpath, int_addr, "".join(tdata[i-steps_start]))) + mem_trace_data[i].append((netpath, int_addr, "".join(tdata[seq]))) return mem_trace_data -def write_vcd_trace(steps_start, steps_stop, index): +def write_vcd_trace(steps, index, seq_time=False): filename = vcdfile.replace("%", index) print_msg("Writing trace to VCD file: %s" % (filename)) @@ -971,10 +993,10 @@ def write_vcd_trace(steps_start, steps_stop, index): vcd.add_clock([topmod] + netpath, edge) path_list.append(netpath) - mem_trace_data = collect_mem_trace_data(steps_start, steps_stop, vcd) + mem_trace_data = collect_mem_trace_data(steps, vcd) - for i in range(steps_start, steps_stop): - vcd.set_time(i) + for seq, i in enumerate(steps): + vcd.set_time(seq if seq_time else i) value_list = smt.get_net_bin_list(topmod, path_list, "s%d" % i) for path, value in zip(path_list, value_list): vcd.set_net([topmod] + path, value) @@ -982,7 +1004,14 @@ def write_vcd_trace(steps_start, steps_stop, index): for path, addr, value in mem_trace_data[i]: vcd.set_net([topmod] + path, value) - vcd.set_time(steps_stop) + if seq_time: + end_time = len(steps) + elif steps: + end_time = steps[-1] + 1 + else: + end_time = 0 + + vcd.set_time(end_time) def detect_state_loop(steps_start, steps_stop): print_msg(f"Checking for loops in found induction counter example") @@ -1027,7 +1056,7 @@ def escape_identifier(identifier): -def write_vlogtb_trace(steps_start, steps_stop, index): +def write_vlogtb_trace(steps, index): filename = vlogtbfile.replace("%", index) print_msg("Writing trace to Verilog testbench: %s" % (filename)) @@ -1092,7 +1121,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index): print(" initial begin", file=f) regs = sorted(smt.hiernets(vlogtb_topmod, regs_only=True)) - regvals = smt.get_net_bin_list(vlogtb_topmod, regs, vlogtb_state.replace("@@step_idx@@", str(steps_start))) + regvals = smt.get_net_bin_list(vlogtb_topmod, regs, vlogtb_state.replace("@@step_idx@@", str(steps[0]))) print("`ifndef VERILATOR", file=f) print(" #1;", file=f) @@ -1107,7 +1136,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index): anyconsts = sorted(smt.hieranyconsts(vlogtb_topmod)) for info in anyconsts: if info[3] is not None: - modstate = smt.net_expr(vlogtb_topmod, vlogtb_state.replace("@@step_idx@@", str(steps_start)), info[0]) + modstate = smt.net_expr(vlogtb_topmod, vlogtb_state.replace("@@step_idx@@", str(steps[0])), info[0]) value = smt.bv2bin(smt.get("(|%s| %s)" % (info[1], modstate))) print(" UUT.%s = %d'b%s;" % (".".join(escape_identifier(info[0] + [info[3]])), len(value), value), file=f); @@ -1117,7 +1146,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index): addr_expr_list = list() data_expr_list = list() - for i in range(steps_start, steps_stop): + for i in steps: for j in range(rports): addr_expr_list.append(smt.mem_expr(vlogtb_topmod, vlogtb_state.replace("@@step_idx@@", str(i)), mempath, "R%dA" % j)) data_expr_list.append(smt.mem_expr(vlogtb_topmod, vlogtb_state.replace("@@step_idx@@", str(i)), mempath, "R%dD" % j)) @@ -1138,7 +1167,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index): print("", file=f) anyseqs = sorted(smt.hieranyseqs(vlogtb_topmod)) - for i in range(steps_start, steps_stop): + for i in steps: pi_names = [[name] for name, _ in primary_inputs if name not in clock_inputs] pi_values = smt.get_net_bin_list(vlogtb_topmod, pi_names, vlogtb_state.replace("@@step_idx@@", str(i))) @@ -1170,14 +1199,14 @@ def write_vlogtb_trace(steps_start, steps_stop, index): print(" end", file=f) print(" always @(posedge clock) begin", file=f) - print(" genclock <= cycle < %d;" % (steps_stop-1), file=f) + print(" genclock <= cycle < %d;" % (steps[-1]), file=f) print(" cycle <= cycle + 1;", file=f) print(" end", file=f) print("endmodule", file=f) -def write_constr_trace(steps_start, steps_stop, index): +def write_constr_trace(steps, index): filename = outconstr.replace("%", index) print_msg("Writing trace to constraints file: %s" % (filename)) @@ -1194,7 +1223,7 @@ def write_constr_trace(steps_start, steps_stop, index): constr_prefix = smtctop[1] + "." if smtcinit: - steps_start = steps_stop - 1 + steps = [steps[-1]] with open(filename, "w") as f: primary_inputs = list() @@ -1203,13 +1232,13 @@ def write_constr_trace(steps_start, steps_stop, index): width = smt.modinfo[constr_topmod].wsize[name] primary_inputs.append((name, width)) - if steps_start == 0 or smtcinit: + if steps[0] == 0 or smtcinit: print("initial", file=f) else: - print("state %d" % steps_start, file=f) + print("state %d" % steps[0], file=f) regnames = sorted(smt.hiernets(constr_topmod, regs_only=True)) - regvals = smt.get_net_list(constr_topmod, regnames, constr_state.replace("@@step_idx@@", str(steps_start))) + regvals = smt.get_net_list(constr_topmod, regnames, constr_state.replace("@@step_idx@@", str(steps[0]))) for name, val in zip(regnames, regvals): print("assume (= [%s%s] %s)" % (constr_prefix, ".".join(name), val), file=f) @@ -1220,7 +1249,7 @@ def write_constr_trace(steps_start, steps_stop, index): addr_expr_list = list() data_expr_list = list() - for i in range(steps_start, steps_stop): + for i in steps: for j in range(rports): addr_expr_list.append(smt.mem_expr(constr_topmod, constr_state.replace("@@step_idx@@", str(i)), mempath, "R%dA" % j)) data_expr_list.append(smt.mem_expr(constr_topmod, constr_state.replace("@@step_idx@@", str(i)), mempath, "R%dD" % j)) @@ -1236,7 +1265,7 @@ def write_constr_trace(steps_start, steps_stop, index): for addr, data in addr_data.items(): print("assume (= (select [%s%s] %s) %s)" % (constr_prefix, ".".join(mempath), addr, data), file=f) - for k in range(steps_start, steps_stop): + for k in steps: if not smtcinit: print("", file=f) print("state %d" % k, file=f) @@ -1247,11 +1276,14 @@ def write_constr_trace(steps_start, steps_stop, index): for name, val in zip(pi_names, pi_values): print("assume (= [%s%s] %s)" % (constr_prefix, ".".join(name), val), file=f) -def write_yw_trace(steps_start, steps_stop, index, allregs=False): - filename = outywfile.replace("%", index) - print_msg("Writing trace to Yosys witness file: %s" % (filename)) +def write_yw_trace(steps, index, allregs=False, filename=None): + if filename is None: + if outywfile is None: + return + filename = outywfile.replace("%", index) + print_msg("Writing trace to Yosys witness file: %s" % (filename)) - mem_trace_data = collect_mem_trace_data(steps_start, steps_stop) + mem_trace_data = collect_mem_trace_data(steps) with open(filename, "w") as f: inits, seqs, clocks, mems = smt.hierwitness(topmod, allregs) @@ -1295,10 +1327,10 @@ def write_yw_trace(steps_start, steps_stop, index, allregs=False): sig = yw.add_sig(word_path, overlap_start, overlap_end - overlap_start, True) mem_init_values.append((sig, overlap_bits.replace("x", "?"))) - for k in range(steps_start, steps_stop): + for i, k in enumerate(steps): step_values = WitnessValues() - if k == steps_start: + if not i: for sig, value in mem_init_values: step_values[sig] = value sigs = inits + seqs @@ -1314,17 +1346,24 @@ def write_yw_trace(steps_start, steps_stop, index, allregs=False): def write_trace(steps_start, steps_stop, index, allregs=False): + if steps_stop is None: + steps = steps_start + seq_time = True + else: + steps = list(range(steps_start, steps_stop)) + seq_time = False + if vcdfile is not None: - write_vcd_trace(steps_start, steps_stop, index) + write_vcd_trace(steps, index, seq_time=seq_time) if vlogtbfile is not None: - write_vlogtb_trace(steps_start, steps_stop, index) + write_vlogtb_trace(steps, index) if outconstr is not None: - write_constr_trace(steps_start, steps_stop, index) + write_constr_trace(steps, index) if outywfile is not None: - write_yw_trace(steps_start, steps_stop, index, allregs) + write_yw_trace(steps, index, allregs) def print_failed_asserts_worker(mod, state, path, extrainfo, infomap, infokey=()): @@ -1596,7 +1635,11 @@ def smt_check_sat(expected=["sat", "unsat"]): smt_forall_assert() return smt.check_sat(expected=expected) -if tempind: + +if incremental: + incremental.mainloop() + +elif tempind: retstatus = "FAILED" skip_counter = step_size for step in range(num_steps, -1, -1): @@ -1954,5 +1997,6 @@ def smt_check_sat(expected=["sat", "unsat"]): smt.write("(exit)") smt.wait() -print_msg("Status: %s" % retstatus) -sys.exit(0 if retstatus == "PASSED" else 1) +if not incremental: + print_msg("Status: %s" % retstatus) + sys.exit(0 if retstatus == "PASSED" else 1) diff --git a/backends/smt2/smtbmc_incremental.py b/backends/smt2/smtbmc_incremental.py new file mode 100644 index 00000000000..2be4fb6799f --- /dev/null +++ b/backends/smt2/smtbmc_incremental.py @@ -0,0 +1,389 @@ +from collections import defaultdict +import json +import typing +from functools import partial + +if typing.TYPE_CHECKING: + import smtbmc +else: + import sys + + smtbmc = sys.modules["__main__"] + + +class InteractiveError(Exception): + pass + + +class Incremental: + def __init__(self): + self.traceidx = 0 + + self.state_set = set() + self.map_cache = {} + + self._cached_hierwitness = {} + self._witness_index = None + + self._yw_constraints = {} + + def setup(self): + generic_assert_map = smtbmc.get_assert_map( + smtbmc.topmod, "state", smtbmc.topmod + ) + self.inv_generic_assert_map = { + tuple(data[1:]): key for key, data in generic_assert_map.items() + } + assert len(self.inv_generic_assert_map) == len(generic_assert_map) + + def print_json(self, **kwargs): + print(json.dumps(kwargs), flush=True) + + def print_msg(self, msg): + self.print_json(msg=msg) + + def get_cached_assert(self, step, name): + try: + assert_map = self.map_cache[step] + except KeyError: + assert_map = self.map_cache[step] = smtbmc.get_assert_map( + smtbmc.topmod, f"s{step}", smtbmc.topmod + ) + return assert_map[self.inv_generic_assert_map[name]][0] + + def arg_step(self, cmd, declare=False, name="step", optional=False): + step = cmd.get(name, None) + if step is None and optional: + return None + if not isinstance(step, int): + if optional: + raise InteractiveError(f"{name} must be an integer") + else: + raise InteractiveError(f"integer {name} argument required") + if declare and step in self.state_set: + raise InteractiveError(f"step {step} already declared") + if not declare and step not in self.state_set: + raise InteractiveError(f"step {step} not declared") + return step + + def expr_arg_len(self, expr, min_len, max_len=-1): + if max_len == -1: + max_len = min_len + arg_len = len(expr) - 1 + + if min_len is not None and arg_len < min_len: + if min_len == max_len: + raise ( + f"{json.dumps(expr[0])} expression must have " + f"{min_len} argument{'s' if min_len != 1 else ''}" + ) + else: + raise ( + f"{json.dumps(expr[0])} expression must have at least " + f"{min_len} argument{'s' if min_len != 1 else ''}" + ) + if max_len is not None and arg_len > max_len: + raise ( + f"{json.dumps(expr[0])} expression can have at most " + f"{min_len} argument{'s' if max_len != 1 else ''}" + ) + + def expr_step(self, expr, smt_out): + self.expr_arg_len(expr, 1) + step = expr[1] + if step not in self.state_set: + raise InteractiveError(f"step {step} not declared") + smt_out.append(f"s{step}") + return "module", smtbmc.topmod + + def expr_mod_constraint(self, expr, smt_out): + self.expr_arg_len(expr, 1) + position = len(smt_out) + smt_out.append(None) + arg_sort = self.expr(expr[1], smt_out, required_sort=["module", None]) + module = arg_sort[1] + suffix = expr[0][3:] + smt_out[position] = f"(|{module}{suffix}| " + smt_out.append(")") + return "Bool" + + def expr_mod_constraint2(self, expr, smt_out): + self.expr_arg_len(expr, 2) + + position = len(smt_out) + smt_out.append(None) + arg_sort = self.expr(expr[1], smt_out, required_sort=["module", None]) + smt_out.append(" ") + self.expr(expr[2], smt_out, required_sort=arg_sort) + module = arg_sort[1] + suffix = expr[0][3:] + smt_out[position] = f"(|{module}{suffix}| " + smt_out.append(")") + return "Bool" + + def expr_not(self, expr, smt_out): + self.expr_arg_len(expr, 1) + + smt_out.append("(not ") + self.expr(expr[1], smt_out, required_sort="Bool") + smt_out.append(")") + return "Bool" + + def expr_eq(self, expr, smt_out): + self.expr_arg_len(expr, 2) + + smt_out.append("(= ") + arg_sort = self.expr(expr[1], smt_out) + if ( + smtbmc.smt.unroll + and isinstance(arg_sort, (list, tuple)) + and arg_sort[0] == "module" + ): + raise InteractiveError("state equality not supported in unroll mode") + + smt_out.append(" ") + self.expr(expr[2], smt_out, required_sort=arg_sort) + smt_out.append(")") + return "Bool" + + def expr_andor(self, expr, smt_out): + if len(expr) == 1: + smt_out.push({"and": "true", "or": "false"}[expr[0]]) + elif len(expr) == 2: + arg_sort = self.expr(expr[1], smt_out) + if arg_sort != "Bool": + raise InteractiveError( + f"arguments of {json.dumps(expr[0])} must have sort Bool" + ) + else: + sep = f"({expr[0]} " + for arg in expr[1:]: + smt_out.append(sep) + sep = " " + self.expr(arg, smt_out, required_sort="Bool") + smt_out.append(")") + return "Bool" + + def expr_yw(self, expr, smt_out): + if len(expr) == 2: + name = None + step = expr[1] + elif len(expr) == 3: + name = expr[1] + step = expr[2] + + if step not in self.state_set: + raise InteractiveError(f"step {step} not declared") + + if name not in self._yw_constraints: + raise InteractiveError(f"no yw file loaded as name {name!r}") + + constraints = self._yw_constraints[name].get(step, []) + + if len(constraints) == 0: + smt_out.append("true") + elif len(constraints) == 1: + smt_out.append(constraints[0]) + else: + sep = "(and " + for constraint in constraints: + smt_out.append(sep) + sep = " " + smt_out.append(constraint) + smt_out.append(")") + + return "Bool" + + def expr_label(self, expr, smt_out): + if len(expr) != 3: + raise InteractiveError(f'expected ["!", label, sub_expr], got {expr!r}') + label = expr[1] + subexpr = expr[2] + + if not isinstance(label, str): + raise InteractiveError(f"expression label has to be a string") + + smt_out.append("(! ") + smt_out.appedd(label) + smt_out.append(" ") + + sort = self.expr(subexpr, smt_out) + + smt_out.append(")") + + return sort + + expr_handlers = { + "step": expr_step, + "mod_h": expr_mod_constraint, + "mod_is": expr_mod_constraint, + "mod_i": expr_mod_constraint, + "mod_a": expr_mod_constraint, + "mod_u": expr_mod_constraint, + "mod_t": expr_mod_constraint2, + "not": expr_not, + "and": expr_andor, + "or": expr_andor, + "=": expr_eq, + "yw": expr_yw, + "!": expr_label, + } + + def expr(self, expr, smt_out, required_sort=None): + if not isinstance(expr, (list, tuple)) or not expr: + raise InteractiveError( + f"expression must be a non-empty JSON array, found: {json.dumps(expr)}" + ) + name = expr[0] + + handler = self.expr_handlers.get(name) + if handler: + sort = handler(self, expr, smt_out) + + if required_sort is not None: + if isinstance(required_sort, (list, tuple)): + if ( + not isinstance(sort, (list, tuple)) + or len(sort) != len(required_sort) + or any( + r is not None and r != s + for r, s in zip(required_sort, sort) + ) + ): + raise InteractiveError( + f"required sort {json.dumps(required_sort)} found sort {json.dumps(sort)}" + ) + return sort + raise InteractiveError(f"unknown expression {json.dumps(expr[0])}") + + def expr_smt(self, expr, required_sort): + smt_out = [] + self.expr(expr, smt_out, required_sort=required_sort) + out = "".join(smt_out) + return out + + def cmd_new_step(self, cmd): + step = self.arg_step(cmd, declare=True) + self.state_set.add(step) + smtbmc.smt_state(step) + + def cmd_assert(self, cmd): + name = cmd.get("cmd") + + assert_fn = { + "assert_antecedent": smtbmc.smt_assert_antecedent, + "assert_consequent": smtbmc.smt_assert_consequent, + "assert": smtbmc.smt_assert, + }[name] + + assert_fn(self.expr_smt(cmd.get("expr"), "Bool")) + + def cmd_push(self, cmd): + smtbmc.smt_push() + + def cmd_pop(self, cmd): + smtbmc.smt_pop() + + def cmd_check(self, cmd): + return smtbmc.smt_check_sat() + + def cmd_design_hierwitness(self, cmd=None): + allregs = (cmd is None) or bool(cmd.get("allreges", False)) + if self._cached_hierwitness[allregs] is not None: + return self._cached_hierwitness[allregs] + inits, seqs, clocks, mems = smtbmc.smt.hierwitness(smtbmc.topmod, allregs) + self._cached_hierwitness[allregs] = result = dict( + inits=inits, seqs=seqs, clocks=clocks, mems=mems + ) + return result + + def cmd_write_yw_trace(self, cmd): + steps = cmd.get("steps") + allregs = bool(cmd.get("allregs", False)) + + if steps is None: + steps = sorted(self.state_set) + + path = cmd.get("path") + + smtbmc.write_yw_trace(steps, self.traceidx, allregs=allregs, filename=path) + + if path is None: + self.traceidx += 1 + + def cmd_read_yw_trace(self, cmd): + steps = cmd.get("steps") + path = cmd.get("path") + name = cmd.get("name") + skip_x = cmd.get("skip_x", False) + if path is None: + raise InteractiveError("path required") + + constraints = defaultdict(list) + + if steps is None: + steps = sorted(self.state_set) + + map_steps = {i: int(j) for i, j in enumerate(steps)} + + smtbmc.ywfile_constraints(path, constraints, map_steps=map_steps, skip_x=skip_x) + + self._yw_constraints[name] = { + map_steps.get(i, i): [smtexpr for cexfile, smtexpr in constraint_list] + for i, constraint_list in constraints.items() + } + + def cmd_ping(self, cmd): + return cmd + + cmd_handlers = { + "new_step": cmd_new_step, + "assert": cmd_assert, + "assert_antecedent": cmd_assert, + "assert_consequent": cmd_assert, + "push": cmd_push, + "pop": cmd_pop, + "check": cmd_check, + "design_hierwitness": cmd_design_hierwitness, + "write_yw_trace": cmd_write_yw_trace, + "read_yw_trace": cmd_read_yw_trace, + "ping": cmd_ping, + } + + def handle_command(self, cmd): + if not isinstance(cmd, dict) or "cmd" not in cmd: + raise InteractiveError('object with "cmd" key required') + + name = cmd.get("cmd", None) + + handler = self.cmd_handlers.get(name) + if handler: + return handler(self, cmd) + else: + raise InteractiveError(f"unknown command: {name}") + + def mainloop(self): + self.setup() + while True: + try: + cmd = input().strip() + if not cmd or cmd.startswith("#") or cmd.startswith("//"): + continue + try: + cmd = json.loads(cmd) + except json.decoder.JSONDecodeError as e: + self.print_json(err=f"invalid JSON: {e}") + continue + except EOFError: + break + + try: + result = self.handle_command(cmd) + except InteractiveError as e: + self.print_json(err=str(e)) + continue + except Exception as e: + self.print_json(err=f"internal error: {e}") + raise + else: + self.print_json(ok=result) diff --git a/backends/smt2/witness.py b/backends/smt2/witness.py index 0977f4532d5..a39500c2dc1 100644 --- a/backends/smt2/witness.py +++ b/backends/smt2/witness.py @@ -33,10 +33,14 @@ def cli(): Display a Yosys witness trace in a human readable format. """) @click.argument("input", type=click.File("r")) -def display(input): +@click.option("--skip-x", help="Treat x bits as unassigned.", is_flag=True) +def display(input, skip_x): click.echo(f"Reading Yosys witness trace {input.name!r}...") inyw = ReadWitness(input) + if skip_x: + inyw.skip_x() + def output(): yield click.style("*** RTLIL bit-order below may differ from source level declarations ***", fg="red") @@ -91,7 +95,11 @@ def stats(input): @click.option("--append", "-p", type=int, multiple=True, help="Number of steps (+ve or -ve) to append to end of input trace. " +"Can be defined multiple times, following the same order as input traces. ") -def yw2yw(inputs, output, append): +@click.option("--skip-x", help="Leave input x bits unassigned.", is_flag=True) +def yw2yw(inputs, output, append, skip_x): + if len(inputs) == 0: + raise click.ClickException(f"no inputs specified") + outyw = WriteWitness(output, "yosys-witness yw2yw") join_inputs = len(inputs) > 1 inyws = {} @@ -129,12 +137,12 @@ def yw2yw(inputs, output, append): click.echo(f"Copying yosys witness trace from {input.name!r} to {output.name!r}...") if first_witness: - outyw.step(init_values) + outyw.step(init_values, skip_x=skip_x) else: - outyw.step(inyw.first_step()) + outyw.step(inyw.first_step(), skip_x=skip_x) for t, values in inyw.steps(1): - outyw.step(values) + outyw.step(values, skip_x=skip_x) click.echo(f" copied {t + 1} time steps.") first_witness = False @@ -174,7 +182,8 @@ def __init__(self, mapfile): @click.argument("input", type=click.File("r")) @click.argument("mapfile", type=click.File("r")) @click.argument("output", type=click.File("w")) -def aiw2yw(input, mapfile, output): +@click.option("--skip-x", help="Leave input x bits unassigned.", is_flag=True) +def aiw2yw(input, mapfile, output, skip_x): input_name = input.name click.echo(f"Converting AIGER witness trace {input_name!r} to Yosys witness trace {output.name!r}...") click.echo(f"Using Yosys witness AIGER map file {mapfile.name!r}") @@ -245,7 +254,7 @@ def aiw2yw(input, mapfile, output): values[bit] = v - outyw.step(values) + outyw.step(values, skip_x=skip_x) outyw.end_trace() diff --git a/backends/smt2/ywio.py b/backends/smt2/ywio.py index 4e95f8c33d2..023a2d351b3 100644 --- a/backends/smt2/ywio.py +++ b/backends/smt2/ywio.py @@ -351,11 +351,14 @@ def write_header(self): self.out.name("steps") self.out.begin_array() - def step(self, values): + def step(self, values, skip_x=False): if not self.header_written: self.write_header() - self.out.value({"bits": values.pack(self.sigmap)}) + packed = values.pack(self.sigmap) + if skip_x: + packed = packed.replace('x', '?') + self.out.value({"bits": packed}) self.t += 1 @@ -390,6 +393,9 @@ def __init__(self, f): self.bits = [step["bits"] for step in data["steps"]] + def skip_x(self): + self.bits = [step.replace('x', '?') for step in self.bits] + def init_step(self): return self.step(0) From 5c96746309e67dfd3d2dfc168d4b3c5c07c34e50 Mon Sep 17 00:00:00 2001 From: Lofty Date: Fri, 17 Nov 2023 12:49:17 +0000 Subject: [PATCH 143/240] ice40: fix -noabc9 --- techlibs/ice40/synth_ice40.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 7632df73381..a9982649b35 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -239,7 +239,7 @@ struct SynthIce40Pass : public ScriptPass continue; } if (args[argidx] == "-noabc9") { - abc9 = true; + abc9 = false; continue; } if (args[argidx] == "-dff") { From ab6c1d368b103addae8cc658659e2f7cfd166d94 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 18 Nov 2023 00:15:31 +0000 Subject: [PATCH 144/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 187ebcd8717..d0fa98bea07 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.35+24 +YOSYS_VER := 0.35+29 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 282ce24eecd6b8da2724baeee5c92635f7700116 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 20 Nov 2023 17:25:09 +0100 Subject: [PATCH 145/240] fmt: Handle free-standing time arguments --- kernel/fmt.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/kernel/fmt.cc b/kernel/fmt.cc index 965e58ebce4..383fa7de16f 100644 --- a/kernel/fmt.cc +++ b/kernel/fmt.cc @@ -326,6 +326,16 @@ void Fmt::parse_verilog(const std::vector &args, bool sformat_lik break; } + case VerilogFmtArg::TIME: { + FmtPart part = {}; + part.type = FmtPart::TIME; + part.realtime = arg->realtime; + part.padding = ' '; + part.width = 20; + parts.push_back(part); + break; + } + case VerilogFmtArg::STRING: { if (arg == args.begin() || !sformat_like) { const auto fmtarg = arg; From c95298225ddb5d5f7e193d5ab23aa969aa9628ff Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 21 Nov 2023 00:16:08 +0000 Subject: [PATCH 146/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index d0fa98bea07..2aeade5d441 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.35+29 +YOSYS_VER := 0.35+36 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 84568453f803b542326cae061b1ee9ef7894c430 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 22 Nov 2023 12:33:47 +0100 Subject: [PATCH 147/240] rtlil: Add `lsb()` `msb()` SigSpec helpers --- kernel/rtlil.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 9c318eac93c..17853fae163 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -921,6 +921,9 @@ struct RTLIL::SigSpec RTLIL::SigSpec extract(int offset, int length = 1) const; RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); } + RTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; }; + RTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; }; + void append(const RTLIL::SigSpec &signal); inline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); } inline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); } From 00e899f98d30de847e0623dd479dfcea2d9989e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 6 Nov 2023 14:05:20 +0100 Subject: [PATCH 148/240] booth: Refactor signed multiplier full adders emission --- passes/techmap/booth.cc | 194 +++++++++++----------------------------- 1 file changed, 52 insertions(+), 142 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index e1e6b360ab6..159fcdcf4fc 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -184,6 +184,24 @@ struct BoothPassWorker { cor_o = module->AndGate(NEW_ID_SUFFIX(name), pp1_nor_pp0, cori_i); } + void BuildBitwiseFa(Module *mod, std::string name, const SigSpec &sig_a, const SigSpec &sig_b, + const SigSpec &sig_c, const SigSpec &sig_x, const SigSpec &sig_y, + const std::string &src = "") + { + // We can't emit a single wide full-adder cell here since + // there would typically be feedback loops involving the cells' + // input and output ports, and Yosys doesn't cope well with + // those + log_assert(sig_a.size() == sig_b.size()); + log_assert(sig_a.size() == sig_c.size()); + log_assert(sig_a.size() == sig_x.size()); + log_assert(sig_a.size() == sig_y.size()); + + for (int i = 0; i < sig_a.size(); i++) + mod->addFa(stringf("%s[%d]", name.c_str(), i), sig_a[i], sig_b[i], + sig_c[i], sig_x[i], sig_y[i], src); + } + void run() { for (auto cell : module->selected_cells()) { @@ -1014,150 +1032,42 @@ struct BoothPassWorker { // int fa_el_ix = 0; int fa_row_ix = 0; - // use 1 d arrays (2d cannot have variable sized indices) - SigSpec fa_sum_n(State::S0, fa_row_count * fa_count); - SigSpec fa_carry_n(State::S0, fa_row_count * fa_count); + std::vector fa_sum; + std::vector fa_carry; for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) { - for (fa_el_ix = 0; fa_el_ix < fa_count; fa_el_ix++) { - fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] = - module->addWire(NEW_ID_SUFFIX(stringf("fa_sum_n_%d_%d", fa_row_ix, fa_el_ix)), 1); - fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix] = - module->addWire(NEW_ID_SUFFIX(stringf("fa_carry_n_%d_%d", fa_row_ix, fa_el_ix)), 1); - } + fa_sum.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count)); + fa_carry.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count)); } // full adder creation - std::string bfa_name; - std::string exc_inv_name; - for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) { - for (fa_el_ix = 0; fa_el_ix < fa_count; fa_el_ix++) { - // base case: 1st row. Inputs from decoders - // Note in rest of tree inputs from prior addition and a decoder - if (fa_row_ix == 0) { - // beginning - // base case: - // first two cells: have B input hooked to 0. - if (fa_el_ix == 0) { - // quadrant 1: we hard code these using non-booth - fa_el_ix++; - - } - // step case - else if (fa_el_ix >= 2 && fa_el_ix <= x_sz) { - // middle (2...x_sz cells) - module->addFa(NEW_ID_SUFFIX(stringf("bfa_0_step_%d_%d_L", fa_row_ix, fa_el_ix)), - /* A */ PPij[(0 * dec_count) + fa_el_ix], - /* B */ PPij[(1 * dec_count) + fa_el_ix - 2], - /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], - /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], - /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] - ); - } - // end 3 cells: x_sz+1.2.3 - // - else { - // fa_el_ix = x_sz+1 - module->addFa(NEW_ID_SUFFIX(stringf("bfa_0_se_0_%d_%d_L", fa_row_ix, fa_el_ix)), - /* A */ PPij[(0 * dec_count) + x_sz], - /* B */ PPij[(1 * dec_count) + fa_el_ix - 2], - /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], - /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], - /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] - ); - - // exception:invert ppi - fa_el_ix++; - SigBit d08_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_0_exc_inv1_%d_%d_L", fa_row_ix, fa_el_ix)), - PPij[(0 * dec_count) + dec_count - 1]); - - SigBit d18_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_0_exc_inv2_%d_%d_L", fa_row_ix, fa_el_ix)), - PPij[(1 * dec_count) + dec_count - 1]); - - module->addFa(NEW_ID_SUFFIX(stringf("bfa_0_se_1_%d_%d_L", fa_row_ix, fa_el_ix)), - /* A */ d08_inv, - /* B */ d18_inv, - /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], - /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], - /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] - ); - - // sign extension - fa_el_ix++; - - module->addFa(NEW_ID_SUFFIX(stringf("bfa_0_se_2_%d_%d_L", fa_row_ix, fa_el_ix)), - /* A */ State::S0, - /* B */ State::S1, - /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], - /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], - /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] - ); - } - } - - // step case: 2nd and rest of rows. (fa_row_ix == 1...n) - // special because these are driven by a decoder and prior fa. - else { - // beginning - if (fa_el_ix == 0) { - // first two cells: have B input hooked to 0. - // column is offset by row_ix*2 - - module->addFa(NEW_ID_SUFFIX(stringf("bfa_base_%d_%d_L", fa_row_ix, fa_el_ix)), - /* A */ fa_sum_n[(fa_row_ix - 1) * fa_count + 2], - /* B */ State::S0, - /* C */ cori_n_int[fa_row_ix], - /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], - /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] - ); - fa_el_ix++; - - module->addFa(NEW_ID_SUFFIX(stringf("bfa_base_%d_%d_L", fa_row_ix, fa_el_ix)), - /* A */ fa_sum_n[(fa_row_ix - 1) * fa_count + 3], // from prior full adder row - /* B */ State::S0, - /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], - /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], - /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] - ); + // base case: 1st row: Inputs from decoders + // 1st row exception: two localized inverters due to sign extension structure + SigBit d08_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]); + SigBit d18_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]); + BuildBitwiseFa(module, NEW_ID_SUFFIX("fa_row_0").str(), + /* A */ {State::S0, d08_inv, PPij[(0 * dec_count) + x_sz], PPij.extract((0 * dec_count) + 2, x_sz - 1)}, + /* B */ {State::S1, d18_inv, PPij.extract((1 * dec_count), x_sz)}, + /* C */ fa_carry[0].extract(1, x_sz + 2), + /* X */ fa_carry[0].extract(2, x_sz + 2), + /* Y */ fa_sum[0].extract(2, x_sz + 2) + ); - } + // step case: 2nd and rest of rows. (fa_row_ix == 1...n) + // special because these are driven by a decoder and prior fa. + for (fa_row_ix = 1; fa_row_ix < fa_row_count; fa_row_ix++) { + // end two bits: sign extension + SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_%d_L", fa_row_ix, fa_el_ix)), + PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]); - else if (fa_el_ix >= 2 && fa_el_ix <= x_sz + 1) { - // middle (2...x_sz+1 cells) - module->addFa(NEW_ID_SUFFIX(stringf("bfa_step_%d_%d_L", fa_row_ix, fa_el_ix)), - /* A */ fa_sum_n[(fa_row_ix - 1) * fa_count + fa_el_ix + 2], - /* B */ PPij[(fa_row_ix + 1) * dec_count + fa_el_ix - 2], - /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], - /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], - /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] - ); - } + BuildBitwiseFa(module, NEW_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(), + /* A */ {State::S0, fa_carry[fa_row_ix - 1][fa_count - 1], fa_sum[fa_row_ix - 1].extract(2, x_sz + 2)}, + /* B */ {State::S1, d_inv, PPij.extract((fa_row_ix + 1) * dec_count, x_sz), State::S0, State::S0}, - else if (fa_el_ix > x_sz + 1) { - // end two bits: sign extension - SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_%d_L", fa_row_ix, fa_el_ix)), - PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]); - - module->addFa(NEW_ID_SUFFIX(stringf("bfa_se_%d_%d_L", fa_row_ix, fa_el_ix)), - /* A */ fa_carry_n[((fa_row_ix - 1) * fa_count) + fa_count - 1], - /* B */ d_inv, - /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], - /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], - /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] - ); - fa_el_ix++; - - // sign extension - module->addFa(NEW_ID_SUFFIX(stringf("bfa_se_%d_%d_L", fa_row_ix, fa_el_ix)), - /* A */ State::S0, - /* B */ State::S1, - /* C */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix - 1], - /* X */ fa_carry_n[(fa_row_ix * fa_count) + fa_el_ix], - /* Y */ fa_sum_n[(fa_row_ix * fa_count) + fa_el_ix] - ); - } - } - } + /* C */ {fa_carry[fa_row_ix].extract(0, x_sz + 3), cori_n_int[fa_row_ix]}, + /* X */ fa_carry[fa_row_ix], + /* Y */ fa_sum[fa_row_ix] + ); } // instantiate the cpa @@ -1175,11 +1085,11 @@ struct BoothPassWorker { int fa_row_ix = cpa_ix / 2; module->addBufGate(NEW_ID_SUFFIX(stringf("pp_buf_%d_driven_by_fa_row_%d", cpa_ix, fa_row_ix)), - fa_sum_n[(fa_row_ix * fa_count) + 0], Z[cpa_ix]); + fa_sum[fa_row_ix][0], Z[cpa_ix]); cpa_ix++; module->addBufGate(NEW_ID_SUFFIX(stringf("pp_buf_%d_driven_by_fa_row_%d", cpa_ix, fa_row_ix)), - fa_sum_n[(fa_row_ix * fa_count) + 1], Z[cpa_ix]); + fa_sum[fa_row_ix][1], Z[cpa_ix]); } else { int offset = fa_row_count * 2; bool base_case = cpa_ix - offset == 0 ? true : false; @@ -1192,7 +1102,7 @@ struct BoothPassWorker { ci = cpa_carry[cpa_ix - offset - 1]; SigBit op; - BuildHa(cpa_name, fa_sum_n[(fa_row_count - 1) * fa_count + cpa_ix - offset + 2], ci, op, + BuildHa(cpa_name, fa_sum[fa_row_count - 1][cpa_ix - offset + 2], ci, op, cpa_carry[cpa_ix - offset]); module->connect(Z[cpa_ix], op); } @@ -1217,9 +1127,9 @@ struct BoothPassWorker { nxj_o_int, cor_o_int, pp0_o_int, pp1_o_int); - module->connect(fa_sum_n[(0 * fa_count) + 0], pp0_o_int); - module->connect(fa_sum_n[(0 * fa_count) + 1], pp1_o_int); - module->connect(fa_carry_n[(0 * fa_count) + 1], cor_o_int); + module->connect(fa_sum[0][0], pp0_o_int); + module->connect(fa_sum[0][1], pp1_o_int); + module->connect(fa_carry[0][1], cor_o_int); module->connect(nxj[(0 * dec_count) + 2], nxj_o_int); } }; From 8d33cc2fb605bd373bd50017a28d77b147bcd777 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 6 Nov 2023 14:18:47 +0100 Subject: [PATCH 149/240] booth: Refactor signed CPA --- passes/techmap/booth.cc | 50 +++++++++++++++-------------------------- 1 file changed, 18 insertions(+), 32 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 159fcdcf4fc..b3c98f0866b 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -1072,40 +1072,26 @@ struct BoothPassWorker { // instantiate the cpa SigSpec cpa_carry; + if (z_sz > fa_row_count * 2) + cpa_carry = module->addWire(NEW_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2); + + // The end case where we pass the last two summands + // from prior row directly to product output + // without using a cpa cell. This is always + // 0,1 index of prior fa row + for (int cpa_ix = 0; cpa_ix < fa_row_count * 2; cpa_ix += 2) { + int fa_row_ix = cpa_ix / 2; + module->connect(Z.extract(cpa_ix, 2), fa_sum[fa_row_ix].extract(0, 2)); + } - for (int cix = 0; cix < z_sz; cix++) - cpa_carry.append(module->addWire(NEW_ID_SUFFIX(stringf("cpa_carry_%d", cix)), 1)); - - for (int cpa_ix = 0; cpa_ix < z_sz; cpa_ix++) { - // The end case where we pass the last two summands - // from prior row directly to product output - // without using a cpa cell. This is always - // 0,1 index of prior fa row - if (cpa_ix <= fa_row_count * 2 - 1) { - int fa_row_ix = cpa_ix / 2; - - module->addBufGate(NEW_ID_SUFFIX(stringf("pp_buf_%d_driven_by_fa_row_%d", cpa_ix, fa_row_ix)), - fa_sum[fa_row_ix][0], Z[cpa_ix]); - - cpa_ix++; - module->addBufGate(NEW_ID_SUFFIX(stringf("pp_buf_%d_driven_by_fa_row_%d", cpa_ix, fa_row_ix)), - fa_sum[fa_row_ix][1], Z[cpa_ix]); - } else { - int offset = fa_row_count * 2; - bool base_case = cpa_ix - offset == 0 ? true : false; - std::string cpa_name = stringf("cpa_%d", cpa_ix - offset); - - SigBit ci; - if (base_case) - ci = cori_n_int[enc_count - 1]; - else - ci = cpa_carry[cpa_ix - offset - 1]; + for (int cpa_ix = fa_row_count * 2; cpa_ix < z_sz; cpa_ix++) { + int offset = fa_row_count * 2; + std::string cpa_name = stringf("cpa_%d", cpa_ix - offset); - SigBit op; - BuildHa(cpa_name, fa_sum[fa_row_count - 1][cpa_ix - offset + 2], ci, op, - cpa_carry[cpa_ix - offset]); - module->connect(Z[cpa_ix], op); - } + SigBit ci = (cpa_ix == offset) ? cori_n_int[enc_count - 1] : cpa_carry[cpa_ix - offset - 1]; + SigBit op; + BuildHa(cpa_name, fa_sum[fa_row_count - 1][cpa_ix - offset + 2], ci, op, cpa_carry[cpa_ix - offset]); + module->connect(Z[cpa_ix], op); } // From d8408b23500d9453b1fe37e0772b3421f1bd32a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 6 Nov 2023 14:24:10 +0100 Subject: [PATCH 150/240] booth: Move up signed quadrant 1 logic --- passes/techmap/booth.cc | 41 +++++++++++++++++------------------------ 1 file changed, 17 insertions(+), 24 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index b3c98f0866b..8be2e6e1db6 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -1027,6 +1027,22 @@ struct BoothPassWorker { PPij[((encoder_ix - 1) * dec_count) + dec_count - 1], unused_op); } + // + // instantiate the quadrant 1 cell. This is the upper right + // quadrant which can be realized using non-booth encoded logic. + // + SigBit pp0_o_int, pp1_o_int, nxj_o_int, q1_carry_out; + + BuildBoothQ1("icb_booth_q1_", + negi_n_int[0], // negi + cori_n_int[0], // cori + X[0], X[1], Y[0], Y[1], + nxj_o_int, q1_carry_out, pp0_o_int, pp1_o_int); + + module->connect(Z[0], pp0_o_int); + module->connect(Z[1], pp1_o_int); + module->connect(nxj[(0 * dec_count) + 2], nxj_o_int); + // // sum up the partial products // @@ -1052,6 +1068,7 @@ struct BoothPassWorker { /* X */ fa_carry[0].extract(2, x_sz + 2), /* Y */ fa_sum[0].extract(2, x_sz + 2) ); + module->connect(fa_carry[0][1], q1_carry_out); // step case: 2nd and rest of rows. (fa_row_ix == 1...n) // special because these are driven by a decoder and prior fa. @@ -1093,30 +1110,6 @@ struct BoothPassWorker { BuildHa(cpa_name, fa_sum[fa_row_count - 1][cpa_ix - offset + 2], ci, op, cpa_carry[cpa_ix - offset]); module->connect(Z[cpa_ix], op); } - - // - // instantiate the quadrant 1 cell. This is the upper right - // quadrant which can be realized using non-booth encoded logic. - // - std::string q1_name = "icb_booth_q1_"; - - SigBit pp0_o_int; - SigBit pp1_o_int; - SigBit nxj_o_int; - SigBit cor_o_int; - - BuildBoothQ1(q1_name, - negi_n_int[0], // negi - cori_n_int[0], // cori - - X[0], X[1], Y[0], Y[1], - - nxj_o_int, cor_o_int, pp0_o_int, pp1_o_int); - - module->connect(fa_sum[0][0], pp0_o_int); - module->connect(fa_sum[0][1], pp1_o_int); - module->connect(fa_carry[0][1], cor_o_int); - module->connect(nxj[(0 * dec_count) + 2], nxj_o_int); } }; From 69e994ff756f5dfeb0d57d3d16182651a69bd680 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 7 Nov 2023 14:41:41 +0100 Subject: [PATCH 151/240] booth: Clean unused FA index variable --- passes/techmap/booth.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 8be2e6e1db6..c94207a5154 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -1046,7 +1046,6 @@ struct BoothPassWorker { // // sum up the partial products // - int fa_el_ix = 0; int fa_row_ix = 0; std::vector fa_sum; std::vector fa_carry; @@ -1074,7 +1073,7 @@ struct BoothPassWorker { // special because these are driven by a decoder and prior fa. for (fa_row_ix = 1; fa_row_ix < fa_row_count; fa_row_ix++) { // end two bits: sign extension - SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_%d_L", fa_row_ix, fa_el_ix)), + SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)), PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]); BuildBitwiseFa(module, NEW_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(), From da207cdce0ca9eac9a6aebc4f580cf3de3062d01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 22 Nov 2023 15:12:15 +0100 Subject: [PATCH 152/240] booth: Make less assumptions when aligning partial products --- passes/techmap/booth.cc | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index c94207a5154..1d28f97f657 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -307,7 +307,7 @@ struct BoothPassWorker { SigSpec Y, // multiplier SigSpec Z) { // result - int x_sz = X.size(), z_sz = Z.size(); + int z_sz = Z.size(); SigSpec one_int, two_int, s_int, sb_int; int encoder_count = 0; @@ -376,7 +376,7 @@ struct BoothPassWorker { for (int i = 0; i < encoder_count + 1; i++) aligned_pp[i].extend_u0(z_sz); - AlignPP(x_sz, z_sz, ppij_int, aligned_pp); + AlignPP(z_sz, ppij_int, aligned_pp); // Debug: dump out aligned partial products. // Later on yosys will clean up unused constants @@ -609,7 +609,7 @@ struct BoothPassWorker { Pad out rows with zeros and left the opt pass clean them up. */ - void AlignPP(int x_sz, int z_sz, std::vector> &ppij_int, + void AlignPP(int z_sz, std::vector> &ppij_int, std::vector &aligned_pp) { unsigned aligned_pp_ix = aligned_pp.size() - 1; @@ -629,12 +629,10 @@ struct BoothPassWorker { // in first column of the last partial product // which is at index corresponding to size of multiplicand { + int prior_row_idx = get<1>(ppij_int[aligned_pp_ix - 1]); SigBit prior_row_sign = get<2>(ppij_int[aligned_pp_ix - 1]); - //if (prior_row_sign) { - log_assert(aligned_pp_ix < aligned_pp.size()); - log_assert(x_sz - 1 < (int)(aligned_pp[aligned_pp_ix].size())); - aligned_pp[aligned_pp_ix][x_sz - 1] = prior_row_sign; - //} + if (prior_row_idx < z_sz) + aligned_pp[aligned_pp_ix][prior_row_idx] = prior_row_sign; } for (int row_ix = aligned_pp_ix - 1; row_ix >= 0; row_ix--) { From 579f6bdc17377f453ea9a9544074111265b946f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 22 Nov 2023 12:42:11 +0100 Subject: [PATCH 153/240] booth: Do not special-case bottom rows Later on all the rows are cropped to the target size anyway, so there's no harm in transitionally including extra top bits. --- passes/techmap/booth.cc | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 1d28f97f657..0c154d150bb 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -331,7 +331,7 @@ struct BoothPassWorker { // data, shift, sign ppij_int.push_back(std::make_tuple(ppij_row_0, 0, s_int[0])); - for (int i = 1; i < encoder_count - 2; i++) { + for (int i = 1; i < encoder_count; i++) { // format 1,S.Data.shift = encoder_ix*2,sign = sb_int[i] SigSpec ppij_row_n; @@ -345,24 +345,6 @@ struct BoothPassWorker { ppij_int.push_back(std::make_tuple(ppij_row_n, i * 2, s_int[i])); } - // Build second to last row - // format S/,Data + sign bit - SigSpec ppij_row_em1; - BuildBoothUMultDecoderRowN(module, X, one_int[encoder_count - 2], two_int[encoder_count - 2], s_int[encoder_count - 2], - sb_int[encoder_count - 2], ppij_row_em1, encoder_count - 2, - false, // include sign - true // no constant - ); - ppij_int.push_back(std::make_tuple(ppij_row_em1, (encoder_count - 2) * 2, s_int[encoder_count - 2])); - // Build last row - // format Data + sign bit - SigSpec ppij_row_e; - BuildBoothUMultDecoderRowN(module, X, one_int[encoder_count - 1], two_int[encoder_count - 1], s_int[encoder_count - 1], - sb_int[encoder_count - 1], ppij_row_e, encoder_count - 1, - true, // no sign - true // no constant - ); - ppij_int.push_back(std::make_tuple(ppij_row_e, (encoder_count - 1) * 2, s_int[encoder_count - 1])); // Debug dump out partial products // DebugDumpPP(ppij_int); From f50894d8bfac9de13d1f063f36dd17d857080d01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 22 Nov 2023 12:44:13 +0100 Subject: [PATCH 154/240] booth: Drop extra decoder arguments --- passes/techmap/booth.cc | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 0c154d150bb..81568b0a1c6 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -337,9 +337,7 @@ struct BoothPassWorker { BuildBoothUMultDecoderRowN(module, X, // multiplicand - one_int[i], two_int[i], s_int[i], sb_int[i], ppij_row_n, i, - false, // include sign - false // include constant + one_int[i], two_int[i], s_int[i], sb_int[i], ppij_row_n, i ); // data, shift, sign ppij_int.push_back(std::make_tuple(ppij_row_n, i * 2, s_int[i])); @@ -413,7 +411,7 @@ struct BoothPassWorker { void BuildBoothUMultDecoderRowN(RTLIL::Module *module, SigSpec X, // multiplicand SigSpec one_int, SigSpec two_int, SigSpec s_int, SigSpec sb_int, - SigSpec &ppij_vec, int row_ix, bool no_sign, bool no_constant) + SigSpec &ppij_vec, int row_ix) { (void)module; int x_sz = GetSize(X); @@ -430,12 +428,10 @@ struct BoothPassWorker { ppij_vec.append(Bur4d_msb("row_dec_red", X[x_sz - 1], two_int, s_int)); // sign bit - if (!no_sign) // if no sign is false then make a sign bit - ppij_vec.append(sb_int); + ppij_vec.append(sb_int); // constant bit - if (!no_constant) // if non constant is false make a constant bit - ppij_vec.append(State::S1); + ppij_vec.append(State::S1); } void DebugDumpAlignPP(std::vector> &aligned_pp) From 48b73be8c6b41d57e2d7646e086b849fd47eaec4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 20 Nov 2023 17:24:24 +0100 Subject: [PATCH 155/240] booth: Replace the default signed architecture Generalize what was formerly the unsigned-only architecture to support both signed and unsigned multiplication, use that as default, and set aside the special low-power architecture that was formerly used for signed multipliers. --- passes/techmap/booth.cc | 94 ++++++++++++++++++++++------------------- 1 file changed, 51 insertions(+), 43 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 81568b0a1c6..a7c43541eed 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -276,18 +276,12 @@ struct BoothPassWorker { } log_assert(GetSize(Y) == required_op_size); - if (!is_signed) /* unsigned multiplier */ - CreateBoothUMult(module, - A, // multiplicand - B, // multiplier(scanned) - Y // result - ); - else /* signed multiplier */ - CreateBoothSMult(module, - A, // multiplicand - B, // multiplier(scanned) - Y // result (sized) - ); + CreateBoothMult(module, + A, // multiplicand + B, // multiplier(scanned) + Y, // result + is_signed + ); module->remove(cell); booth_counter++; @@ -295,24 +289,23 @@ struct BoothPassWorker { } /* - Build Unsigned Multiplier. + Build Multiplier. ------------------------- - Create a booth unsigned multiplier. - Uses a generic booth multiplier with - extra row of decoders and extended multiplier + Uses a generic booth multiplier */ - void CreateBoothUMult(RTLIL::Module *module, + void CreateBoothMult(RTLIL::Module *module, SigSpec X, // multiplicand SigSpec Y, // multiplier - SigSpec Z) + SigSpec Z, + bool is_signed) { // result int z_sz = Z.size(); SigSpec one_int, two_int, s_int, sb_int; int encoder_count = 0; - BuildBoothUMultEncoders(Y, one_int, two_int, s_int, sb_int, module, encoder_count); + BuildBoothMultEncoders(Y, one_int, two_int, s_int, sb_int, module, encoder_count, is_signed); // Build the decoder rows // format of each Partial product to be passed to CSA @@ -326,7 +319,7 @@ struct BoothPassWorker { // Row 0: special case 1. Format S/.S.S.C.Data SigSpec ppij_row_0; - BuildBoothUMultDecoderRow0(module, X, s_int, sb_int, one_int, two_int, ppij_row_0); + BuildBoothMultDecoderRow0(module, X, s_int, sb_int, one_int, two_int, ppij_row_0, is_signed); // data, shift, sign ppij_int.push_back(std::make_tuple(ppij_row_0, 0, s_int[0])); @@ -335,9 +328,10 @@ struct BoothPassWorker { // format 1,S.Data.shift = encoder_ix*2,sign = sb_int[i] SigSpec ppij_row_n; - BuildBoothUMultDecoderRowN(module, + BuildBoothMultDecoderRowN(module, X, // multiplicand - one_int[i], two_int[i], s_int[i], sb_int[i], ppij_row_n, i + one_int[i], two_int[i], s_int[i], sb_int[i], ppij_row_n, i, + is_signed ); // data, shift, sign ppij_int.push_back(std::make_tuple(ppij_row_n, i * 2, s_int[i])); @@ -373,6 +367,7 @@ struct BoothPassWorker { // Debug code: Dump out the csa trees // DumpCSATrees(debug_csa_trees); // Build the CPA to do the final accumulation. + BuildCPA(module, s_vec, c_vec, Z); } @@ -380,11 +375,12 @@ struct BoothPassWorker { Build Row 0 of decoders */ - void BuildBoothUMultDecoderRow0(RTLIL::Module *module, + void BuildBoothMultDecoderRow0(RTLIL::Module *module, SigSpec X, // multiplicand SigSpec s_int, SigSpec sb_int, SigSpec one_int, - SigSpec two_int, SigSpec &ppij_vec) + SigSpec two_int, SigSpec &ppij_vec, bool is_signed) { + (void)sb_int; (void)module; int x_sz = GetSize(X); SigBit ppij; @@ -397,21 +393,32 @@ struct BoothPassWorker { ppij_vec.append(Bur4d_n(stringf("row0_dec_%d", i), X[i], X[i - 1], one_int[0], two_int[0], s_int[0])); + // The redundant bit. Duplicate decoding of last bit. - ppij_vec.append(Bur4d_msb("row0_dec_msb", X[x_sz - 1], two_int[0], s_int[0])); + if (!is_signed) { + ppij_vec.append(Bur4d_msb("row0_dec_msb", X.msb(), two_int[0], s_int[0])); + } else { + ppij_vec.append(Bur4d_n("row0_dec_msb", X.msb(), X.msb(), + one_int[0], two_int[0], s_int[0])); + } // append the sign bits - ppij_vec.append(s_int[0]); - ppij_vec.append(s_int[0]); - ppij_vec.append(sb_int[0]); + if (is_signed) { + SigBit e = module->XorGate(NEW_ID, s_int[0], module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int[0], one_int[0]))); + ppij_vec.append({module->NotGate(NEW_ID, e), e, e}); + } else { + // append the sign bits + ppij_vec.append({module->NotGate(NEW_ID, s_int[0]), s_int[0], s_int[0]}); + } } // Build a generic row of decoders. - void BuildBoothUMultDecoderRowN(RTLIL::Module *module, + void BuildBoothMultDecoderRowN(RTLIL::Module *module, SigSpec X, // multiplicand SigSpec one_int, SigSpec two_int, SigSpec s_int, SigSpec sb_int, - SigSpec &ppij_vec, int row_ix) + SigSpec &ppij_vec, int row_ix, + bool is_signed) { (void)module; int x_sz = GetSize(X); @@ -424,13 +431,14 @@ struct BoothPassWorker { ppij_vec.append(Bur4d_n(stringf("row_%d_dec_%d", row_ix, i), X[i], X[i - 1], one_int, two_int, s_int)); - // redundant bit - ppij_vec.append(Bur4d_msb("row_dec_red", X[x_sz - 1], two_int, s_int)); - - // sign bit - ppij_vec.append(sb_int); + if (!is_signed) { // redundant bit + ppij_vec.append(Bur4d_msb("row_dec_red", X[x_sz - 1], two_int, s_int)); + } else { + ppij_vec.append(Bur4d_n(stringf("row_%d_dec_msb", row_ix), X[x_sz - 1], X[x_sz - 1], + one_int, two_int, s_int)); + } - // constant bit + ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_ID, sb_int, module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int, one_int)))); ppij_vec.append(State::S1); } @@ -807,12 +815,12 @@ struct BoothPassWorker { } } - void BuildBoothUMultEncoders(SigSpec Y, SigSpec &one_int, SigSpec &two_int, - SigSpec &s_int, SigSpec &sb_int, RTLIL::Module *module, int &encoder_ix) + void BuildBoothMultEncoders(SigSpec Y, SigSpec &one_int, SigSpec &two_int, + SigSpec &s_int, SigSpec &sb_int, RTLIL::Module *module, int &encoder_ix, bool is_signed) { int y_sz = GetSize(Y); - for (int y_ix = 0; y_ix < y_sz;) { + for (int y_ix = 0; y_ix < (!is_signed ? y_sz : y_sz - 1);) { std::string enc_name = stringf("bur_enc_%d", encoder_ix); two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); @@ -838,7 +846,7 @@ struct BoothPassWorker { bool need_padded_cell = false; if (y_ix > y_sz - 1) { - y0 = State::S0; + y0 = is_signed ? Y.msb() : State::S0; need_padded_cell = false; } else { y0 = Y[y_ix]; @@ -847,7 +855,7 @@ struct BoothPassWorker { if (y_ix > y_sz - 1) { need_padded_cell = false; - y1 = State::S0; + y1 = is_signed ? Y.msb() : State::S0; } else { y1 = Y[y_ix]; y_ix++; @@ -855,10 +863,10 @@ struct BoothPassWorker { if (y_ix > y_sz - 1) { need_padded_cell = false; - y2 = State::S0; + y2 = is_signed ? Y.msb() : State::S0; } else { if (y_ix == y_sz - 1) - need_padded_cell = true; + need_padded_cell = !is_signed; else need_padded_cell = false; y2 = Y[y_ix]; From 7005ea9411806b67ab89bd668a5d9cb8d28dd0c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 7 Nov 2023 14:53:20 +0100 Subject: [PATCH 156/240] booth: Revisit help --- passes/techmap/booth.cc | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index a7c43541eed..0830f97662d 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -1104,21 +1104,13 @@ struct BoothPass : public Pass { log("\n"); log(" booth [selection]\n"); log("\n"); - log("This pass replaces multiplier cells with an implementation based on the Booth\n"); - log("algorithm. It operates on $mul cells whose width of operands is at least 4x4\n"); - log("and whose width of result is at least 8. The detailed architecture is selected\n"); - log("from two options based on the signedness of the operands to the $mul cell.\n"); + log("This pass replaces multiplier cells with a radix-4 Booth-encoded implementation.\n"); + log("It operates on $mul cells whose width of operands is at least 4x4 and whose\n"); + log("width of result is at least 8.\n"); log("\n"); - log("See the references below for the description of the architectures.\n"); - log("\n"); - log("Signed-multiplier architecture:\n"); - log("Y. J. Chang, Y. C. Cheng, S. C. Liao and C. H. Hsiao, \"A Low Power Radix-4 Booth\n"); - log("Multiplier With Pre-Encoded Mechanism,\" in IEEE Access, vol. 8, pp. 114842-114853,\n"); - log("2020, doi: 10.1109/ACCESS.2020.3003684\n"); - log("\n"); - log("Unsigned-multiplier architecture:\n"); - log("G. W. Bewick, \"Fast Multiplication: Algorithms and Implementations,\" PhD Thesis,\n"); - log("Department of Electrical Engineering, Stanford University, 1994\n"); + log(" -lowpower\n"); + log(" use an alternative low-power architecture for the generated multiplier\n"); + log(" (signed multipliers only)\n"); log("\n"); } void execute(vector args, RTLIL::Design *design) override From beb5cb55a537086dd066aca4e29248cbac44a417 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 22 Nov 2023 14:57:13 +0100 Subject: [PATCH 157/240] booth: Expose `-lowpower` option --- passes/techmap/booth.cc | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 0830f97662d..5814002368a 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -66,6 +66,7 @@ struct BoothPassWorker { RTLIL::Module *module; SigMap sigmap; int booth_counter; + bool lowpower = false; BoothPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; } @@ -276,12 +277,20 @@ struct BoothPassWorker { } log_assert(GetSize(Y) == required_op_size); - CreateBoothMult(module, - A, // multiplicand - B, // multiplier(scanned) - Y, // result - is_signed - ); + if (!lowpower) + CreateBoothMult(module, + A, // multiplicand + B, // multiplier(scanned) + Y, // result + is_signed + ); + else + CreateBoothLowpowerMult(module, + A, // multiplicand + B, // multiplier(scanned) + Y, // result + is_signed + ); module->remove(cell); booth_counter++; @@ -904,12 +913,15 @@ struct BoothPassWorker { } /* - Signed Multiplier + Low-power Multiplier */ - void CreateBoothSMult(RTLIL::Module *module, SigSpec X, SigSpec Y, SigSpec Z) + void CreateBoothLowpowerMult(RTLIL::Module *module, SigSpec X, SigSpec Y, SigSpec Z, bool is_signed) { // product int x_sz = X.size(), y_sz = Y.size(), z_sz = Z.size(); + if (!is_signed) + log_error("Low-power Booth architecture is only supported on signed multipliers.\n"); + unsigned enc_count = (y_sz / 2) + (((y_sz % 2) != 0) ? 1 : 0); int dec_count = x_sz + 1; @@ -1118,8 +1130,13 @@ struct BoothPass : public Pass { log_header(design, "Executing BOOTH pass (map to Booth multipliers).\n"); size_t argidx; + bool lowpower = false; for (argidx = 1; argidx < args.size(); argidx++) { break; + if (args[argidx] == "-lowpower") + lowpower = true; + else + break; } extra_args(args, argidx, design); @@ -1128,6 +1145,7 @@ struct BoothPass : public Pass { for (auto mod : design->selected_modules()) { if (!mod->has_processes_warn()) { BoothPassWorker worker(mod); + worker.lowpower = lowpower; worker.run(); total += worker.booth_counter; } From d6566eb3443856ce3f54444fb542e60c4c2f3d19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 22 Nov 2023 14:59:54 +0100 Subject: [PATCH 158/240] booth: Redo baseline architecture summation Redo the summation logic: strive for some degree of balance on the generated Wallace tree, emit an `$add` cell for the final summation. --- passes/techmap/booth.cc | 55 ++++++++++++++++++++++++++++++++--------- 1 file changed, 44 insertions(+), 11 deletions(-) diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 5814002368a..09c20b50712 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -67,6 +67,7 @@ struct BoothPassWorker { SigMap sigmap; int booth_counter; bool lowpower = false; + bool mapped_cpa = false; BoothPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; } @@ -297,6 +298,36 @@ struct BoothPassWorker { } } + SigSig WallaceSum(int width, std::vector summands) + { + for (auto &s : summands) + s.extend_u0(width); + + while (summands.size() > 2) { + std::vector new_summands; + int i; + for (i = 0; i < (int) summands.size() - 2; i += 3) { + SigSpec x = module->addWire(NEW_ID, width); + SigSpec y = module->addWire(NEW_ID, width); + BuildBitwiseFa(module, NEW_ID.str(), summands[i], summands[i + 1], + summands[i + 2], x, y); + new_summands.push_back(y); + new_summands.push_back({x.extract(0, width - 1), State::S0}); + } + + new_summands.insert(new_summands.begin(), summands.begin() + i, summands.end()); + + std::swap(summands, new_summands); + } + + if (!summands.size()) + return SigSig(SigSpec(width, State::S0), SigSpec(width, State::S0)); + else if (summands.size() == 1) + return SigSig(summands[0], SigSpec(width, State::S0)); + else + return SigSig(summands[0], summands[1]); + } + /* Build Multiplier. ------------------------- @@ -365,19 +396,16 @@ struct BoothPassWorker { // Later on yosys will clean up unused constants // DebugDumpAlignPP(aligned_pp); - SigSpec s_vec; - SigSpec c_vec; - std::vector> debug_csa_trees; - - debug_csa_trees.resize(z_sz); - - BuildCSATree(module, aligned_pp, s_vec, c_vec, debug_csa_trees); + SigSig wtree_sum = WallaceSum(z_sz, aligned_pp); // Debug code: Dump out the csa trees // DumpCSATrees(debug_csa_trees); // Build the CPA to do the final accumulation. - - BuildCPA(module, s_vec, c_vec, Z); + log_assert(wtree_sum.second[0] == State::S0); + if (mapped_cpa) + BuildCPA(module, wtree_sum.first, {State::S0, wtree_sum.second.extract_end(1)}, Z); + else + module->addAdd(NEW_ID, wtree_sum.first, {wtree_sum.second.extract_end(1), State::S0}, Z); } /* @@ -1130,10 +1158,14 @@ struct BoothPass : public Pass { log_header(design, "Executing BOOTH pass (map to Booth multipliers).\n"); size_t argidx; + bool mapped_cpa = false; bool lowpower = false; for (argidx = 1; argidx < args.size(); argidx++) { - break; - if (args[argidx] == "-lowpower") + if (args[argidx] == "-mapped_cpa") + // Have an undocumented option which helps with multiplier + // verification using specialized tools (AMulet2 in particular) + mapped_cpa = true; + else if (args[argidx] == "-lowpower") lowpower = true; else break; @@ -1145,6 +1177,7 @@ struct BoothPass : public Pass { for (auto mod : design->selected_modules()) { if (!mod->has_processes_warn()) { BoothPassWorker worker(mod); + worker.mapped_cpa = mapped_cpa; worker.lowpower = lowpower; worker.run(); total += worker.booth_counter; From de16cd253dfa55d1314aeadf955e877d17020991 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 7 Nov 2023 14:33:09 +0100 Subject: [PATCH 159/240] synth_lattice: Enable `booth` by default on XO3 --- techlibs/lattice/synth_lattice.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index f54f52c3df1..cc5821ad832 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -362,6 +362,8 @@ struct SynthLatticePass : public ScriptPass run("techmap -map +/mul2dsp.v -map +/lattice/dsp_map" + dsp_map + ".v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)"); run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)"); } + if (family == "xo3" || help_mode) + run("booth", "(only if '-family xo3')"); run("alumacc"); run("opt"); run("memory -nomap" + no_rw_check_opt); From 8f207eed1baf85ad185c7139729b10f9756a0041 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 23 Nov 2023 11:01:49 +0100 Subject: [PATCH 160/240] Add attributes to module instantiation --- frontends/verific/verific.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9737fde89c2..ce687601fec 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1980,6 +1980,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma } RTLIL::Cell *cell = module->addCell(inst_name, inst_type); + import_attributes(cell->attributes, inst); if (inst->IsPrimitive() && mode_keep) cell->attributes[ID::keep] = 1; From 031ad38b5cc2410823089e1990cd68694a4a9bb3 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 24 Nov 2023 00:15:38 +0000 Subject: [PATCH 161/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 2aeade5d441..a6fd38de25f 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.35+36 +YOSYS_VER := 0.35+39 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 3dd5262355c8a550d17c92de49910cb10b4c544b Mon Sep 17 00:00:00 2001 From: Catherine Date: Tue, 28 Nov 2023 11:31:21 +0000 Subject: [PATCH 162/240] Add *.dwo files to .gitignore These files are generated in `-gsplit-dwarf` builds, which provide faster linking. --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 9b799c1f38d..6e4ffea4203 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,6 @@ *.o *.d +*.dwo .*.swp *.gch *.gcda From 62bbd086b1c3695f00a8b096b4d454b7602df068 Mon Sep 17 00:00:00 2001 From: Catherine Date: Tue, 28 Nov 2023 12:09:47 +0000 Subject: [PATCH 163/240] cxxrtl: reorganize runtime component files. In preparation for substantial expansion of CXXRTL's runtime, this commit reorganizes the files used by the implementation. Only minimal changes are required in a consumer. First, change: -I$(yosys-config --datdir)/include to: -I$(yosys-config --datdir)/include/backends/cxxrtl/runtime Second, change: #include to: #include (and do the same for cxxrtl_vcd.h, etc.) --- Makefile | 12 ++++++------ backends/cxxrtl/cxxrtl_backend.cc | 10 +++++----- backends/cxxrtl/runtime/README.txt | 18 ++++++++++++++++++ .../{ => runtime/cxxrtl/capi}/cxxrtl_capi.cc | 6 +++--- .../{ => runtime/cxxrtl/capi}/cxxrtl_capi.h | 0 .../cxxrtl/capi/cxxrtl_capi_vcd.cc} | 6 +++--- .../cxxrtl/capi/cxxrtl_capi_vcd.h} | 6 +++--- backends/cxxrtl/{ => runtime/cxxrtl}/cxxrtl.h | 3 ++- .../cxxrtl/{ => runtime/cxxrtl}/cxxrtl_vcd.h | 2 +- tests/fmt/run-test.sh | 4 ++-- 10 files changed, 43 insertions(+), 24 deletions(-) create mode 100644 backends/cxxrtl/runtime/README.txt rename backends/cxxrtl/{ => runtime/cxxrtl/capi}/cxxrtl_capi.cc (97%) rename backends/cxxrtl/{ => runtime/cxxrtl/capi}/cxxrtl_capi.h (100%) rename backends/cxxrtl/{cxxrtl_vcd_capi.cc => runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc} (95%) rename backends/cxxrtl/{cxxrtl_vcd_capi.h => runtime/cxxrtl/capi/cxxrtl_capi_vcd.h} (97%) rename backends/cxxrtl/{ => runtime/cxxrtl}/cxxrtl.h (99%) rename backends/cxxrtl/{ => runtime/cxxrtl}/cxxrtl_vcd.h (99%) diff --git a/Makefile b/Makefile index a6fd38de25f..397e2035c71 100644 --- a/Makefile +++ b/Makefile @@ -647,12 +647,12 @@ $(eval $(call add_include_file,frontends/ast/ast.h)) $(eval $(call add_include_file,frontends/ast/ast_binding.h)) $(eval $(call add_include_file,frontends/blif/blifparse.h)) $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) -$(eval $(call add_include_file,backends/cxxrtl/cxxrtl.h)) -$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd.h)) -$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_capi.cc)) -$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_capi.h)) -$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.cc)) -$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.h)) +$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/cxxrtl.h)) +$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h)) +$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc)) +$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h)) +$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc)) +$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h)) OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o OBJS += kernel/binding.o diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 3fd4857bd51..a322ed3085c 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -2536,7 +2536,7 @@ struct CxxrtlWorker { f << "#define " << include_guard << "\n"; f << "\n"; if (top_module != nullptr && debug_info) { - f << "#include \n"; + f << "#include \n"; f << "\n"; f << "#ifdef __cplusplus\n"; f << "extern \"C\" {\n"; @@ -2554,7 +2554,7 @@ struct CxxrtlWorker { } f << "#ifdef __cplusplus\n"; f << "\n"; - f << "#include \n"; + f << "#include \n"; f << "\n"; f << "using namespace cxxrtl;\n"; f << "\n"; @@ -2573,17 +2573,17 @@ struct CxxrtlWorker { if (split_intf) f << "#include \"" << intf_filename << "\"\n"; else - f << "#include \n"; + f << "#include \n"; if (has_prints) f << "#include \n"; f << "\n"; f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n"; f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n"; - f << "#include \n"; + f << "#include \n"; f << "#endif\n"; f << "\n"; f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n"; - f << "#include \n"; + f << "#include \n"; f << "#endif\n"; f << "\n"; f << "using namespace cxxrtl_yosys;\n"; diff --git a/backends/cxxrtl/runtime/README.txt b/backends/cxxrtl/runtime/README.txt new file mode 100644 index 00000000000..9ae7051cdcc --- /dev/null +++ b/backends/cxxrtl/runtime/README.txt @@ -0,0 +1,18 @@ +This directory contains the runtime components of CXXRTL and should be placed on the include path +when building the simulation using the `-I${YOSYS}/backends/cxxrtl/runtime` option. These components +are not used in the Yosys binary; they are only built as a part of the simulation binary. + +The interfaces declared in `cxxrtl_capi*.h` contain the stable C API. These interfaces will not be +changed in backward-incompatible ways unless no other option is available, and any breaking changes +will be made in a way that causes the downstream code to fail in a visible way. The ABI of these +interfaces is considered stable as well, and it will not use features complicating its use via +libraries such as libffi or ctypes. + +The implementations in `cxxrtl_capi*.cc` are considered private; they are still placed in the include +path to enable build-system-less builds (where the CXXRTL runtime component is included in the C++ +file of the simulation toplevel). + +The interfaces declared in `cxxrtl*.h` (without `capi`) are unstable and may change without notice. + +For clarity, all of the files in this directory and its subdirectories have unique names regardless +of the directory where they are placed. \ No newline at end of file diff --git a/backends/cxxrtl/cxxrtl_capi.cc b/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc similarity index 97% rename from backends/cxxrtl/cxxrtl_capi.cc rename to backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc index d50ddcd6941..593e067a181 100644 --- a/backends/cxxrtl/cxxrtl_capi.cc +++ b/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc @@ -16,10 +16,10 @@ * */ -// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_capi.h`. +// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl/capi/cxxrtl_capi.h`. -#include -#include +#include +#include struct _cxxrtl_handle { std::unique_ptr module; diff --git a/backends/cxxrtl/cxxrtl_capi.h b/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h similarity index 100% rename from backends/cxxrtl/cxxrtl_capi.h rename to backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h diff --git a/backends/cxxrtl/cxxrtl_vcd_capi.cc b/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc similarity index 95% rename from backends/cxxrtl/cxxrtl_vcd_capi.cc rename to backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc index 52a9198b869..0949a9363eb 100644 --- a/backends/cxxrtl/cxxrtl_vcd_capi.cc +++ b/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc @@ -16,10 +16,10 @@ * */ -// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.h`. +// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl/capi/cxxrtl_capi_vcd.h`. -#include -#include +#include +#include extern const cxxrtl::debug_items &cxxrtl_debug_items_from_handle(cxxrtl_handle handle); diff --git a/backends/cxxrtl/cxxrtl_vcd_capi.h b/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h similarity index 97% rename from backends/cxxrtl/cxxrtl_vcd_capi.h rename to backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h index d55afe2230e..844f3cb8c83 100644 --- a/backends/cxxrtl/cxxrtl_vcd_capi.h +++ b/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h @@ -16,8 +16,8 @@ * */ -#ifndef CXXRTL_VCD_CAPI_H -#define CXXRTL_VCD_CAPI_H +#ifndef CXXRTL_CAPI_VCD_H +#define CXXRTL_CAPI_VCD_H // This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.cc`. // @@ -27,7 +27,7 @@ #include #include -#include +#include #ifdef __cplusplus extern "C" { diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h similarity index 99% rename from backends/cxxrtl/cxxrtl.h rename to backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index b2871ee19df..c1cc81e44a2 100644 --- a/backends/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -39,7 +39,8 @@ #include #include -#include +// `cxxrtl::debug_item` has to inherit from `cxxrtl_object` to satisfy strict aliasing requirements. +#include #ifndef __has_attribute # define __has_attribute(x) 0 diff --git a/backends/cxxrtl/cxxrtl_vcd.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h similarity index 99% rename from backends/cxxrtl/cxxrtl_vcd.h rename to backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h index b76922bbd8a..cb2ccf5fc26 100644 --- a/backends/cxxrtl/cxxrtl_vcd.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h @@ -19,7 +19,7 @@ #ifndef CXXRTL_VCD_H #define CXXRTL_VCD_H -#include +#include namespace cxxrtl { diff --git a/tests/fmt/run-test.sh b/tests/fmt/run-test.sh index 914a7234747..5b28c18c120 100644 --- a/tests/fmt/run-test.sh +++ b/tests/fmt/run-test.sh @@ -51,7 +51,7 @@ test_cxxrtl () { local subtest=$1; shift ../../yosys -p "read_verilog ${subtest}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-${subtest}.cc" - ${CC:-gcc} -std=c++11 -o yosys-${subtest} -I../.. ${subtest}_tb.cc -lstdc++ + ${CC:-gcc} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++ ./yosys-${subtest} 2>yosys-${subtest}.log iverilog -o iverilog-${subtest} ${subtest}.v ${subtest}_tb.v ./iverilog-${subtest} |grep -v '\$finish called' >iverilog-${subtest}.log @@ -69,7 +69,7 @@ diff iverilog-always_full.log iverilog-always_full-1.log ../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log ../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc" -${CC:-gcc} -std=c++11 -o yosys-display_lm_cc -I../.. display_lm_tb.cc -lstdc++ +${CC:-gcc} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++ ./yosys-display_lm_cc >yosys-display_lm_cc.log for log in yosys-display_lm.log yosys-display_lm_cc.log; do grep "^%l: \\\\bot\$" "$log" From 8614d9b32f588ee14f615a4c98bb6ddc9ea35556 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 29 Nov 2023 00:16:09 +0000 Subject: [PATCH 164/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 397e2035c71..a00ffccf8ae 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.35+39 +YOSYS_VER := 0.35+56 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From bf955cc2b03d5fd657907a212c56f05aada5b15c Mon Sep 17 00:00:00 2001 From: gatecat Date: Fri, 1 Dec 2023 10:20:21 +0100 Subject: [PATCH 165/240] nexus: Fix format strings to remove space padding Signed-off-by: gatecat --- techlibs/nexus/brams_map.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/techlibs/nexus/brams_map.v b/techlibs/nexus/brams_map.v index cec56cec4ab..dbcee5c41c7 100644 --- a/techlibs/nexus/brams_map.v +++ b/techlibs/nexus/brams_map.v @@ -134,8 +134,8 @@ DP16K #( .INITVAL_3D($sformatf("0x%080x", init_slice('h3d))), .INITVAL_3E($sformatf("0x%080x", init_slice('h3e))), .INITVAL_3F($sformatf("0x%080x", init_slice('h3f))), - .DATA_WIDTH_A($sformatf("X%d", PORT_A_WIDTH)), - .DATA_WIDTH_B($sformatf("X%d", PORT_B_WIDTH)), + .DATA_WIDTH_A($sformatf("X%0d", PORT_A_WIDTH)), + .DATA_WIDTH_B($sformatf("X%0d", PORT_B_WIDTH)), .OUTREG_A("BYPASSED"), .OUTREG_B("BYPASSED"), .RESETMODE_A(PORT_A_OPTION_RESETMODE), @@ -298,8 +298,8 @@ PDPSC16K #( .INITVAL_3D($sformatf("0x%080x", init_slice('h3d))), .INITVAL_3E($sformatf("0x%080x", init_slice('h3e))), .INITVAL_3F($sformatf("0x%080x", init_slice('h3f))), - .DATA_WIDTH_W($sformatf("X%d", PORT_W_WIDTH)), - .DATA_WIDTH_R($sformatf("X%d", PORT_R_WIDTH)), + .DATA_WIDTH_W($sformatf("X%0d", PORT_W_WIDTH)), + .DATA_WIDTH_R($sformatf("X%0d", PORT_R_WIDTH)), .OUTREG("BYPASSED"), .RESETMODE(PORT_R_OPTION_RESETMODE), .ASYNC_RST_RELEASE(PORT_R_OPTION_RESETMODE), @@ -389,8 +389,8 @@ PDP16K #( .INITVAL_3D($sformatf("0x%080x", init_slice('h3d))), .INITVAL_3E($sformatf("0x%080x", init_slice('h3e))), .INITVAL_3F($sformatf("0x%080x", init_slice('h3f))), - .DATA_WIDTH_W($sformatf("X%d", PORT_W_WIDTH)), - .DATA_WIDTH_R($sformatf("X%d", PORT_R_WIDTH)), + .DATA_WIDTH_W($sformatf("X%0d", PORT_W_WIDTH)), + .DATA_WIDTH_R($sformatf("X%0d", PORT_R_WIDTH)), .OUTREG("BYPASSED"), .RESETMODE(PORT_R_OPTION_RESETMODE), .ASYNC_RST_RELEASE(PORT_R_OPTION_RESETMODE), From 8bd681acfc3b0913e57f6312ed357b2334cf19cb Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 4 Dec 2023 00:16:38 +0000 Subject: [PATCH 166/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a00ffccf8ae..b980bfdd211 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.35+56 +YOSYS_VER := 0.35+58 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 98769010afc4a57f3ce8c359c1c6e88a864c5986 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Fri, 7 Jul 2023 15:27:21 +0200 Subject: [PATCH 167/240] synth_quicklogic: rearrange files to prepare for adding more architectures --- techlibs/quicklogic/Makefile.inc | 19 +++-- techlibs/quicklogic/{ => common}/cells_sim.v | 0 techlibs/quicklogic/lut_sim.v | 76 ------------------ techlibs/quicklogic/{ => pp3}/abc9_map.v | 0 techlibs/quicklogic/{ => pp3}/abc9_model.v | 0 techlibs/quicklogic/{ => pp3}/abc9_unmap.v | 0 .../{pp3_cells_map.v => pp3/cells_map.v} | 0 .../{pp3_cells_sim.v => pp3/cells_sim.v} | 77 +++++++++++++++++++ .../{pp3_ffs_map.v => pp3/ffs_map.v} | 0 .../{pp3_latches_map.v => pp3/latches_map.v} | 0 .../{pp3_lut_map.v => pp3/lut_map.v} | 0 techlibs/quicklogic/synth_quicklogic.cc | 50 +++++++++--- tests/arch/quicklogic/add_sub.ys | 2 +- tests/arch/quicklogic/adffs.ys | 8 +- tests/arch/quicklogic/counter.ys | 2 +- tests/arch/quicklogic/dffs.ys | 4 +- tests/arch/quicklogic/fsm.ys | 2 +- tests/arch/quicklogic/logic.ys | 2 +- tests/arch/quicklogic/mux.ys | 8 +- tests/arch/quicklogic/tribuf.ys | 2 +- 20 files changed, 139 insertions(+), 113 deletions(-) rename techlibs/quicklogic/{ => common}/cells_sim.v (100%) delete mode 100644 techlibs/quicklogic/lut_sim.v rename techlibs/quicklogic/{ => pp3}/abc9_map.v (100%) rename techlibs/quicklogic/{ => pp3}/abc9_model.v (100%) rename techlibs/quicklogic/{ => pp3}/abc9_unmap.v (100%) rename techlibs/quicklogic/{pp3_cells_map.v => pp3/cells_map.v} (100%) rename techlibs/quicklogic/{pp3_cells_sim.v => pp3/cells_sim.v} (76%) rename techlibs/quicklogic/{pp3_ffs_map.v => pp3/ffs_map.v} (100%) rename techlibs/quicklogic/{pp3_latches_map.v => pp3/latches_map.v} (100%) rename techlibs/quicklogic/{pp3_lut_map.v => pp3/lut_map.v} (100%) diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index 51eb28d44bd..43d8fdf7990 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,13 +1,12 @@ OBJS += techlibs/quicklogic/synth_quicklogic.o -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_ffs_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_lut_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_latches_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/cells_sim.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/lut_sim.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_sim.v)) +$(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_model.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_unmap.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/ffs_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/lut_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/latches_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_sim.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_model.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_unmap.v)) diff --git a/techlibs/quicklogic/cells_sim.v b/techlibs/quicklogic/common/cells_sim.v similarity index 100% rename from techlibs/quicklogic/cells_sim.v rename to techlibs/quicklogic/common/cells_sim.v diff --git a/techlibs/quicklogic/lut_sim.v b/techlibs/quicklogic/lut_sim.v deleted file mode 100644 index 851ce4d6845..00000000000 --- a/techlibs/quicklogic/lut_sim.v +++ /dev/null @@ -1,76 +0,0 @@ -(* abc9_lut=1, lib_whitebox *) -module LUT1 ( - output O, - input I0 -); - parameter [1:0] INIT = 0; - parameter EQN = "(I0)"; - - // These timings are for PolarPro 3E; other families will need updating. - specify - (I0 => O) = 698; // FS -> FZ - endspecify - - assign O = I0 ? INIT[1] : INIT[0]; -endmodule - -// TZ TSL TAB -(* abc9_lut=2, lib_whitebox *) -module LUT2 ( - output O, - input I0, I1 -); - parameter [3:0] INIT = 4'h0; - parameter EQN = "(I0)"; - - // These timings are for PolarPro 3E; other families will need updating. - specify - (I0 => O) = 1251; // TAB -> TZ - (I1 => O) = 1406; // TSL -> TZ - endspecify - - wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule - -(* abc9_lut=2, lib_whitebox *) -module LUT3 ( - output O, - input I0, I1, I2 -); - parameter [7:0] INIT = 8'h0; - parameter EQN = "(I0)"; - - // These timings are for PolarPro 3E; other families will need updating. - specify - (I0 => O) = 1251; // TAB -> TZ - (I1 => O) = 1406; // TSL -> TZ - (I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ - endspecify - - wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0]; - wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule - -(* abc9_lut=4, lib_whitebox *) -module LUT4 ( - output O, - input I0, I1, I2, I3 -); - parameter [15:0] INIT = 16'h0; - parameter EQN = "(I0)"; - - // These timings are for PolarPro 3E; other families will need updating. - specify - (I0 => O) = 995; // TBS -> CZ - (I1 => O) = 1437; // ('TAB', 'BAB') -> CZ - (I2 => O) = 1593; // ('TSL', 'BSL') -> CZ - (I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ - endspecify - - wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0]; - wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0]; - wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule diff --git a/techlibs/quicklogic/abc9_map.v b/techlibs/quicklogic/pp3/abc9_map.v similarity index 100% rename from techlibs/quicklogic/abc9_map.v rename to techlibs/quicklogic/pp3/abc9_map.v diff --git a/techlibs/quicklogic/abc9_model.v b/techlibs/quicklogic/pp3/abc9_model.v similarity index 100% rename from techlibs/quicklogic/abc9_model.v rename to techlibs/quicklogic/pp3/abc9_model.v diff --git a/techlibs/quicklogic/abc9_unmap.v b/techlibs/quicklogic/pp3/abc9_unmap.v similarity index 100% rename from techlibs/quicklogic/abc9_unmap.v rename to techlibs/quicklogic/pp3/abc9_unmap.v diff --git a/techlibs/quicklogic/pp3_cells_map.v b/techlibs/quicklogic/pp3/cells_map.v similarity index 100% rename from techlibs/quicklogic/pp3_cells_map.v rename to techlibs/quicklogic/pp3/cells_map.v diff --git a/techlibs/quicklogic/pp3_cells_sim.v b/techlibs/quicklogic/pp3/cells_sim.v similarity index 76% rename from techlibs/quicklogic/pp3_cells_sim.v rename to techlibs/quicklogic/pp3/cells_sim.v index 5820d7a9ec0..201a7d33331 100644 --- a/techlibs/quicklogic/pp3_cells_sim.v +++ b/techlibs/quicklogic/pp3/cells_sim.v @@ -327,3 +327,80 @@ module qlal4s3b_cell_macro ( ); endmodule + +(* abc9_lut=1, lib_whitebox *) +module LUT1 ( + output O, + input I0 +); + parameter [1:0] INIT = 0; + parameter EQN = "(I0)"; + + // These timings are for PolarPro 3E; other families will need updating. + specify + (I0 => O) = 698; // FS -> FZ + endspecify + + assign O = I0 ? INIT[1] : INIT[0]; +endmodule + +// TZ TSL TAB +(* abc9_lut=2, lib_whitebox *) +module LUT2 ( + output O, + input I0, I1 +); + parameter [3:0] INIT = 4'h0; + parameter EQN = "(I0)"; + + // These timings are for PolarPro 3E; other families will need updating. + specify + (I0 => O) = 1251; // TAB -> TZ + (I1 => O) = 1406; // TSL -> TZ + endspecify + + wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +(* abc9_lut=2, lib_whitebox *) +module LUT3 ( + output O, + input I0, I1, I2 +); + parameter [7:0] INIT = 8'h0; + parameter EQN = "(I0)"; + + // These timings are for PolarPro 3E; other families will need updating. + specify + (I0 => O) = 1251; // TAB -> TZ + (I1 => O) = 1406; // TSL -> TZ + (I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ + endspecify + + wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0]; + wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +(* abc9_lut=4, lib_whitebox *) +module LUT4 ( + output O, + input I0, I1, I2, I3 +); + parameter [15:0] INIT = 16'h0; + parameter EQN = "(I0)"; + + // These timings are for PolarPro 3E; other families will need updating. + specify + (I0 => O) = 995; // TBS -> CZ + (I1 => O) = 1437; // ('TAB', 'BAB') -> CZ + (I2 => O) = 1593; // ('TSL', 'BSL') -> CZ + (I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ + endspecify + + wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0]; + wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0]; + wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule diff --git a/techlibs/quicklogic/pp3_ffs_map.v b/techlibs/quicklogic/pp3/ffs_map.v similarity index 100% rename from techlibs/quicklogic/pp3_ffs_map.v rename to techlibs/quicklogic/pp3/ffs_map.v diff --git a/techlibs/quicklogic/pp3_latches_map.v b/techlibs/quicklogic/pp3/latches_map.v similarity index 100% rename from techlibs/quicklogic/pp3_latches_map.v rename to techlibs/quicklogic/pp3/latches_map.v diff --git a/techlibs/quicklogic/pp3_lut_map.v b/techlibs/quicklogic/pp3/lut_map.v similarity index 100% rename from techlibs/quicklogic/pp3_lut_map.v rename to techlibs/quicklogic/pp3/lut_map.v diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 94bd44db008..7fddbc97078 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -60,13 +60,14 @@ struct SynthQuickLogicPass : public ScriptPass { log("\n"); } - string top_opt, blif_file, family, currmodule, verilog_file; + string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path; bool abc9; void clear_flags() override { top_opt = "-auto-top"; blif_file = ""; + edif_file = ""; verilog_file = ""; currmodule = ""; family = "pp3"; @@ -81,6 +82,14 @@ struct SynthQuickLogicPass : public ScriptPass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } if (args[argidx] == "-top" && argidx+1 < args.size()) { top_opt = "-top " + args[++argidx]; continue; @@ -93,6 +102,10 @@ struct SynthQuickLogicPass : public ScriptPass { blif_file = args[++argidx]; continue; } + if (args[argidx] == "-edif" && argidx + 1 < args.size()) { + edif_file = args[++argidx]; + continue; + } if (args[argidx] == "-verilog" && argidx+1 < args.size()) { verilog_file = args[++argidx]; continue; @@ -126,13 +139,16 @@ struct SynthQuickLogicPass : public ScriptPass { void script() override { + if (help_mode) { + family = ""; + } + if (check_label("begin")) { - run(stringf("read_verilog -lib -specify +/quicklogic/cells_sim.v +/quicklogic/%s_cells_sim.v", family.c_str())); - run("read_verilog -lib -specify +/quicklogic/lut_sim.v"); + run(stringf("read_verilog -lib -specify +/quicklogic/common/cells_sim.v +/quicklogic/%s/cells_sim.v", family.c_str())); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } - if (check_label("coarse")) { + if (check_label("prepare")) { run("proc"); run("flatten"); run("tribuf -logic"); @@ -147,6 +163,9 @@ struct SynthQuickLogicPass : public ScriptPass { run("peepopt"); run("opt_clean"); run("share"); + } + + if (check_label("coarse")) { run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); run("opt_expr"); run("opt_clean"); @@ -175,18 +194,18 @@ struct SynthQuickLogicPass : public ScriptPass { run("opt_expr"); run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x"); - run(stringf("techmap -map +/quicklogic/%s_cells_map.v -map +/quicklogic/%s_ffs_map.v", family.c_str(), family.c_str())); + run(stringf("techmap -map +/quicklogic/%s/cells_map.v -map +/quicklogic/%s/ffs_map.v", family.c_str(), family.c_str())); run("opt_expr -mux_undef"); } if (check_label("map_luts")) { - run(stringf("techmap -map +/quicklogic/%s_latches_map.v", family.c_str())); + run(stringf("techmap -map +/quicklogic/%s/latches_map.v", family.c_str())); if (abc9) { - run("read_verilog -lib -specify -icells +/quicklogic/abc9_model.v"); - run("techmap -map +/quicklogic/abc9_map.v"); + run(stringf("read_verilog -lib -specify -icells +/quicklogic/%s/abc9_model.v", family.c_str())); + run(stringf("techmap -map +/quicklogic/%s/abc9_map.v", family.c_str())); run("abc9 -maxlut 4 -dff"); - run("techmap -map +/quicklogic/abc9_unmap.v"); + run(stringf("techmap -map +/quicklogic/%s/abc9_unmap.v", family.c_str())); } else { run("abc -luts 1,2,2,4 -dress"); } @@ -194,7 +213,7 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("map_cells")) { - run(stringf("techmap -map +/quicklogic/%s_lut_map.v", family.c_str())); + run(stringf("techmap -map +/quicklogic/%s/lut_map.v", family.c_str())); run("clean"); } @@ -218,17 +237,24 @@ struct SynthQuickLogicPass : public ScriptPass { run("blackbox =A:whitebox"); } - if (check_label("blif")) { + if (check_label("blif", "(if -blif)")) { if (!blif_file.empty() || help_mode) { run(stringf("write_blif -attr -param %s %s", top_opt.c_str(), blif_file.c_str())); } } - if (check_label("verilog")) { + if (check_label("verilog", "(if -verilog)")) { if (!verilog_file.empty() || help_mode) { run(stringf("write_verilog -noattr -nohex %s", help_mode ? "" : verilog_file.c_str())); } } + + if (check_label("edif", "(if -edif)")) { + if (!edif_file.empty() || help_mode) { + run("splitnets -ports -format ()"); + run(stringf("write_edif -nogndvcc -attrprop -pvector par %s %s", top_opt.c_str(), edif_file.c_str())); + } + } } } SynthQuicklogicPass; diff --git a/tests/arch/quicklogic/add_sub.ys b/tests/arch/quicklogic/add_sub.ys index 73ee5cb4413..47db42afc9a 100644 --- a/tests/arch/quicklogic/add_sub.ys +++ b/tests/arch/quicklogic/add_sub.ys @@ -1,6 +1,6 @@ read_verilog ../common/add_sub.v hierarchy -top top -equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 2 t:LUT2 diff --git a/tests/arch/quicklogic/adffs.ys b/tests/arch/quicklogic/adffs.ys index 41a17584427..43f36c20cb5 100644 --- a/tests/arch/quicklogic/adffs.ys +++ b/tests/arch/quicklogic/adffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top adff proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check +equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:dffepc @@ -19,7 +19,7 @@ select -assert-none t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* design -load read hierarchy -top adffn proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:LUT1 @@ -36,7 +36,7 @@ select -assert-none t:LUT1 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad design -load read hierarchy -top dffs proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:LUT2 @@ -53,7 +53,7 @@ select -assert-none t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad design -load read hierarchy -top ndffnr proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:LUT1 diff --git a/tests/arch/quicklogic/counter.ys b/tests/arch/quicklogic/counter.ys index 2e266417caf..9a7dcdf0809 100644 --- a/tests/arch/quicklogic/counter.ys +++ b/tests/arch/quicklogic/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -assert -multiclock -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:LUT1 diff --git a/tests/arch/quicklogic/dffs.ys b/tests/arch/quicklogic/dffs.ys index e1fbef635d8..2bcfbf672de 100644 --- a/tests/arch/quicklogic/dffs.ys +++ b/tests/arch/quicklogic/dffs.ys @@ -5,7 +5,7 @@ design -save read hierarchy -top my_dff proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check +equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd my_dff # Constrain all select calls below inside the top module select -assert-count 1 t:ckpad @@ -20,7 +20,7 @@ select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:logic_1 t:outpad %% t:* design -load read hierarchy -top my_dffe proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check +equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd my_dffe # Constrain all select calls below inside the top module diff --git a/tests/arch/quicklogic/fsm.ys b/tests/arch/quicklogic/fsm.ys index 130dacf42a9..50dcb71b142 100644 --- a/tests/arch/quicklogic/fsm.ys +++ b/tests/arch/quicklogic/fsm.ys @@ -3,7 +3,7 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic +equiv_opt -run :prove -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic async2sync miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter diff --git a/tests/arch/quicklogic/logic.ys b/tests/arch/quicklogic/logic.ys index 4b327c00af7..9c34ddaeb3d 100644 --- a/tests/arch/quicklogic/logic.ys +++ b/tests/arch/quicklogic/logic.ys @@ -1,7 +1,7 @@ read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/quicklogic/mux.ys b/tests/arch/quicklogic/mux.ys index ea17fa99b3d..5214bb7872d 100644 --- a/tests/arch/quicklogic/mux.ys +++ b/tests/arch/quicklogic/mux.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top mux2 proc -equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 @@ -15,7 +15,7 @@ select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module select -assert-count 3 t:LUT3 @@ -27,7 +27,7 @@ select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT1 @@ -41,7 +41,7 @@ select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 diff --git a/tests/arch/quicklogic/tribuf.ys b/tests/arch/quicklogic/tribuf.ys index de763009eaf..d74fbbcdd2a 100644 --- a/tests/arch/quicklogic/tribuf.ys +++ b/tests/arch/quicklogic/tribuf.ys @@ -4,7 +4,7 @@ proc tribuf flatten synth -equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module select -assert-count 2 t:inpad From 48c1fdc33d2fbe4659052376746a2942bc32f0e6 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 27 Nov 2023 09:42:40 +0100 Subject: [PATCH 168/240] add qlf_k6n10f architecture + bram inference (Copied from QuickLogic Yosys plugin repo) --- techlibs/quicklogic/Makefile.inc | 12 + techlibs/quicklogic/ql-bram-merge.cc | 216 + techlibs/quicklogic/qlf_k6n10f/arith_map.v | 99 + .../quicklogic/qlf_k6n10f/bram_types_sim.v | 73373 ++++++++++++++++ .../quicklogic/qlf_k6n10f/brams_final_map.v | 1464 + techlibs/quicklogic/qlf_k6n10f/brams_map.v | 2839 + techlibs/quicklogic/qlf_k6n10f/brams_sim.v | 11081 +++ techlibs/quicklogic/qlf_k6n10f/cells_sim.v | 376 + techlibs/quicklogic/qlf_k6n10f/ffs_map.v | 133 + .../quicklogic/qlf_k6n10f/libmap_brams.txt | 22 + .../quicklogic/qlf_k6n10f/libmap_brams_map.v | 457 + techlibs/quicklogic/quicklogic_eqn.cc | 100 + techlibs/quicklogic/synth_quicklogic.cc | 187 +- 13 files changed, 90338 insertions(+), 21 deletions(-) create mode 100644 techlibs/quicklogic/ql-bram-merge.cc create mode 100644 techlibs/quicklogic/qlf_k6n10f/arith_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/brams_final_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/brams_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/brams_sim.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/cells_sim.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/ffs_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt create mode 100644 techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v create mode 100644 techlibs/quicklogic/quicklogic_eqn.cc diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index 43d8fdf7990..fcc49cd77f8 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,4 +1,6 @@ OBJS += techlibs/quicklogic/synth_quicklogic.o +OBJS += techlibs/quicklogic/ql-bram-merge.o +OBJS += techlibs/quicklogic/quicklogic_eqn.o $(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v)) @@ -10,3 +12,13 @@ $(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_ $(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_model.v)) $(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_map.v)) $(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_unmap.v)) + +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/arith_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_final_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v)) \ No newline at end of file diff --git a/techlibs/quicklogic/ql-bram-merge.cc b/techlibs/quicklogic/ql-bram-merge.cc new file mode 100644 index 00000000000..d64bd64cf60 --- /dev/null +++ b/techlibs/quicklogic/ql-bram-merge.cc @@ -0,0 +1,216 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2023 N. Engelhardt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +// ============================================================================ + + + +struct QlBramMergeWorker { + + const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K); + const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED); + + // can be used to record parameter values that have to match on both sides + typedef dict MergeableGroupKeyType; + + RTLIL::Module *module; + dict> mergeable_groups; + + QlBramMergeWorker(RTLIL::Module* module) : module(module) + { + for (RTLIL::Cell* cell : module->selected_cells()) + { + if(cell->type != split_cell_type) continue; + if(!cell->hasParam(ID(OPTION_SPLIT))) continue; + if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue; + mergeable_groups[get_key(cell)].insert(cell); + } + } + + static MergeableGroupKeyType get_key(RTLIL::Cell* cell) + { + MergeableGroupKeyType key; + // For now, there are no restrictions on which cells can be merged + (void) cell; + return key; + } + + const dict& param_map(bool second) + { + static const dict bram1_map = { + { ID(INIT), ID(INIT1) }, + { ID(PORT_A_WIDTH), ID(PORT_A1_WIDTH) }, + { ID(PORT_B_WIDTH), ID(PORT_B1_WIDTH) }, + { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A1_WR_BE_WIDTH) }, + { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B1_WR_BE_WIDTH) } + }; + static const dict bram2_map = { + { ID(INIT), ID(INIT2) }, + { ID(PORT_A_WIDTH), ID(PORT_A2_WIDTH) }, + { ID(PORT_B_WIDTH), ID(PORT_B2_WIDTH) }, + { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A2_WR_BE_WIDTH) }, + { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B2_WR_BE_WIDTH) } + }; + + if(second) + return bram2_map; + else + return bram1_map; + } + + const dict& port_map(bool second) + { + static const dict bram1_map = { + { ID(PORT_A_CLK), ID(PORT_A1_CLK) }, + { ID(PORT_B_CLK), ID(PORT_B1_CLK) }, + { ID(PORT_A_CLK_EN), ID(PORT_A1_CLK_EN) }, + { ID(PORT_B_CLK_EN), ID(PORT_B1_CLK_EN) }, + { ID(PORT_A_ADDR), ID(PORT_A1_ADDR) }, + { ID(PORT_B_ADDR), ID(PORT_B1_ADDR) }, + { ID(PORT_A_WR_DATA), ID(PORT_A1_WR_DATA) }, + { ID(PORT_B_WR_DATA), ID(PORT_B1_WR_DATA) }, + { ID(PORT_A_WR_EN), ID(PORT_A1_WR_EN) }, + { ID(PORT_B_WR_EN), ID(PORT_B1_WR_EN) }, + { ID(PORT_A_WR_BE), ID(PORT_A1_WR_BE) }, + { ID(PORT_B_WR_BE), ID(PORT_B1_WR_BE) }, + { ID(PORT_A_RD_DATA), ID(PORT_A1_RD_DATA) }, + { ID(PORT_B_RD_DATA), ID(PORT_B1_RD_DATA) } + }; + static const dict bram2_map = { + { ID(PORT_A_CLK), ID(PORT_A2_CLK) }, + { ID(PORT_B_CLK), ID(PORT_B2_CLK) }, + { ID(PORT_A_CLK_EN), ID(PORT_A2_CLK_EN) }, + { ID(PORT_B_CLK_EN), ID(PORT_B2_CLK_EN) }, + { ID(PORT_A_ADDR), ID(PORT_A2_ADDR) }, + { ID(PORT_B_ADDR), ID(PORT_B2_ADDR) }, + { ID(PORT_A_WR_DATA), ID(PORT_A2_WR_DATA) }, + { ID(PORT_B_WR_DATA), ID(PORT_B2_WR_DATA) }, + { ID(PORT_A_WR_EN), ID(PORT_A2_WR_EN) }, + { ID(PORT_B_WR_EN), ID(PORT_B2_WR_EN) }, + { ID(PORT_A_WR_BE), ID(PORT_A2_WR_BE) }, + { ID(PORT_B_WR_BE), ID(PORT_B2_WR_BE) }, + { ID(PORT_A_RD_DATA), ID(PORT_A2_RD_DATA) }, + { ID(PORT_B_RD_DATA), ID(PORT_B2_RD_DATA) } + }; + + if(second) + return bram2_map; + else + return bram1_map; + } + + void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2) + { + + // Create the new cell + RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type); + log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name)); + + for (auto &it : param_map(false)) + { + if(bram1->hasParam(it.first)) + merged->setParam(it.second, bram1->getParam(it.first)); + } + for (auto &it : param_map(true)) + { + if(bram2->hasParam(it.first)) + merged->setParam(it.second, bram2->getParam(it.first)); + } + + for (auto &it : port_map(false)) + { + if (bram1->hasPort(it.first)) + merged->setPort(it.second, bram1->getPort(it.first)); + else + log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name)); + } + for (auto &it : port_map(true)) + { + if (bram2->hasPort(it.first)) + merged->setPort(it.second, bram2->getPort(it.first)); + else + log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name)); + } + merged->attributes = bram1->attributes; + for (auto attr: bram2->attributes) + if (!merged->has_attribute(attr.first)) + merged->attributes.insert(attr); + + // Remove the old cells + module->remove(bram1); + module->remove(bram2); + + } + + void merge_bram_groups() + { + for (auto &it : mergeable_groups) + { + while (it.second.size() > 1) + { + merge_brams(it.second.pop(), it.second.pop()); + } + } + } + +}; + +struct QlBramMergePass : public Pass { + + QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_bram_merge [selection]\n"); + log("\n"); + log(" This pass identifies k6n10f 18K BRAM cells and packs pairs of them together\n"); + log(" into a TDP36K cell operating in split mode\n"); + log("\n"); + } + + + + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing QL_BRAM_MERGE pass.\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (RTLIL::Module* module : design->selected_modules()) + { + QlBramMergeWorker worker(module); + worker.merge_bram_groups(); + } + } + + +} QlBramMergePass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/qlf_k6n10f/arith_map.v b/techlibs/quicklogic/qlf_k6n10f/arith_map.v new file mode 100644 index 00000000000..908b17189c5 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/arith_map.v @@ -0,0 +1,99 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +(* techmap_celltype = "$alu" *) +module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 2; + parameter B_WIDTH = 2; + parameter Y_WIDTH = 2; + parameter _TECHMAP_CONSTVAL_CI_ = 0; + parameter _TECHMAP_CONSTMSK_CI_ = 0; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + (* force_downto *) + output [Y_WIDTH-1:0] CO; + + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + (* force_downto *) + wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + + genvar i; + wire co; + + (* force_downto *) + //wire [Y_WIDTH-1:0] C = {CO, CI}; + wire [Y_WIDTH:0] C; + (* force_downto *) + wire [Y_WIDTH-1:0] S = {AA ^ BB}; + assign CO[Y_WIDTH-1:0] = C[Y_WIDTH:1]; + //assign CO[Y_WIDTH-1] = co; + + generate + adder_carry intermediate_adder ( + .cin ( ), + .cout (C[0]), + .p (1'b0), + .g (CI), + .sumout () + ); + endgenerate + genvar i; + generate if (Y_WIDTH > 2) begin + for (i = 0; i < Y_WIDTH-2; i = i + 1) begin:slice + adder_carry my_adder ( + .cin(C[i]), + .g(AA[i]), + .p(S[i]), + .cout(C[i+1]), + .sumout(Y[i]) + ); + end + end endgenerate + generate + adder_carry final_adder ( + .cin (C[Y_WIDTH-2]), + .cout (), + .p (1'b0), + .g (1'b0), + .sumout (co) + ); + endgenerate + + assign Y[Y_WIDTH-2] = S[Y_WIDTH-2] ^ co; + assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2]; + assign Y[Y_WIDTH-1] = S[Y_WIDTH-1] ^ C[Y_WIDTH-1]; + assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1]; + + assign X = S; +endmodule + diff --git a/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v b/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v new file mode 100644 index 00000000000..3a06f676d68 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v @@ -0,0 +1,73373 @@ +// **AUTOGENERATED FILE** **DO NOT EDIT** +// Generated by qlf_k6n10f/generate_bram_types_sim.py at 2023-05-02 10:42:53.971682+00:00 + +module TDP36K_BRAM_A_X1_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v new file mode 100644 index 00000000000..7d04c5dda6c --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v @@ -0,0 +1,1464 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module BRAM2x18_SP ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); +localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); +localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); +localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 4'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 4'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A1_WRWIDTH *) +(* port_b_dwidth = PORT_B1_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + +input PORT_A1_CLK_i; +input [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input PORT_A1_WEN_i; +input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input PORT_A1_REN_i; +output [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input PORT_B1_CLK_i; +input [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input PORT_B1_WEN_i; +input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input PORT_B1_REN_i; +output [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input PORT_A2_CLK_i; +input [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input PORT_A2_WEN_i; +input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input PORT_A2_REN_i; +output [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input PORT_B2_CLK_i; +input [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input PORT_B2_WEN_i; +input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input PORT_B2_REN_i; +output [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(PORT_A1_DWIDTH); +localparam PORT_B1_WRWIDTH = rwmode(PORT_B1_DWIDTH); +localparam PORT_A2_WRWIDTH = rwmode(PORT_A2_DWIDTH); +localparam PORT_B2_WRWIDTH = rwmode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A1_WRWIDTH *) +(* port_b_dwidth = PORT_B1_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + + +module BRAM2x18_SFIFO ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + + +module BRAM2x18_AFIFO ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_map.v new file mode 100644 index 00000000000..42e1fc98b85 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/brams_map.v @@ -0,0 +1,2839 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module RAM_36K_BLK ( + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o +); + +parameter WR_ADDR_WIDTH = 10; +parameter RD_ADDR_WIDTH = 10; +parameter WR_DATA_WIDTH = 36; +parameter RD_DATA_WIDTH = 36; +parameter BE_WIDTH = 4; + +parameter INIT = 0; + +input wire WEN_i; +input wire REN_i; +input wire WR_CLK_i; +input wire RD_CLK_i; +input wire [BE_WIDTH-1:0] WR_BE_i; +input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i; +input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; +input wire [WR_DATA_WIDTH-1 :0] WDATA_i; +output wire [RD_DATA_WIDTH-1 :0] RDATA_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +32, 36: rwmode = 36; +default: rwmode = 36; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [3:0] WR_BE; + +wire [35:0] PORT_B_RDATA; +wire [35:0] PORT_A_WDATA; + +wire [14:0] WR_ADDR_INT; +wire [14:0] RD_ADDR_INT; + +wire [14:0] PORT_A_ADDR; +wire [14:0] PORT_B_ADDR; + +wire PORT_A_CLK; +wire PORT_B_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + +localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); +localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + +assign PORT_A_CLK = WR_CLK_i; +assign PORT_B_CLK = RD_CLK_i; + +generate + if (WR_ADDR_WIDTH == 15) begin + assign WR_ADDR_INT = WR_ADDR_i; + end else begin + assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; + assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; + end +endgenerate + +case (WR_DATA_WIDTH) + 1: begin + assign PORT_A_ADDR = WR_ADDR_INT; + end + 2: begin + assign PORT_A_ADDR = WR_ADDR_INT << 1; + end + 4: begin + assign PORT_A_ADDR = WR_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A_ADDR = WR_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A_ADDR = WR_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_A_ADDR = WR_ADDR_INT << 5; + end + default: begin + assign PORT_A_ADDR = WR_ADDR_INT; + end +endcase + +generate + if (RD_ADDR_WIDTH == 15) begin + assign RD_ADDR_INT = RD_ADDR_i; + end else begin + assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; + assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; + end +endgenerate + +case (RD_DATA_WIDTH) + 1: begin + assign PORT_B_ADDR = RD_ADDR_INT; + end + 2: begin + assign PORT_B_ADDR = RD_ADDR_INT << 1; + end + 4: begin + assign PORT_B_ADDR = RD_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B_ADDR = RD_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B_ADDR = RD_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_B_ADDR = RD_ADDR_INT << 5; + end + default: begin + assign PORT_B_ADDR = RD_ADDR_INT; + end +endcase + +case (BE_WIDTH) + 4: begin + assign WR_BE = WR_BE_i[BE_WIDTH-1 :0]; + end + default: begin + assign WR_BE[3:BE_WIDTH] = 0; + assign WR_BE[BE_WIDTH-1 :0] = WR_BE_i[BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN_i; +assign {BE_A2_i, BE_A1_i} = WR_BE; + +assign REN_B1_i = REN_i; +assign WEN_B1_i = 1'b0; +assign {BE_B2_i, BE_B1_i} = 4'h0; + +generate + if (WR_DATA_WIDTH == 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A_WDATA[17:0]; +assign WDATA_A2_i = PORT_A_WDATA[35:18]; + +assign WDATA_B1_i = 18'h0; +assign WDATA_B2_i = 18'h0; + +generate + if (RD_DATA_WIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end +endgenerate + +assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A_WRWIDTH *) +(* port_b_dwidth = PORT_B_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module RAM_18K_BLK ( + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o +); + +parameter WR_ADDR_WIDTH = 10; +parameter RD_ADDR_WIDTH = 10; +parameter WR_DATA_WIDTH = 18; +parameter RD_DATA_WIDTH = 18; +parameter BE_WIDTH = 2; + +input wire WEN_i; +input wire REN_i; +input wire WR_CLK_i; +input wire RD_CLK_i; +input wire [BE_WIDTH-1:0] WR_BE_i; +input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i; +input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; +input wire [WR_DATA_WIDTH-1 :0] WDATA_i; +output wire [RD_DATA_WIDTH-1 :0] RDATA_o; + + (* is_inferred = 0 *) + (* is_split = 0 *) + (* is_fifo = 0 *) + BRAM2x18_SP #( + .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), + .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .BE1_WIDTH(BE_WIDTH), + .WR2_ADDR_WIDTH(), + .RD2_ADDR_WIDTH(), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .BE2_WIDTH() + ) U1 + ( + .RESET_ni(1'b1), + + .WEN1_i(WEN_i), + .REN1_i(REN_i), + .WR1_CLK_i(WR_CLK_i), + .RD1_CLK_i(RD_CLK_i), + .WR1_BE_i(WR_BE_i), + .WR1_ADDR_i(WR_ADDR_i), + .RD1_ADDR_i(RD_ADDR_i), + .WDATA1_i(WDATA_i), + .RDATA1_o(RDATA_o), + + .WEN2_i(1'b0), + .REN2_i(1'b0), + .WR2_CLK_i(1'b0), + .RD2_CLK_i(1'b0), + .WR2_BE_i(2'b00), + .WR2_ADDR_i(14'h0), + .RD2_ADDR_i(14'h0), + .WDATA2_i(18'h0), + .RDATA2_o() + ); + +endmodule + +module RAM_18K_X2_BLK ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); +localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); +localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); +localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 4'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 4'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 1 *) +(* is_fifo = 0 *) +(* port_a1_dwidth = PORT_A1_WRWIDTH *) +(* port_a2_dwidth = PORT_A2_WRWIDTH *) +(* port_b1_dwidth = PORT_B1_WRWIDTH *) +(* port_b2_dwidth = PORT_B2_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module DPRAM_36K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o +); + +parameter PORT_A_AWIDTH = 10; +parameter PORT_A_DWIDTH = 36; +parameter PORT_A_WR_BE_WIDTH = 4; + +parameter PORT_B_AWIDTH = 10; +parameter PORT_B_DWIDTH = 36; +parameter PORT_B_WR_BE_WIDTH = 4; + +input PORT_A_CLK_i; +input [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i; +input [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i; +input PORT_A_WEN_i; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i; +input PORT_A_REN_i; +output [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o; + +input PORT_B_CLK_i; +input [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i; +input [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i; +input PORT_B_WEN_i; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i; +input PORT_B_REN_i; +output [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +32, 36: rwmode = 36; +default: rwmode = 36; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [3:0] PORT_A_WR_BE; +wire [3:0] PORT_B_WR_BE; + +wire [35:0] PORT_B_WDATA; +wire [35:0] PORT_B_RDATA; +wire [35:0] PORT_A_WDATA; +wire [35:0] PORT_A_RDATA; + +wire [14:0] PORT_A_ADDR_INT; +wire [14:0] PORT_B_ADDR_INT; + +wire [14:0] PORT_A_ADDR; +wire [14:0] PORT_B_ADDR; + +wire PORT_A_CLK; +wire PORT_B_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B_DWIDTH); + +localparam PORT_A_WRWIDTH = rwmode(PORT_A_DWIDTH); +localparam PORT_B_WRWIDTH = rwmode(PORT_B_DWIDTH); + +assign PORT_A_CLK = PORT_A_CLK_i; +assign PORT_B_CLK = PORT_B_CLK_i; + +generate + if (PORT_A_AWIDTH == 15) begin + assign PORT_A_ADDR_INT = PORT_A_ADDR_i; + end else begin + assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; + assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; + end +endgenerate + +case (PORT_A_DWIDTH) + 1: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT; + end + 2: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 1; + end + 4: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 5; + end + default: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT; + end +endcase + +generate + if (PORT_B_AWIDTH == 15) begin + assign PORT_B_ADDR_INT = PORT_B_ADDR_i; + end else begin + assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; + assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; + end +endgenerate + +case (PORT_B_DWIDTH) + 1: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT; + end + 2: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 1; + end + 4: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 5; + end + default: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT; + end +endcase + +case (PORT_A_WR_BE_WIDTH) + 4: begin + assign PORT_A_WR_BE = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A_WR_BE[3:PORT_A_WR_BE_WIDTH] = 0; + assign PORT_A_WR_BE[PORT_A_WR_BE_WIDTH-1 :0] = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B_WR_BE_WIDTH) + 4: begin + assign PORT_B_WR_BE = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B_WR_BE[3:PORT_B_WR_BE_WIDTH] = 0; + assign PORT_B_WR_BE[PORT_B_WR_BE_WIDTH-1 :0] = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A_REN_i; +assign WEN_A1_i = PORT_A_WEN_i; +assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE; + +assign REN_B1_i = PORT_B_REN_i; +assign WEN_B1_i = PORT_B_WEN_i; +assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; + +generate + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A_WDATA[17:0]; +assign WDATA_A2_i = PORT_A_WDATA[35:18]; + +generate + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; + end +endgenerate + +assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0]; + +generate + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; + assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; + end else begin + assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B_WDATA[17:0]; +assign WDATA_B2_i = PORT_B_WDATA[35:18]; + +generate + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end +endgenerate + +assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A_WRWIDTH *) +(* port_b_dwidth = PORT_B_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module DPRAM_18K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o +); + +parameter PORT_A_AWIDTH = 10; +parameter PORT_A_DWIDTH = 36; +parameter PORT_A_WR_BE_WIDTH = 4; + +parameter PORT_B_AWIDTH = 10; +parameter PORT_B_DWIDTH = 36; +parameter PORT_B_WR_BE_WIDTH = 4; + +input PORT_A_CLK_i; +input [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i; +input [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i; +input PORT_A_WEN_i; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i; +input PORT_A_REN_i; +output [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o; + +input PORT_B_CLK_i; +input [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i; +input [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i; +input PORT_B_WEN_i; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i; +input PORT_B_REN_i; +output [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o; + + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +BRAM2x18_dP #( + .PORT_A1_AWIDTH(PORT_A_AWIDTH), + .PORT_A1_DWIDTH(PORT_A_DWIDTH), + .PORT_A1_WR_BE_WIDTH(PORT_A_WR_BE_WIDTH), + .PORT_B1_AWIDTH(PORT_B_AWIDTH), + .PORT_B1_DWIDTH(PORT_B_DWIDTH), + .PORT_B1_WR_BE_WIDTH(PORT_B_WR_BE_WIDTH), + .PORT_A2_AWIDTH(), + .PORT_A2_DWIDTH(), + .PORT_A2_WR_BE_WIDTH(), + .PORT_B2_AWIDTH(), + .PORT_B2_DWIDTH(), + .PORT_B2_WR_BE_WIDTH() +) U1 ( + .PORT_A1_CLK_i(PORT_A_CLK_i), + .PORT_A1_WEN_i(PORT_A_WEN_i), + .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), + .PORT_A1_REN_i(PORT_A_REN_i), + .PORT_A1_ADDR_i(PORT_A_ADDR_i), + .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), + .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), + + .PORT_B1_CLK_i(PORT_B_CLK_i), + .PORT_B1_WEN_i(PORT_B_WEN_i), + .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), + .PORT_B1_REN_i(PORT_B_REN_i), + .PORT_B1_ADDR_i(PORT_B_ADDR_i), + .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), + .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), + + .PORT_A2_CLK_i(1'b0), + .PORT_A2_WEN_i(1'b0), + .PORT_A2_WR_BE_i(2'b00), + .PORT_A2_REN_i(1'b0), + .PORT_A2_ADDR_i(14'h0), + .PORT_A2_WR_DATA_i(18'h0), + .PORT_A2_RD_DATA_o(), + + .PORT_B2_CLK_i(1'b0), + .PORT_B2_WEN_i(1'b0), + .PORT_B2_WR_BE_i(2'b00), + .PORT_B2_REN_i(1'b0), + .PORT_B2_ADDR_i(14'h0), + .PORT_B2_WR_DATA_i(18'h0), + .PORT_B2_RD_DATA_o() +); + +endmodule + + +module DPRAM_18K_X2_BLK ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + + +input PORT_A1_CLK_i; +input [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input PORT_A1_WEN_i; +input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input PORT_A1_REN_i; +output [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input PORT_B1_CLK_i; +input [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input PORT_B1_WEN_i; +input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input PORT_B1_REN_i; +output [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input PORT_A2_CLK_i; +input [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input PORT_A2_WEN_i; +input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input PORT_A2_REN_i; +output [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input PORT_B2_CLK_i; +input [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input PORT_B2_WEN_i; +input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input PORT_B2_REN_i; +output [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(PORT_A1_DWIDTH); +localparam PORT_B1_WRWIDTH = rwmode(PORT_B1_DWIDTH); +localparam PORT_A2_WRWIDTH = rwmode(PORT_A2_DWIDTH); +localparam PORT_B2_WRWIDTH = rwmode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 1 *) +(* is_fifo = 0 *) +(* port_a1_dwidth = PORT_A1_WRWIDTH *) +(* port_a2_dwidth = PORT_A2_WRWIDTH *) +(* port_b1_dwidth = PORT_B1_WRWIDTH *) +(* port_b2_dwidth = PORT_B2_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module SFIFO_36K_BLK ( + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + 32, 36: rwmode = 36; + default: rwmode = 36; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + + wire Push_Clk, Pop_Clk; + + assign Push_Clk = CLK; + assign Pop_Clk = CLK; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); + localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = PORT_A_WRWIDTH *) + (* port_b_dwidth = PORT_B_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg[17:0]), + .WDATA_A2_i(in_reg[35:18]), + .RDATA_A1_o(fifo_flags), + .RDATA_A2_o(), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk), + .CLK_A2_i(1'b0), + .REN_A1_i(1'b1), + .REN_A2_i(1'b0), + .WEN_A1_i(PUSH), + .WEN_A2_i(1'b0), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg[17:0]), + .RDATA_B2_o(out_reg[35:18]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk), + .CLK_B2_i(1'b0), + .REN_B1_i(POP), + .REN_B2_i(1'b0), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush), + .FLUSH2_i(1'b0) + ); + + + +endmodule + +module AFIFO_36K_BLK ( + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + 32, 36: rwmode = 36; + default: rwmode = 36; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); + localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = PORT_A_WRWIDTH *) + (* port_b_dwidth = PORT_B_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg[17:0]), + .WDATA_A2_i(in_reg[35:18]), + .RDATA_A1_o(fifo_flags), + .RDATA_A2_o(), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk), + .CLK_A2_i(1'b0), + .REN_A1_i(1'b1), + .REN_A2_i(1'b0), + .WEN_A1_i(PUSH), + .WEN_A2_i(1'b0), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg[17:0]), + .RDATA_B2_o(out_reg[35:18]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk), + .CLK_B2_i(1'b0), + .REN_B1_i(POP), + .REN_B2_i(1'b0), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush), + .FLUSH2_i(1'b0) + ); + + + +endmodule + +module SFIFO_18K_BLK ( + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + BRAM2x18_SFIFO #( + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .CLK1(CLK), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .CLK2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() + ); + +endmodule + +module SFIFO_18K_X2_BLK ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = PORT_A1_WRWIDTH *) + (* port_a2_dwidth = PORT_A2_WRWIDTH *) + (* port_b1_dwidth = PORT_B1_WRWIDTH *) + (* port_b2_dwidth = PORT_B2_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module AFIFO_18K_BLK ( + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + BRAM2x18_AFIFO #( + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .Push_Clk1(Push_Clk), + .Pop_Clk1(Pop_Clk), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .Push_Clk2(1'b0), + .Pop_Clk2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() + ); + +endmodule + +module AFIFO_18K_X2_BLK ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = PORT_A1_WRWIDTH *) + (* port_a2_dwidth = PORT_A2_WRWIDTH *) + (* port_b1_dwidth = PORT_B1_WRWIDTH *) + (* port_b2_dwidth = PORT_B2_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_sim.v b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v new file mode 100644 index 00000000000..2c2b814abb1 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v @@ -0,0 +1,11081 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +`timescale 1ns /10ps + +`default_nettype none + +module TDP36K ( + RESET_ni, + WEN_A1_i, + WEN_B1_i, + REN_A1_i, + REN_B1_i, + CLK_A1_i, + CLK_B1_i, + BE_A1_i, + BE_B1_i, + ADDR_A1_i, + ADDR_B1_i, + WDATA_A1_i, + WDATA_B1_i, + RDATA_A1_o, + RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, + WEN_B2_i, + REN_A2_i, + REN_B2_i, + CLK_A2_i, + CLK_B2_i, + BE_A2_i, + BE_B2_i, + ADDR_A2_i, + ADDR_B2_i, + WDATA_A2_i, + WDATA_B2_i, + RDATA_A2_o, + RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + // First 18K RAMFIFO (41 bits) + localparam [ 0:0] SYNC_FIFO1_i = MODE_BITS[0]; + localparam [ 2:0] RMODE_A1_i = MODE_BITS[3 : 1]; + localparam [ 2:0] RMODE_B1_i = MODE_BITS[6 : 4]; + localparam [ 2:0] WMODE_A1_i = MODE_BITS[9 : 7]; + localparam [ 2:0] WMODE_B1_i = MODE_BITS[12:10]; + localparam [ 0:0] FMODE1_i = MODE_BITS[13]; + localparam [ 0:0] POWERDN1_i = MODE_BITS[14]; + localparam [ 0:0] SLEEP1_i = MODE_BITS[15]; + localparam [ 0:0] PROTECT1_i = MODE_BITS[16]; + localparam [11:0] UPAE1_i = MODE_BITS[28:17]; + localparam [11:0] UPAF1_i = MODE_BITS[40:29]; + + // Second 18K RAMFIFO (39 bits) + localparam [ 0:0] SYNC_FIFO2_i = MODE_BITS[41]; + localparam [ 2:0] RMODE_A2_i = MODE_BITS[44:42]; + localparam [ 2:0] RMODE_B2_i = MODE_BITS[47:45]; + localparam [ 2:0] WMODE_A2_i = MODE_BITS[50:48]; + localparam [ 2:0] WMODE_B2_i = MODE_BITS[53:51]; + localparam [ 0:0] FMODE2_i = MODE_BITS[54]; + localparam [ 0:0] POWERDN2_i = MODE_BITS[55]; + localparam [ 0:0] SLEEP2_i = MODE_BITS[56]; + localparam [ 0:0] PROTECT2_i = MODE_BITS[57]; + localparam [10:0] UPAE2_i = MODE_BITS[68:58]; + localparam [10:0] UPAF2_i = MODE_BITS[79:69]; + + // Split (1 bit) + localparam [ 0:0] SPLIT_i = MODE_BITS[80]; + + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + input wire RESET_ni; + input wire WEN_A1_i; + input wire WEN_B1_i; + input wire REN_A1_i; + input wire REN_B1_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + input wire [1:0] BE_A1_i; + input wire [1:0] BE_B1_i; + input wire [14:0] ADDR_A1_i; + input wire [14:0] ADDR_B1_i; + input wire [17:0] WDATA_A1_i; + input wire [17:0] WDATA_B1_i; + output reg [17:0] RDATA_A1_o; + output reg [17:0] RDATA_B1_o; + input wire FLUSH1_i; + input wire WEN_A2_i; + input wire WEN_B2_i; + input wire REN_A2_i; + input wire REN_B2_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + input wire [1:0] BE_A2_i; + input wire [1:0] BE_B2_i; + input wire [13:0] ADDR_A2_i; + input wire [13:0] ADDR_B2_i; + input wire [17:0] WDATA_A2_i; + input wire [17:0] WDATA_B2_i; + output reg [17:0] RDATA_A2_o; + output reg [17:0] RDATA_B2_o; + input wire FLUSH2_i; + wire EMPTY2; + wire EPO2; + wire EWM2; + wire FULL2; + wire FMO2; + wire FWM2; + wire EMPTY1; + wire EPO1; + wire EWM1; + wire FULL1; + wire FMO1; + wire FWM1; + wire UNDERRUN1; + wire OVERRUN1; + wire UNDERRUN2; + wire OVERRUN2; + wire UNDERRUN3; + wire OVERRUN3; + wire EMPTY3; + wire EPO3; + wire EWM3; + wire FULL3; + wire FMO3; + wire FWM3; + wire ram_fmode1; + wire ram_fmode2; + wire [17:0] ram_rdata_a1; + wire [17:0] ram_rdata_b1; + wire [17:0] ram_rdata_a2; + wire [17:0] ram_rdata_b2; + reg [17:0] ram_wdata_a1; + reg [17:0] ram_wdata_b1; + reg [17:0] ram_wdata_a2; + reg [17:0] ram_wdata_b2; + reg [14:0] laddr_a1; + reg [14:0] laddr_b1; + wire [13:0] ram_addr_a1; + wire [13:0] ram_addr_b1; + wire [13:0] ram_addr_a2; + wire [13:0] ram_addr_b2; + wire smux_clk_a1; + wire smux_clk_b1; + wire smux_clk_a2; + wire smux_clk_b2; + reg [1:0] ram_be_a1; + reg [1:0] ram_be_a2; + reg [1:0] ram_be_b1; + reg [1:0] ram_be_b2; + wire [2:0] ram_rmode_a1; + wire [2:0] ram_wmode_a1; + wire [2:0] ram_rmode_b1; + wire [2:0] ram_wmode_b1; + wire [2:0] ram_rmode_a2; + wire [2:0] ram_wmode_a2; + wire [2:0] ram_rmode_b2; + wire [2:0] ram_wmode_b2; + wire ram_ren_a1; + wire ram_ren_b1; + wire ram_ren_a2; + wire ram_ren_b2; + wire ram_wen_a1; + wire ram_wen_b1; + wire ram_wen_a2; + wire ram_wen_b2; + wire ren_o; + wire [11:0] ff_raddr; + wire [11:0] ff_waddr; + reg [35:0] fifo_rdata; + wire [1:0] fifo_rmode; + wire [1:0] fifo_wmode; + wire [1:0] bwl; + wire [17:0] pl_dout0; + wire [17:0] pl_dout1; + wire sclk_a1; + wire sclk_b1; + wire sclk_a2; + wire sclk_b2; + wire sreset; + wire flush1; + wire flush2; + assign sreset = RESET_ni; + assign flush1 = ~FLUSH1_i; + assign flush2 = ~FLUSH2_i; + assign ram_fmode1 = FMODE1_i & SPLIT_i; + assign ram_fmode2 = FMODE2_i & SPLIT_i; + assign smux_clk_a1 = CLK_A1_i; + assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i); + assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i); + assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); + assign sclk_a1 = smux_clk_a1; + assign sclk_a2 = smux_clk_a2; + assign sclk_b1 = smux_clk_b1; + assign sclk_b2 = smux_clk_b2; + assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i)); + assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i)); + localparam MODE_36 = 3'b011; + assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4]))); + assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4]))); + assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4])); + assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4])); + assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3])); + localparam MODE_18 = 3'b010; + localparam MODE_9 = 3'b001; + always @(*) begin : WDATA_SEL + case (SPLIT_i) + 1: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_wdata_b1 = WDATA_B1_i; + ram_wdata_b2 = WDATA_B2_i; + ram_be_a2 = BE_A2_i; + ram_be_b2 = BE_B2_i; + ram_be_a1 = BE_A1_i; + ram_be_b1 = BE_B1_i; + end + 0: begin + case (WMODE_A1_i) + MODE_36: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + MODE_18: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i); + ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i); + end + MODE_9: begin + ram_wdata_a1[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a1[16] = WDATA_A1_i[16]; + ram_wdata_a1[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a1[17] = WDATA_A1_i[16]; + ram_wdata_a2[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a2[16] = WDATA_A1_i[16]; + ram_wdata_a2[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a2[17] = WDATA_A1_i[16]; + case (bwl) + 0: {ram_be_a2, ram_be_a1} = 4'b0001; + 1: {ram_be_a2, ram_be_a1} = 4'b0010; + 2: {ram_be_a2, ram_be_a1} = 4'b0100; + 3: {ram_be_a2, ram_be_a1} = 4'b1000; + endcase + end + default: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + endcase + case (WMODE_B1_i) + MODE_36: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i); + ram_be_b2 = BE_B2_i; + ram_be_b1 = BE_B1_i; + end + MODE_18: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b1 = BE_B1_i; + ram_be_b2 = BE_B1_i; + end + MODE_9: begin + ram_wdata_b1[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b1[16] = WDATA_B1_i[16]; + ram_wdata_b1[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b1[17] = WDATA_B1_i[16]; + ram_wdata_b2[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b2[16] = WDATA_B1_i[16]; + ram_wdata_b2[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b2[17] = WDATA_B1_i[16]; + case (ADDR_B1_i[4:3]) + 0: {ram_be_b2, ram_be_b1} = 4'b0001; + 1: {ram_be_b2, ram_be_b1} = 4'b0010; + 2: {ram_be_b2, ram_be_b1} = 4'b0100; + 3: {ram_be_b2, ram_be_b1} = 4'b1000; + endcase + end + default: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b2 = BE_B1_i; + ram_be_b1 = BE_B1_i; + end + endcase + end + endcase + end + assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + always @(*) begin : FIFO_READ_SEL + case (RMODE_B1_i) + MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; + MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1}); + MODE_9: + case (ff_raddr[1:0]) + 0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}; + 1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]}; + 2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]}; + 3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]}; + endcase + default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1}; + endcase + end + localparam MODE_1 = 3'b101; + localparam MODE_2 = 3'b110; + localparam MODE_4 = 3'b100; + always @(*) begin : RDATA_SEL + case (SPLIT_i) + 1: begin + RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1); + RDATA_B1_o = ram_rdata_b1; + RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2); + RDATA_B2_o = ram_rdata_b2; + end + 0: begin + if (FMODE1_i) begin + RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3}; + RDATA_A2_o = 18'b000000000000000000; + end + else + case (RMODE_A1_i) + MODE_36: begin + RDATA_A1_o = {ram_rdata_a1[17:0]}; + RDATA_A2_o = {ram_rdata_a2[17:0]}; + end + MODE_18: begin + RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}}); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:4] = 14'b00000000000000; + RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]); + end + MODE_2: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:2] = 16'b0000000000000000; + RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]); + end + MODE_1: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:1] = 17'b00000000000000000; + RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]); + end + default: begin + RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]}; + RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]}; + end + endcase + case (RMODE_B1_i) + MODE_36: begin + RDATA_B1_o = {ram_rdata_b1}; + RDATA_B2_o = {ram_rdata_b2}; + end + MODE_18: begin + RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1)); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]})); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:4] = 14'b00000000000000; + RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]); + end + MODE_2: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:2] = 16'b0000000000000000; + RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]); + end + MODE_1: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:1] = 17'b00000000000000000; + RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]); + end + default: begin + RDATA_B1_o = ram_rdata_b1; + RDATA_B2_o = ram_rdata_b2; + end + endcase + end + endcase + end + always @(posedge sclk_a1 or negedge sreset) + if (sreset == 0) + laddr_a1 <= 1'sb0; + else + laddr_a1 <= ADDR_A1_i; + always @(posedge sclk_b1 or negedge sreset) + if (sreset == 0) + laddr_b1 <= 1'sb0; + else + laddr_b1 <= ADDR_B1_i; + assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00))); + assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00))); + fifo_ctl #( + .ADDR_WIDTH(12), + .FIFO_WIDTH(3'd4), + .DEPTH(7) + ) fifo36_ctl( + .rclk(sclk_b1), + .rst_R_n(flush1), + .wclk(sclk_a1), + .rst_W_n(flush1), + .ren(REN_B1_i), + .wen(ram_wen_a1), + .sync(SYNC_FIFO1_i), + .rmode(fifo_rmode), + .wmode(fifo_wmode), + .ren_o(ren_o), + .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}), + .raddr(ff_raddr), + .waddr(ff_waddr), + .upaf(UPAF1_i), + .upae(UPAE1_i) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF1_i[10:0]), + .UPAE_i(UPAE1_i[10:0]), + .SYNC_FIFO_i(SYNC_FIFO1_i), + .POWERDN_i(POWERDN1_i), + .SLEEP_i(SLEEP1_i), + .PROTECT_i(PROTECT1_i) + )u1( + .RMODE_A_i(ram_rmode_a1), + .RMODE_B_i(ram_rmode_b1), + .WMODE_A_i(ram_wmode_a1), + .WMODE_B_i(ram_wmode_b1), + .WEN_A_i(ram_wen_a1), + .WEN_B_i(ram_wen_b1), + .REN_A_i(ram_ren_a1), + .REN_B_i(ram_ren_b1), + .CLK_A_i(sclk_a1), + .CLK_B_i(sclk_b1), + .BE_A_i(ram_be_a1), + .BE_B_i(ram_be_b1), + .ADDR_A_i(ram_addr_a1), + .ADDR_B_i(ram_addr_b1), + .WDATA_A_i(ram_wdata_a1), + .WDATA_B_i(ram_wdata_b1), + .RDATA_A_o(ram_rdata_a1), + .RDATA_B_o(ram_rdata_b1), + .EMPTY_o(EMPTY1), + .EPO_o(EPO1), + .EWM_o(EWM1), + .UNDERRUN_o(UNDERRUN1), + .FULL_o(FULL1), + .FMO_o(FMO1), + .FWM_o(FWM1), + .OVERRUN_o(OVERRUN1), + .FLUSH_ni(flush1), + .FMODE_i(ram_fmode1) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF2_i), + .UPAE_i(UPAE2_i), + .SYNC_FIFO_i(SYNC_FIFO2_i), + .POWERDN_i(POWERDN2_i), + .SLEEP_i(SLEEP2_i), + .PROTECT_i(PROTECT2_i) + )u2( + .RMODE_A_i(ram_rmode_a2), + .RMODE_B_i(ram_rmode_b2), + .WMODE_A_i(ram_wmode_a2), + .WMODE_B_i(ram_wmode_b2), + .WEN_A_i(ram_wen_a2), + .WEN_B_i(ram_wen_b2), + .REN_A_i(ram_ren_a2), + .REN_B_i(ram_ren_b2), + .CLK_A_i(sclk_a2), + .CLK_B_i(sclk_b2), + .BE_A_i(ram_be_a2), + .BE_B_i(ram_be_b2), + .ADDR_A_i(ram_addr_a2), + .ADDR_B_i(ram_addr_b2), + .WDATA_A_i(ram_wdata_a2), + .WDATA_B_i(ram_wdata_b2), + .RDATA_A_o(ram_rdata_a2), + .RDATA_B_o(ram_rdata_b2), + .EMPTY_o(EMPTY2), + .EPO_o(EPO2), + .EWM_o(EWM2), + .UNDERRUN_o(UNDERRUN2), + .FULL_o(FULL2), + .FMO_o(FMO2), + .FWM_o(FWM2), + .OVERRUN_o(OVERRUN2), + .FLUSH_ni(flush2), + .FMODE_i(ram_fmode2) + ); +endmodule + +module RAM_18K_X2_BLK ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 4'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 4'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 1 *) +(* port_a1_dwidth = WR1_DATA_WIDTH *) +(* port_a2_dwidth = WR2_DATA_WIDTH *) +(* port_b1_dwidth = RD1_DATA_WIDTH *) +(* port_b2_dwidth = RD2_DATA_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_SP ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 4'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 4'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* port_a_dwidth = WR1_DATA_WIDTH *) +(* port_b_dwidth = RD1_DATA_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module RAM_18K_BLK ( + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o +); + +parameter WR_ADDR_WIDTH = 10; +parameter RD_ADDR_WIDTH = 10; +parameter WR_DATA_WIDTH = 18; +parameter RD_DATA_WIDTH = 18; +parameter BE_WIDTH = 2; + +input wire WEN_i; +input wire REN_i; +input wire WR_CLK_i; +input wire RD_CLK_i; +input wire [BE_WIDTH-1:0] WR_BE_i; +input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i; +input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; +input wire [WR_DATA_WIDTH-1 :0] WDATA_i; +output wire [RD_DATA_WIDTH-1 :0] RDATA_o; + + (* is_inferred = 0 *) + (* is_split = 0 *) + BRAM2x18_SP #( + .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), + .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .BE1_WIDTH(BE_WIDTH), + .WR2_ADDR_WIDTH(), + .RD2_ADDR_WIDTH(), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .BE2_WIDTH() + ) U1 + ( + .RESET_ni(1'b1), + + .WEN1_i(WEN_i), + .REN1_i(REN_i), + .WR1_CLK_i(WR_CLK_i), + .RD1_CLK_i(RD_CLK_i), + .WR1_BE_i(WR_BE_i), + .WR1_ADDR_i(WR_ADDR_i), + .RD1_ADDR_i(RD_ADDR_i), + .WDATA1_i(WDATA_i), + .RDATA1_o(RDATA_o), + + .WEN2_i(1'b0), + .REN2_i(1'b0), + .WR2_CLK_i(1'b0), + .RD2_CLK_i(1'b0), + .WR2_BE_i(2'b00), + .WR2_ADDR_i(14'h0), + .RD2_ADDR_i(14'h0), + .WDATA2_i(18'h0), + .RDATA2_o() + ); + +endmodule + +module RAM_36K_BLK ( + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o +); + +parameter WR_ADDR_WIDTH = 10; +parameter RD_ADDR_WIDTH = 10; +parameter WR_DATA_WIDTH = 36; +parameter RD_DATA_WIDTH = 36; +parameter BE_WIDTH = 4; + +parameter INIT = 0; + +input wire WEN_i; +input wire REN_i; +input wire WR_CLK_i; +input wire RD_CLK_i; +input wire [BE_WIDTH-1:0] WR_BE_i; +input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i; +input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; +input wire [WR_DATA_WIDTH-1 :0] WDATA_i; +output wire [RD_DATA_WIDTH-1 :0] RDATA_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [3:0] WR_BE; + +wire [35:0] PORT_B_RDATA; +wire [35:0] PORT_A_WDATA; + +wire [14:0] WR_ADDR_INT; +wire [14:0] RD_ADDR_INT; + +wire [14:0] PORT_A_ADDR; +wire [14:0] PORT_B_ADDR; + +wire PORT_A_CLK; +wire PORT_B_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + +assign PORT_A_CLK = WR_CLK_i; +assign PORT_B_CLK = RD_CLK_i; + +generate + if (WR_ADDR_WIDTH == 15) begin + assign WR_ADDR_INT = WR_ADDR_i; + end else begin + assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; + assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; + end +endgenerate + +case (WR_DATA_WIDTH) + 1: begin + assign PORT_A_ADDR = WR_ADDR_INT; + end + 2: begin + assign PORT_A_ADDR = WR_ADDR_INT << 1; + end + 4: begin + assign PORT_A_ADDR = WR_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A_ADDR = WR_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A_ADDR = WR_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_A_ADDR = WR_ADDR_INT << 5; + end + default: begin + assign PORT_A_ADDR = WR_ADDR_INT; + end +endcase + +generate + if (RD_ADDR_WIDTH == 15) begin + assign RD_ADDR_INT = RD_ADDR_i; + end else begin + assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; + assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; + end +endgenerate + +case (RD_DATA_WIDTH) + 1: begin + assign PORT_B_ADDR = RD_ADDR_INT; + end + 2: begin + assign PORT_B_ADDR = RD_ADDR_INT << 1; + end + 4: begin + assign PORT_B_ADDR = RD_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B_ADDR = RD_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B_ADDR = RD_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_B_ADDR = RD_ADDR_INT << 5; + end + default: begin + assign PORT_B_ADDR = RD_ADDR_INT; + end +endcase + +case (BE_WIDTH) + 4: begin + assign WR_BE = WR_BE_i[BE_WIDTH-1 :0]; + end + default: begin + assign WR_BE[3:BE_WIDTH] = 0; + assign WR_BE[BE_WIDTH-1 :0] = WR_BE_i[BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN_i; +assign {BE_A2_i, BE_A1_i} = WR_BE; + +assign REN_B1_i = REN_i; +assign WEN_B1_i = 1'b0; +assign {BE_B2_i, BE_B1_i} = 4'h0; + +generate + if (WR_DATA_WIDTH == 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A_WDATA[17:0]; +assign WDATA_A2_i = PORT_A_WDATA[35:18]; + +assign WDATA_B1_i = 18'h0; +assign WDATA_B2_i = 18'h0; + +generate + if (RD_DATA_WIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end +endgenerate + +assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 1 *) +(* is_split = 0 *) +(* port_a_width = WR_DATA_WIDTH *) +(* port_b_width = RD_DATA_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + + +module DPRAM_18K_X2_BLK ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + + +input wire PORT_A1_CLK_i; +input wire [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input wire [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input wire PORT_A1_WEN_i; +input wire [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input wire PORT_A1_REN_i; +output wire [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input wire PORT_B1_CLK_i; +input wire [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input wire [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input wire PORT_B1_WEN_i; +input wire [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input wire PORT_B1_REN_i; +output wire [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input wire PORT_A2_CLK_i; +input wire [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input wire [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input wire PORT_A2_WEN_i; +input wire [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input wire PORT_A2_REN_i; +output wire [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input wire PORT_B2_CLK_i; +input wire [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input wire [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input wire PORT_B2_WEN_i; +input wire [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input wire PORT_B2_REN_i; +output wire [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 1 *) +(* port_a1_dwidth = PORT_A1_DWIDTH *) +(* port_a2_dwidth = PORT_A2_DWIDTH *) +(* port_b1_dwidth = PORT_B1_DWIDTH *) +(* port_b2_dwidth = PORT_B2_DWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + +input wire PORT_A1_CLK_i; +input wire [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input wire [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input wire PORT_A1_WEN_i; +input wire [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input wire PORT_A1_REN_i; +output wire [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input wire PORT_B1_CLK_i; +input wire [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input wire [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input wire PORT_B1_WEN_i; +input wire [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input wire PORT_B1_REN_i; +output wire [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input wire PORT_A2_CLK_i; +input wire [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input wire [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input wire PORT_A2_WEN_i; +input wire [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input wire PORT_A2_REN_i; +output wire [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input wire PORT_B2_CLK_i; +input wire [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input wire [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input wire PORT_B2_WEN_i; +input wire [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input wire PORT_B2_REN_i; +output wire [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* port_a_dwidth = PORT_A1_DWIDTH *) +(* port_b_dwidth = PORT_B1_DWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module DPRAM_18K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o +); + +parameter PORT_A_AWIDTH = 10; +parameter PORT_A_DWIDTH = 36; +parameter PORT_A_WR_BE_WIDTH = 4; + +parameter PORT_B_AWIDTH = 10; +parameter PORT_B_DWIDTH = 36; +parameter PORT_B_WR_BE_WIDTH = 4; + +input wire PORT_A_CLK_i; +input wire [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i; +input wire [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i; +input wire PORT_A_WEN_i; +input wire [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i; +input wire PORT_A_REN_i; +output wire [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o; + +input wire PORT_B_CLK_i; +input wire [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i; +input wire [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i; +input wire PORT_B_WEN_i; +input wire [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i; +input wire PORT_B_REN_i; +output wire [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o; + + +(* is_inferred = 0 *) +(* is_split = 0 *) +BRAM2x18_dP #( + .PORT_A1_AWIDTH(PORT_A_AWIDTH), + .PORT_A1_DWIDTH(PORT_A_DWIDTH), + .PORT_A1_WR_BE_WIDTH(PORT_A_WR_BE_WIDTH), + .PORT_B1_AWIDTH(PORT_B_AWIDTH), + .PORT_B1_DWIDTH(PORT_B_DWIDTH), + .PORT_B1_WR_BE_WIDTH(PORT_B_WR_BE_WIDTH), + .PORT_A2_AWIDTH(), + .PORT_A2_DWIDTH(), + .PORT_A2_WR_BE_WIDTH(), + .PORT_B2_AWIDTH(), + .PORT_B2_DWIDTH(), + .PORT_B2_WR_BE_WIDTH() +) U1 ( + .PORT_A1_CLK_i(PORT_A_CLK_i), + .PORT_A1_WEN_i(PORT_A_WEN_i), + .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), + .PORT_A1_REN_i(PORT_A_REN_i), + .PORT_A1_ADDR_i(PORT_A_ADDR_i), + .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), + .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), + + .PORT_B1_CLK_i(PORT_B_CLK_i), + .PORT_B1_WEN_i(PORT_B_WEN_i), + .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), + .PORT_B1_REN_i(PORT_B_REN_i), + .PORT_B1_ADDR_i(PORT_B_ADDR_i), + .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), + .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), + + .PORT_A2_CLK_i(1'b0), + .PORT_A2_WEN_i(1'b0), + .PORT_A2_WR_BE_i(2'b00), + .PORT_A2_REN_i(1'b0), + .PORT_A2_ADDR_i(14'h0), + .PORT_A2_WR_DATA_i(18'h0), + .PORT_A2_RD_DATA_o(), + + .PORT_B2_CLK_i(1'b0), + .PORT_B2_WEN_i(1'b0), + .PORT_B2_WR_BE_i(2'b00), + .PORT_B2_REN_i(1'b0), + .PORT_B2_ADDR_i(14'h0), + .PORT_B2_WR_DATA_i(18'h0), + .PORT_B2_RD_DATA_o() +); + +endmodule + +module DPRAM_36K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o +); + +parameter PORT_A_AWIDTH = 10; +parameter PORT_A_DWIDTH = 36; +parameter PORT_A_WR_BE_WIDTH = 4; + +parameter PORT_B_AWIDTH = 10; +parameter PORT_B_DWIDTH = 36; +parameter PORT_B_WR_BE_WIDTH = 4; + +input wire PORT_A_CLK_i; +input wire [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i; +input wire [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i; +input wire PORT_A_WEN_i; +input wire [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i; +input wire PORT_A_REN_i; +output wire [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o; + +input wire PORT_B_CLK_i; +input wire [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i; +input wire [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i; +input wire PORT_B_WEN_i; +input wire [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i; +input wire PORT_B_REN_i; +output wire [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [3:0] PORT_A_WR_BE; +wire [3:0] PORT_B_WR_BE; + +wire [35:0] PORT_B_WDATA; +wire [35:0] PORT_B_RDATA; +wire [35:0] PORT_A_WDATA; +wire [35:0] PORT_A_RDATA; + +wire [14:0] PORT_A_ADDR_INT; +wire [14:0] PORT_B_ADDR_INT; + +wire [14:0] PORT_A_ADDR; +wire [14:0] PORT_B_ADDR; + +wire PORT_A_CLK; +wire PORT_B_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B_DWIDTH); + +assign PORT_A_CLK = PORT_A_CLK_i; +assign PORT_B_CLK = PORT_B_CLK_i; + +generate + if (PORT_A_AWIDTH == 15) begin + assign PORT_A_ADDR_INT = PORT_A_ADDR_i; + end else begin + assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; + assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; + end +endgenerate + +case (PORT_A_DWIDTH) + 1: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT; + end + 2: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 1; + end + 4: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 5; + end + default: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT; + end +endcase + +generate + if (PORT_B_AWIDTH == 15) begin + assign PORT_B_ADDR_INT = PORT_B_ADDR_i; + end else begin + assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; + assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; + end +endgenerate + +case (PORT_B_DWIDTH) + 1: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT; + end + 2: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 1; + end + 4: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 5; + end + default: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT; + end +endcase + +case (PORT_A_WR_BE_WIDTH) + 4: begin + assign PORT_A_WR_BE = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A_WR_BE[3:PORT_A_WR_BE_WIDTH] = 0; + assign PORT_A_WR_BE[PORT_A_WR_BE_WIDTH-1 :0] = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B_WR_BE_WIDTH) + 4: begin + assign PORT_B_WR_BE = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B_WR_BE[3:PORT_B_WR_BE_WIDTH] = 0; + assign PORT_B_WR_BE[PORT_B_WR_BE_WIDTH-1 :0] = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A_REN_i; +assign WEN_A1_i = PORT_A_WEN_i; +assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE; + +assign REN_B1_i = PORT_B_REN_i; +assign WEN_B1_i = PORT_B_WEN_i; +assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; + +generate + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A_WDATA[17:0]; +assign WDATA_A2_i = PORT_A_WDATA[35:18]; + +generate + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; + end +endgenerate + +assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0]; + +generate + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; + assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; + end else begin + assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B_WDATA[17:0]; +assign WDATA_B2_i = PORT_B_WDATA[35:18]; + +generate + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end +endgenerate + +assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 1 *) +(* is_split = 0 *) +(* port_a_width = PORT_A_DWIDTH *) +(* port_b_width = PORT_B_DWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_SFIFO ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire CLK1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire CLK2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = WR1_DATA_WIDTH *) + (* port_b_dwidth = RD1_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module SFIFO_18K_BLK ( + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + BRAM2x18_SFIFO #( + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .CLK1(CLK), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .CLK2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() + ); + +endmodule + +module SFIFO_18K_X2_BLK ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire CLK1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire CLK2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = WR1_DATA_WIDTH *) + (* port_a2_dwidth = WR2_DATA_WIDTH *) + (* port_b1_dwidth = RD1_DATA_WIDTH *) + (* port_b2_dwidth = RD2_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + + +module BRAM2x18_AFIFO ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire Push_Clk1, Pop_Clk1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire Push_Clk2, Pop_Clk2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = WR1_DATA_WIDTH *) + (* port_b_dwidth = RD1_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module AFIFO_18K_BLK ( + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + BRAM2x18_AFIFO #( + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .Push_Clk1(Push_Clk), + .Pop_Clk1(Pop_Clk), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .Push_Clk2(1'b0), + .Pop_Clk2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() + ); + +endmodule + +module AFIFO_18K_X2_BLK ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire Push_Clk1, Pop_Clk1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire Push_Clk2, Pop_Clk2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = WR1_DATA_WIDTH *) + (* port_a2_dwidth = WR2_DATA_WIDTH *) + (* port_b1_dwidth = RD1_DATA_WIDTH *) + (* port_b2_dwidth = RD2_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module SFIFO_36K_BLK ( + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + + wire Push_Clk, Pop_Clk; + + assign Push_Clk = CLK; + assign Pop_Clk = CLK; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = WR_DATA_WIDTH *) + (* port_b_dwidth = RD_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg[17:0]), + .WDATA_A2_i(in_reg[35:18]), + .RDATA_A1_o(fifo_flags), + .RDATA_A2_o(), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk), + .CLK_A2_i(1'b0), + .REN_A1_i(1'b1), + .REN_A2_i(1'b0), + .WEN_A1_i(PUSH), + .WEN_A2_i(1'b0), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg[17:0]), + .RDATA_B2_o(out_reg[35:18]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk), + .CLK_B2_i(1'b0), + .REN_B1_i(POP), + .REN_B2_i(1'b0), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush), + .FLUSH2_i(1'b0) + ); + +endmodule + + +module AFIFO_36K_BLK ( + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = WR_DATA_WIDTH *) + (* port_b_dwidth = RD_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg[17:0]), + .WDATA_A2_i(in_reg[35:18]), + .RDATA_A1_o(fifo_flags), + .RDATA_A2_o(), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk), + .CLK_A2_i(1'b0), + .REN_A1_i(1'b1), + .REN_A2_i(1'b0), + .WEN_A1_i(PUSH), + .WEN_A2_i(1'b0), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg[17:0]), + .RDATA_B2_o(out_reg[35:18]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk), + .CLK_B2_i(1'b0), + .REN_B1_i(POP), + .REN_B2_i(1'b0), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush), + .FLUSH2_i(1'b0) + ); + +endmodule + +//=============================================================================== +module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/cells_sim.v b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v new file mode 100644 index 00000000000..645a62f833a --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v @@ -0,0 +1,376 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`timescale 1ps/1ps + +`default_nettype none +(* abc9_lut=1 *) +module LUT1(output wire O, input wire I0); + parameter [1:0] INIT = 0; + assign O = I0 ? INIT[1] : INIT[0]; + specify + (I0 => O) = 74; + endspecify +endmodule + +(* abc9_lut=2 *) +module LUT2(output wire O, input wire I0, I1); + parameter [3:0] INIT = 0; + wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 116; + (I1 => O) = 74; + endspecify +endmodule + +(* abc9_lut=3 *) +module LUT3(output wire O, input wire I0, I1, I2); + parameter [7:0] INIT = 0; + wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 162; + (I1 => O) = 116; + (I2 => O) = 174; + endspecify +endmodule + +(* abc9_lut=3 *) +module LUT4(output wire O, input wire I0, I1, I2, I3); + parameter [15:0] INIT = 0; + wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 201; + (I1 => O) = 162; + (I2 => O) = 116; + (I3 => O) = 74; + endspecify +endmodule + +(* abc9_lut=3 *) +module LUT5(output wire O, input wire I0, I1, I2, I3, I4); + parameter [31:0] INIT = 0; + wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 228; + (I1 => O) = 189; + (I2 => O) = 143; + (I3 => O) = 100; + (I4 => O) = 55; + endspecify +endmodule + +(* abc9_lut=5 *) +module LUT6(output wire O, input wire I0, I1, I2, I3, I4, I5); + parameter [63:0] INIT = 0; + wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; + wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 251; + (I1 => O) = 212; + (I2 => O) = 166; + (I3 => O) = 123; + (I4 => O) = 77; + (I5 => O) = 43; + endspecify +endmodule + +(* abc9_flop, lib_whitebox *) +module sh_dff( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C +); + + initial Q <= 1'b0; + always @(posedge C) + Q <= D; + + specify + (posedge C => (Q +: D)) = 0; + $setuphold(posedge C, D, 0, 0); + endspecify + +endmodule + +(* abc9_box, lib_whitebox *) +(* blackbox *) +(* keep *) +module adder_carry( + output wire sumout, + (* abc9_carry *) + output wire cout, + input wire p, + input wire g, + (* abc9_carry *) + input wire cin +); + assign sumout = p ^ cin; + assign cout = p ? cin : g; + + specify + (p => sumout) = 35; + (g => sumout) = 35; + (cin => sumout) = 40; + (p => cout) = 67; + (g => cout) = 65; + (cin => cout) = 69; + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C +); + initial Q <= 1'b0; + + always @(posedge C) + Q <= D; + + specify + (posedge C=>(Q+:D)) = 285; + $setuphold(posedge C, D, 56, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module dffn( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C +); + initial Q <= 1'b0; + + always @(negedge C) + Q <= D; + + specify + (negedge C=>(Q+:D)) = 285; + $setuphold(negedge C, D, 56, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module dffsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q <= 1'b0; + + always @(posedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (posedge C => (Q +: D)) = 280; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(posedge C, D, 56, 0); + $setuphold(posedge C, E, 32, 0); + $setuphold(posedge C, R, 0, 0); + $setuphold(posedge C, S, 0, 0); + $recrem(posedge R, posedge C, 0, 0); + $recrem(posedge S, posedge C, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module dffnsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q <= 1'b0; + + always @(negedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (negedge C => (Q +: D)) = 280; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(negedge C, D, 56, 0); + $setuphold(negedge C, E, 32, 0); + $setuphold(negedge C, R, 0, 0); + $setuphold(negedge C, S, 0, 0); + $recrem(posedge R, negedge C, 0, 0); + $recrem(posedge S, negedge C, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module sdffsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q <= 1'b0; + + always @(posedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (posedge C => (Q +: D)) = 280; + $setuphold(posedge C, D, 56, 0); + $setuphold(posedge C, R, 32, 0); + $setuphold(posedge C, S, 0, 0); + $setuphold(posedge C, E, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module sdffnsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q <= 1'b0; + + always @(negedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (negedge C => (Q +: D)) = 280; + $setuphold(negedge C, D, 56, 0); + $setuphold(negedge C, R, 32, 0); + $setuphold(negedge C, S, 0, 0); + $setuphold(negedge C, E, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module latchsre ( + output reg Q, + input wire S, + input wire R, + input wire D, + input wire G, + input wire E +); + initial Q <= 1'b0; + + always @* + begin + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E && G) + Q <= D; + end + + specify + (posedge G => (Q +: D)) = 0; + $setuphold(posedge G, D, 0, 0); + $setuphold(posedge G, E, 0, 0); + $setuphold(posedge G, R, 0, 0); + $setuphold(posedge G, S, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module latchnsre ( + output reg Q, + input wire S, + input wire R, + input wire D, + input wire G, + input wire E +); + initial Q <= 1'b0; + + always @* + begin + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E && !G) + Q <= D; + end + + specify + (negedge G => (Q +: D)) = 0; + $setuphold(negedge G, D, 0, 0); + $setuphold(negedge G, E, 0, 0); + $setuphold(negedge G, R, 0, 0); + $setuphold(negedge G, S, 0, 0); + endspecify + +endmodule + diff --git a/techlibs/quicklogic/qlf_k6n10f/ffs_map.v b/techlibs/quicklogic/qlf_k6n10f/ffs_map.v new file mode 100644 index 00000000000..26fa6ed3604 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/ffs_map.v @@ -0,0 +1,133 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +// DFF, asynchronous set/reset, enable +module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q); + input C; + input S; + input R; + input E; + input D; + output Q; + dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); +endmodule + +module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q); + input C; + input S; + input R; + input E; + input D; + output Q; + dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); +endmodule + +// DFF, synchronous set or reset, enable +module \$_SDFFE_PN0P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; + output Q; + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); +endmodule + +module \$_SDFFE_PN1P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; + output Q; + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); +endmodule + +module \$_SDFFE_NN0P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; + output Q; + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); +endmodule + +module \$_SDFFE_NN1P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; + output Q; + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); +endmodule + +// Latch, no set/reset, no enable +module \$_DLATCH_P_ (input E, D, output Q); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); +endmodule + +module \$_DLATCH_N_ (input E, D, output Q); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); +endmodule + +// Latch with async set and reset and enable +module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); +endmodule + +module \$_DLATCHSR_NPP_ (input E, S, R, D, output Q); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); +endmodule + +module \$__SHREG_DFF_P_ (D, Q, C); + input D; + input C; + output Q; + + parameter DEPTH = 2; + + reg [DEPTH-2:0] q; + + genvar i; + generate for (i = 0; i < DEPTH; i = i + 1) begin: slice + + // First in chain + generate if (i == 0) begin + sh_dff #() shreg_beg ( + .Q(q[i]), + .D(D), + .C(C) + ); + end endgenerate + // Middle in chain + generate if (i > 0 && i != DEPTH-1) begin + sh_dff #() shreg_mid ( + .Q(q[i]), + .D(q[i-1]), + .C(C) + ); + end endgenerate + // Last in chain + generate if (i == DEPTH-1) begin + sh_dff #() shreg_end ( + .Q(Q), + .D(q[i-1]), + .C(C) + ); + end endgenerate + end: slice + endgenerate + +endmodule + diff --git a/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt b/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt new file mode 100644 index 00000000000..3317956f822 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt @@ -0,0 +1,22 @@ +ram block $__QLF_TDP36K { + init any; + byte 9; + option "SPLIT" 0 { + abits 15; + widths 1 2 4 9 18 36 per_port; + } + option "SPLIT" 1 { + abits 14; + widths 1 2 4 9 18 per_port; + } + cost 65; + port srsw "A" "B" { + width tied; + clock posedge; + # wen causes read even when ren is low + # map clken = wen || ren + clken; + wrbe_separate; + rdwr old; + } +} diff --git a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v new file mode 100644 index 00000000000..20638c4f9af --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v @@ -0,0 +1,457 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module \$__QLF_TDP36K (PORT_A_CLK, PORT_A_ADDR, PORT_A_WR_DATA, PORT_A_WR_EN, PORT_A_WR_BE, PORT_A_CLK_EN, PORT_A_RD_DATA, + PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA); + +parameter INIT = 0; + +parameter OPTION_SPLIT = 0; + +parameter PORT_A_WIDTH = 1; +parameter PORT_A_WR_BE_WIDTH = 1; + +parameter PORT_B_WIDTH = 1; +parameter PORT_B_WR_BE_WIDTH = 1; + +input PORT_A_CLK; +input [14:0] PORT_A_ADDR; +input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; +input PORT_A_WR_EN; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; +input PORT_A_CLK_EN; +output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; + +input PORT_B_CLK; +input [14:0] PORT_B_ADDR; +input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA; +input PORT_B_WR_EN; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE; +input PORT_B_CLK_EN; +output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B_WIDTH); + +assign REN_A1_i = PORT_A_CLK_EN; +assign WEN_A1_i = PORT_A_CLK_EN & PORT_A_WR_EN; +assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE; + +assign REN_B1_i = PORT_B_CLK_EN; +assign WEN_B1_i = PORT_B_CLK_EN & PORT_B_WR_EN; +assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; + +case (PORT_A_WIDTH) +9: assign { WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A_WR_DATA; +18: assign { WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A_WR_DATA; +36: assign { WDATA_A2_i[17], WDATA_A2_i[15:8], WDATA_A2_i[16], WDATA_A2_i[7:0], WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0]} = PORT_A_WR_DATA; +default: assign WDATA_A1_i = PORT_A_WR_DATA; // 1,2,4 +endcase + +case (PORT_B_WIDTH) +9: assign { WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B_WR_DATA; +18: assign { WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B_WR_DATA; +36: assign { WDATA_B2_i[17], WDATA_B2_i[15:8], WDATA_B2_i[16], WDATA_B2_i[7:0], WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0]} = PORT_B_WR_DATA; +default: assign WDATA_B1_i = PORT_B_WR_DATA; // 1,2,4 +endcase + +case (PORT_A_WIDTH) +9: assign PORT_A_RD_DATA = { RDATA_A1_o[16], RDATA_A1_o[7:0] }; +18: assign PORT_A_RD_DATA = { RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0] }; +36: assign PORT_A_RD_DATA = { RDATA_A2_o[17], RDATA_A2_o[15:8], RDATA_A2_o[16], RDATA_A2_o[7:0], RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0]}; +default: assign PORT_A_RD_DATA = RDATA_A1_o; // 1,2,4 +endcase + +case (PORT_B_WIDTH) +9: assign PORT_B_RD_DATA = { RDATA_B1_o[16], RDATA_B1_o[7:0] }; +18: assign PORT_B_RD_DATA = { RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0] }; +36: assign PORT_B_RD_DATA = { RDATA_B2_o[17], RDATA_B2_o[15:8], RDATA_B2_o[16], RDATA_B2_o[7:0], RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0]}; +default: assign PORT_B_RD_DATA = RDATA_B1_o; // 1,2,4 +endcase + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 1 *) +(* is_split = 0 *) +(* port_a_width = PORT_A_WIDTH *) +(* port_b_width = PORT_B_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + + +module \$__QLF_TDP36K_MERGED (...); + +parameter INIT1 = 0; + +parameter PORT_A1_WIDTH = 1; +parameter PORT_B1_WIDTH = 1; + +parameter PORT_A1_WR_BE_WIDTH = 1; +parameter PORT_B1_WR_BE_WIDTH = 1; + +input PORT_A1_CLK; +input [14:0] PORT_A1_ADDR; +input [PORT_A1_WIDTH-1:0] PORT_A1_WR_DATA; +input PORT_A1_WR_EN; +input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE; +input PORT_A1_CLK_EN; +output [PORT_A1_WIDTH-1:0] PORT_A1_RD_DATA; + +input PORT_B1_CLK; +input [14:0] PORT_B1_ADDR; +input [PORT_B1_WIDTH-1:0] PORT_B1_WR_DATA; +input PORT_B1_WR_EN; +input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE; +input PORT_B1_CLK_EN; +output [PORT_B1_WIDTH-1:0] PORT_B1_RD_DATA; + +parameter INIT2 = 0; + +parameter PORT_A2_WIDTH = 1; +parameter PORT_B2_WIDTH = 1; +parameter PORT_A2_WR_BE_WIDTH = 1; +parameter PORT_B2_WR_BE_WIDTH = 1; + +input PORT_A2_CLK; +input [14:0] PORT_A2_ADDR; +input [PORT_A2_WIDTH-1:0] PORT_A2_WR_DATA; +input PORT_A2_WR_EN; +input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE; +input PORT_A2_CLK_EN; +output [PORT_A2_WIDTH-1:0] PORT_A2_RD_DATA; + +input PORT_B2_CLK; +input [14:0] PORT_B2_ADDR; +input [PORT_B2_WIDTH-1:0] PORT_B2_WR_DATA; +input PORT_B2_WR_EN; +input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE; +input PORT_B2_CLK_EN; +output [PORT_B2_WIDTH-1:0] PORT_B2_RD_DATA; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_WIDTH); +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_WIDTH); + +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_WIDTH); + +assign REN_A1_i = PORT_A1_CLK_EN; +assign WEN_A1_i = PORT_A1_CLK_EN & PORT_A1_WR_EN; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_B1_i = PORT_B1_CLK_EN; +assign WEN_B1_i = PORT_B1_CLK_EN & PORT_B1_WR_EN; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_A2_i = PORT_A2_CLK_EN; +assign WEN_A2_i = PORT_A2_CLK_EN & PORT_A2_WR_EN; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B2_i = PORT_B2_CLK_EN; +assign WEN_B2_i = PORT_B2_CLK_EN & PORT_B2_WR_EN; +assign BE_B2_i = PORT_B2_WR_BE; + +assign ADDR_A1_i = PORT_A1_ADDR; +assign ADDR_B1_i = PORT_B1_ADDR; +assign ADDR_A2_i = PORT_A2_ADDR; +assign ADDR_B2_i = PORT_B2_ADDR; + +case (PORT_A1_WIDTH) +9: assign { WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A1_WR_DATA; +18: assign { WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A1_WR_DATA; +default: assign WDATA_A1_i = PORT_A1_WR_DATA; // 1,2,4,8,16 +endcase + +case (PORT_B1_WIDTH) +9: assign { WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B1_WR_DATA; +18: assign { WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B1_WR_DATA; +default: assign WDATA_B1_i = PORT_B1_WR_DATA; // 1,2,4,8,16 +endcase + +case (PORT_A1_WIDTH) +9: assign PORT_A1_RD_DATA = { RDATA_A1_o[16], RDATA_A1_o[7:0] }; +18: assign PORT_A1_RD_DATA = { RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0] }; +default: assign PORT_A1_RD_DATA = RDATA_A1_o; // 1,2,4,8,16 +endcase + +case (PORT_B1_WIDTH) +9: assign PORT_B1_RD_DATA = { RDATA_B1_o[16], RDATA_B1_o[7:0] }; +18: assign PORT_B1_RD_DATA = { RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0] }; +default: assign PORT_B1_RD_DATA = RDATA_B1_o; // 1,2,4,8,16 +endcase + +case (PORT_A2_WIDTH) +9: assign { WDATA_A2_i[16], WDATA_A2_i[7:0] } = PORT_A2_WR_DATA; +18: assign { WDATA_A2_i[17], WDATA_A2_i[15:8], WDATA_A2_i[16], WDATA_A2_i[7:0] } = PORT_A2_WR_DATA; +default: assign WDATA_A2_i = PORT_A2_WR_DATA; // 1,2,4,8,16 +endcase + +case (PORT_B2_WIDTH) +9: assign { WDATA_B2_i[16], WDATA_B2_i[7:0] } = PORT_B2_WR_DATA; +18: assign { WDATA_B2_i[17], WDATA_B2_i[15:8], WDATA_B2_i[16], WDATA_B2_i[7:0] } = PORT_B2_WR_DATA; +default: assign WDATA_B2_i = PORT_B2_WR_DATA; // 1,2,4,8,16 +endcase + +case (PORT_A2_WIDTH) +9: assign PORT_A2_RD_DATA = { RDATA_A2_o[16], RDATA_A2_o[7:0] }; +18: assign PORT_A2_RD_DATA = { RDATA_A2_o[17], RDATA_A2_o[15:8], RDATA_A2_o[16], RDATA_A2_o[7:0] }; +default: assign PORT_A2_RD_DATA = RDATA_A2_o; // 1,2,4,8,16 +endcase + +case (PORT_B2_WIDTH) +9: assign PORT_B2_RD_DATA = { RDATA_B2_o[16], RDATA_B2_o[7:0] }; +18: assign PORT_B2_RD_DATA = { RDATA_B2_o[17], RDATA_B2_o[15:8], RDATA_B2_o[16], RDATA_B2_o[7:0] }; +default: assign PORT_B2_RD_DATA = RDATA_B2_o; // 1,2,4,8,16 +endcase + +defparam _TECHMAP_REPLACE_.MODE_BITS = {1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + +(* is_inferred = 1 *) +(* is_split = 1 *) +(* port_a1_width = PORT_A1_WIDTH *) +(* port_a2_width = PORT_A2_WIDTH *) +(* port_b1_width = PORT_B1_WIDTH *) +(* port_b2_width = PORT_B2_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(WDATA_A1_i), + .WDATA_A2_i(WDATA_A2_i), + .RDATA_A1_o(RDATA_A1_o), + .RDATA_A2_o(RDATA_A2_o), + .ADDR_A1_i(ADDR_A1_i), + .ADDR_A2_i(ADDR_A2_i), + .CLK_A1_i(PORT_A1_CLK), + .CLK_A2_i(PORT_A2_CLK), + .REN_A1_i(REN_A1_i), + .REN_A2_i(REN_A2_i), + .WEN_A1_i(WEN_A1_i), + .WEN_A2_i(WEN_A2_i), + .BE_A1_i(BE_A1_i), + .BE_A2_i(BE_A2_i), + + .WDATA_B1_i(WDATA_B1_i), + .WDATA_B2_i(WDATA_B2_i), + .RDATA_B1_o(RDATA_B1_o), + .RDATA_B2_o(RDATA_B2_o), + .ADDR_B1_i(ADDR_B1_i), + .ADDR_B2_i(ADDR_B2_i), + .CLK_B1_i(PORT_B1_CLK), + .CLK_B2_i(PORT_B2_CLK), + .REN_B1_i(REN_B1_i), + .REN_B2_i(REN_B2_i), + .WEN_B1_i(WEN_B1_i), + .WEN_B2_i(WEN_B2_i), + .BE_B1_i(BE_B1_i), + .BE_B2_i(BE_B2_i), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule \ No newline at end of file diff --git a/techlibs/quicklogic/quicklogic_eqn.cc b/techlibs/quicklogic/quicklogic_eqn.cc new file mode 100644 index 00000000000..b82a1b2866e --- /dev/null +++ b/techlibs/quicklogic/quicklogic_eqn.cc @@ -0,0 +1,100 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct QuicklogicEqnPass : public Pass { + QuicklogicEqnPass() : Pass("quicklogic_eqn", "Quicklogic: Calculate equations for luts") {} + void help() override + { + log("\n"); + log(" quicklogic_eqn [selection]\n"); + log("\n"); + log("Calculate equations for luts since bitstream generator depends on it.\n"); + log("\n"); + } + + Const init2eqn(Const init, int inputs) + { + std::string init_bits = init.as_string(); + const char *names[] = {"I0", "I1", "I2", "I3", "I4"}; + + std::string eqn; + int width = (int)pow(2, inputs); + for (int i = 0; i < width; i++) { + if (init_bits[width - 1 - i] == '1') { + eqn += "("; + for (int j = 0; j < inputs; j++) { + if (i & (1 << j)) + eqn += names[j]; + else + eqn += std::string("~") + names[j]; + + if (j != (inputs - 1)) + eqn += "*"; + } + eqn += ")+"; + } + } + if (eqn.empty()) + return Const("0"); + eqn = eqn.substr(0, eqn.length() - 1); + return Const(eqn); + } + + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing Quicklogic_EQN pass (calculate equations for luts).\n"); + + extra_args(args, args.size(), design); + + int cnt = 0; + for (auto module : design->selected_modules()) { + for (auto cell : module->selected_cells()) { + if (cell->type == ID(LUT1)) { + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 1)); + cnt++; + } + if (cell->type == ID(LUT2)) { + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 2)); + cnt++; + } + if (cell->type == ID(LUT3)) { + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 3)); + cnt++; + } + if (cell->type == ID(LUT4)) { + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 4)); + cnt++; + } + if (cell->type == ID(LUT5)) { + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 5)); + cnt++; + } + } + } + log_header(design, "Updated %d of LUT* elements with equation.\n", cnt); + } +} QuicklogicEqnPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 7fddbc97078..15ab68a3f72 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2021 QuickLogic Corp. + * Copyright 2020-2022 F4PGA Authors * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -30,6 +31,7 @@ struct SynthQuickLogicPass : public ScriptPass { void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" synth_quicklogic [options]\n"); log("This command runs synthesis for QuickLogic FPGAs\n"); @@ -42,6 +44,17 @@ struct SynthQuickLogicPass : public ScriptPass { log(" generate the synthesis netlist for the specified family.\n"); log(" supported values:\n"); log(" - pp3: PolarPro 3 \n"); + log(" - qlf_k6n10f: K6N10f\n"); + log("\n"); + log(" -nocarry\n"); + log(" do not use adder_carry cells in output netlist.\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use block RAM cells in output netlist.\n"); + log("\n"); + log(" -bramtypes\n"); + log(" Emit specialized BRAM cells for particular address and data width\n"); + log(" configurations.\n"); log("\n"); log(" -blif \n"); log(" write the design to the specified BLIF file. writing of an output file\n"); @@ -61,7 +74,7 @@ struct SynthQuickLogicPass : public ScriptPass { } string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path; - bool abc9; + bool abc9, inferAdder, nobram, bramTypes; void clear_flags() override { @@ -72,12 +85,26 @@ struct SynthQuickLogicPass : public ScriptPass { currmodule = ""; family = "pp3"; abc9 = true; + inferAdder = true; + nobram = false; + bramTypes = false; + lib_path = "+/quicklogic/"; + } + + void set_scratchpad_defaults(RTLIL::Design *design) { + lib_path = design->scratchpad_get_string("ql.lib_path", lib_path); + if (lib_path.back() != '/') + lib_path += "/"; + inferAdder = !design->scratchpad_get_bool("ql.nocarry", false); + nobram = design->scratchpad_get_bool("ql.nobram", false); + bramTypes = design->scratchpad_get_bool("ql.bramtypes", false); } void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); + set_scratchpad_defaults(design); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -114,6 +141,18 @@ struct SynthQuickLogicPass : public ScriptPass { abc9 = false; continue; } + if (args[argidx] == "-nocarry") { + inferAdder = false; + continue; + } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } + if (args[argidx] == "-bramtypes") { + bramTypes = true; + continue; + } break; } extra_args(args, argidx, design); @@ -121,7 +160,7 @@ struct SynthQuickLogicPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); - if (family != "pp3") + if (family != "pp3" && family != "qlf_k6n10f") log_cmd_error("Invalid family specified: '%s'\n", family.c_str()); if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) { @@ -144,14 +183,22 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("begin")) { - run(stringf("read_verilog -lib -specify +/quicklogic/common/cells_sim.v +/quicklogic/%s/cells_sim.v", family.c_str())); + std::string read_simlibs = stringf("read_verilog -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path.c_str(), lib_path.c_str(), family.c_str()); + if (family == "qlf_k6n10f") { + read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path.c_str()); + if (bramTypes) + read_simlibs += stringf(" %sqlf_k6n10f/bram_types_sim.v", lib_path.c_str()); + } + run(read_simlibs); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } if (check_label("prepare")) { run("proc"); run("flatten"); - run("tribuf -logic"); + if (help_mode || family == "pp3") { + run("tribuf -logic", " (for pp3)"); + } run("deminout"); run("opt_expr"); run("opt_clean"); @@ -176,6 +223,71 @@ struct SynthQuickLogicPass : public ScriptPass { run("opt_clean"); } + if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)") && (help_mode || family == "qlf_k6n10f")) { + run("memory_libmap -lib " + lib_path + family + "/libmap_brams.txt"); + run("ql_bram_merge"); + run("techmap -map " + lib_path + family + "/libmap_brams_map.v"); + run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); + run("techmap -map " + lib_path + family + "/brams_final_map.v"); + + if (help_mode) { + run("chtype -set TDP36K_ t:TDP36K a:", "(if -bram_types)"); + } + else if (bramTypes) { + for (int a_dwidth : {1, 2, 4, 9, 18, 36}) + for (int b_dwidth: {1, 2, 4, 9, 18, 36}) { + run(stringf("chtype -set TDP36K_BRAM_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " + "a:is_fifo=0 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", + a_dwidth, b_dwidth, a_dwidth, b_dwidth)); + + run(stringf("chtype -set TDP36K_FIFO_ASYNC_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " + "a:is_fifo=1 %%i a:sync_fifo=0 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", + a_dwidth, b_dwidth, a_dwidth, b_dwidth)); + + run(stringf("chtype -set TDP36K_FIFO_SYNC_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " + "a:is_fifo=1 %%i a:sync_fifo=1 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", + a_dwidth, b_dwidth, a_dwidth, b_dwidth)); + } + + for (int a1_dwidth : {1, 2, 4, 9, 18}) + for (int b1_dwidth: {1, 2, 4, 9, 18}) + for (int a2_dwidth : {1, 2, 4, 9, 18}) + for (int b2_dwidth: {1, 2, 4, 9, 18}) { + run(stringf("chtype -set TDP36K_BRAM_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " + "a:is_split=1 %%i a:is_fifo=0 %%i " + "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", + a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); + + run(stringf("chtype -set TDP36K_FIFO_ASYNC_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " + "a:is_split=1 %%i a:is_fifo=1 %%i a:sync_fifo=0 %%i " + "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", + a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); + + run(stringf("chtype -set TDP36K_FIFO_SYNC_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " + "a:is_split=1 %%i a:is_fifo=1 %%i a:sync_fifo=1 %%i " + "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", + a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); + } + + + for (int a_width : {1, 2, 4, 9, 18, 36}) + for (int b_width: {1, 2, 4, 9, 18, 36}) { + run(stringf("chtype -set TDP36K_BRAM_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=1 %%i " + "a:port_a_width=%d %%i a:port_b_width=%d %%i", + a_width, b_width, a_width, b_width)); + } + + for (int a1_width : {1, 2, 4, 9, 18}) + for (int b1_width: {1, 2, 4, 9, 18}) + for (int a2_width : {1, 2, 4, 9, 18}) + for (int b2_width: {1, 2, 4, 9, 18}) { + run(stringf("chtype -set TDP36K_BRAM_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=1 %%i " + "a:port_a1_width=%d %%i a:port_b1_width=%d %%i a:port_a2_width=%d %%i a:port_b2_width=%d %%i", + a1_width, b1_width, a2_width, b2_width, a1_width, b1_width, a2_width, b2_width)); + } + } + } + if (check_label("map_ffram")) { run("opt -fast -mux_undef -undriven -fine"); run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block " @@ -185,36 +297,65 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("map_gates")) { - run("techmap"); + if (inferAdder && family == "qlf_k6n10f") { + run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v", "(unless -no_adder)"); + } else { + run("techmap"); + } run("opt -fast"); - run("muxcover -mux8 -mux4"); + if (help_mode || family == "pp3") { + run("muxcover -mux8 -mux4", "(for pp3)"); + } } if (check_label("map_ffs")) { run("opt_expr"); - run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x"); - - run(stringf("techmap -map +/quicklogic/%s/cells_map.v -map +/quicklogic/%s/ffs_map.v", family.c_str(), family.c_str())); - - run("opt_expr -mux_undef"); + if (help_mode) { + run("shregmap -minlen -maxlen ", "(for qlf_k6n10f)"); + run("dfflegalize -cell "); + run("techmap -map " + lib_path + family + "/cells_map.v", "(for pp3)"); + } + if (family == "pp3") { + run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x"); + run("techmap -map " + lib_path + family + "/cells_map.v -map " + lib_path + family + "/ffs_map.v"); + run("opt_expr -mux_undef"); + } else if (family == "qlf_k6n10f") { + run("shregmap -minlen 8 -maxlen 20"); + // FIXME: Apparently dfflegalize leaves around $_DLATCH_[NP]_ even if + // not in the allowed set. As a workaround we put them in the allowed + // set explicitly and map them later to $_DLATCHSR_[NP]NN_. + run("dfflegalize -cell $_DFFSRE_?NNP_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0" " -cell $_SDFFE_?N?P_ 0"); + } + run("opt"); } - if (check_label("map_luts")) { - run(stringf("techmap -map +/quicklogic/%s/latches_map.v", family.c_str())); + if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) { + run("techmap -map " + lib_path + family + "/latches_map.v"); if (abc9) { - run(stringf("read_verilog -lib -specify -icells +/quicklogic/%s/abc9_model.v", family.c_str())); - run(stringf("techmap -map +/quicklogic/%s/abc9_map.v", family.c_str())); + run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v"); + run("techmap -map " + lib_path + family + "/abc9_map.v"); run("abc9 -maxlut 4 -dff"); - run(stringf("techmap -map +/quicklogic/%s/abc9_unmap.v", family.c_str())); + run("techmap -map " + lib_path + family + "/abc9_unmap.v"); } else { run("abc -luts 1,2,2,4 -dress"); } run("clean"); } - if (check_label("map_cells")) { - run(stringf("techmap -map +/quicklogic/%s/lut_map.v", family.c_str())); + if (check_label("map_luts", "(for qlf_k6n10f)") && (help_mode || family == "qlf_k6n10f")) { + if (abc9) { + run("abc9 -maxlut 6"); + } else { + run("abc -lut 6 -dress"); + } + run("clean"); + run("opt_lut"); + } + + if (check_label("map_cells", "(for pp3)") && (help_mode || family == "pp3")) { + run("techmap -map " + lib_path + family + "/lut_map.v"); run("clean"); + run("opt_lut"); } if (check_label("check")) { @@ -224,14 +365,18 @@ struct SynthQuickLogicPass : public ScriptPass { run("check -noinit"); } - if (check_label("iomap")) { + if (check_label("iomap", "(for pp3)") && (family == "pp3" || help_mode)) { run("clkbufmap -inpad ckpad Q:P"); run("iopadmap -bits -outpad outpad A:P -inpad inpad Q:P -tinoutpad bipad EN:Q:A:P A:top"); } if (check_label("finalize")) { - run("setundef -zero -params -undriven"); - run("hilomap -hicell logic_1 A -locell logic_0 A -singleton A:top"); + if (help_mode || family == "pp3") { + run("setundef -zero -params -undriven", "(for pp3)"); + } + if (family == "pp3" || !edif_file.empty()) { + run("hilomap -hicell logic_1 A -locell logic_0 A -singleton A:top", "(for pp3 or if -edif)"); + } run("opt_clean -purge"); run("check"); run("blackbox =A:whitebox"); From 6682693888148594c21bba3a75e1fe0ab6aef950 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 14 Aug 2023 16:20:36 +0200 Subject: [PATCH 169/240] change ql-bram-types pass to use mode parameter; clean up primitive libraries --- techlibs/quicklogic/Makefile.inc | 2 +- techlibs/quicklogic/ql-bram-merge.cc | 348 +- techlibs/quicklogic/ql-bram-types.cc | 165 + techlibs/quicklogic/qlf_k6n10f/arith_map.v | 46 +- .../quicklogic/qlf_k6n10f/bram_types_sim.v | 142779 ++++++++------- .../quicklogic/qlf_k6n10f/brams_final_map.v | 1152 +- techlibs/quicklogic/qlf_k6n10f/brams_map.v | 2426 +- techlibs/quicklogic/qlf_k6n10f/brams_sim.v | 13460 +- techlibs/quicklogic/qlf_k6n10f/cells_sim.v | 534 +- techlibs/quicklogic/qlf_k6n10f/ffs_map.v | 154 +- .../qlf_k6n10f/generate_bram_types_sim.py | 246 + techlibs/quicklogic/quicklogic_eqn.cc | 100 - techlibs/quicklogic/synth_quicklogic.cc | 74 +- 13 files changed, 80867 insertions(+), 80619 deletions(-) create mode 100644 techlibs/quicklogic/ql-bram-types.cc create mode 100644 techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py delete mode 100644 techlibs/quicklogic/quicklogic_eqn.cc diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index fcc49cd77f8..df69a3fc32c 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,6 +1,6 @@ OBJS += techlibs/quicklogic/synth_quicklogic.o OBJS += techlibs/quicklogic/ql-bram-merge.o -OBJS += techlibs/quicklogic/quicklogic_eqn.o +OBJS += techlibs/quicklogic/ql-bram-types.o $(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v)) diff --git a/techlibs/quicklogic/ql-bram-merge.cc b/techlibs/quicklogic/ql-bram-merge.cc index d64bd64cf60..1098bc8f696 100644 --- a/techlibs/quicklogic/ql-bram-merge.cc +++ b/techlibs/quicklogic/ql-bram-merge.cc @@ -31,184 +31,184 @@ PRIVATE_NAMESPACE_BEGIN struct QlBramMergeWorker { - const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K); - const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED); - - // can be used to record parameter values that have to match on both sides - typedef dict MergeableGroupKeyType; - - RTLIL::Module *module; - dict> mergeable_groups; - - QlBramMergeWorker(RTLIL::Module* module) : module(module) - { - for (RTLIL::Cell* cell : module->selected_cells()) - { - if(cell->type != split_cell_type) continue; - if(!cell->hasParam(ID(OPTION_SPLIT))) continue; - if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue; - mergeable_groups[get_key(cell)].insert(cell); - } - } - - static MergeableGroupKeyType get_key(RTLIL::Cell* cell) - { - MergeableGroupKeyType key; - // For now, there are no restrictions on which cells can be merged - (void) cell; - return key; - } - - const dict& param_map(bool second) - { - static const dict bram1_map = { - { ID(INIT), ID(INIT1) }, - { ID(PORT_A_WIDTH), ID(PORT_A1_WIDTH) }, - { ID(PORT_B_WIDTH), ID(PORT_B1_WIDTH) }, - { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A1_WR_BE_WIDTH) }, - { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B1_WR_BE_WIDTH) } - }; - static const dict bram2_map = { - { ID(INIT), ID(INIT2) }, - { ID(PORT_A_WIDTH), ID(PORT_A2_WIDTH) }, - { ID(PORT_B_WIDTH), ID(PORT_B2_WIDTH) }, - { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A2_WR_BE_WIDTH) }, - { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B2_WR_BE_WIDTH) } - }; - - if(second) - return bram2_map; - else - return bram1_map; - } - - const dict& port_map(bool second) - { - static const dict bram1_map = { - { ID(PORT_A_CLK), ID(PORT_A1_CLK) }, - { ID(PORT_B_CLK), ID(PORT_B1_CLK) }, - { ID(PORT_A_CLK_EN), ID(PORT_A1_CLK_EN) }, - { ID(PORT_B_CLK_EN), ID(PORT_B1_CLK_EN) }, - { ID(PORT_A_ADDR), ID(PORT_A1_ADDR) }, - { ID(PORT_B_ADDR), ID(PORT_B1_ADDR) }, - { ID(PORT_A_WR_DATA), ID(PORT_A1_WR_DATA) }, - { ID(PORT_B_WR_DATA), ID(PORT_B1_WR_DATA) }, - { ID(PORT_A_WR_EN), ID(PORT_A1_WR_EN) }, - { ID(PORT_B_WR_EN), ID(PORT_B1_WR_EN) }, - { ID(PORT_A_WR_BE), ID(PORT_A1_WR_BE) }, - { ID(PORT_B_WR_BE), ID(PORT_B1_WR_BE) }, - { ID(PORT_A_RD_DATA), ID(PORT_A1_RD_DATA) }, - { ID(PORT_B_RD_DATA), ID(PORT_B1_RD_DATA) } - }; - static const dict bram2_map = { - { ID(PORT_A_CLK), ID(PORT_A2_CLK) }, - { ID(PORT_B_CLK), ID(PORT_B2_CLK) }, - { ID(PORT_A_CLK_EN), ID(PORT_A2_CLK_EN) }, - { ID(PORT_B_CLK_EN), ID(PORT_B2_CLK_EN) }, - { ID(PORT_A_ADDR), ID(PORT_A2_ADDR) }, - { ID(PORT_B_ADDR), ID(PORT_B2_ADDR) }, - { ID(PORT_A_WR_DATA), ID(PORT_A2_WR_DATA) }, - { ID(PORT_B_WR_DATA), ID(PORT_B2_WR_DATA) }, - { ID(PORT_A_WR_EN), ID(PORT_A2_WR_EN) }, - { ID(PORT_B_WR_EN), ID(PORT_B2_WR_EN) }, - { ID(PORT_A_WR_BE), ID(PORT_A2_WR_BE) }, - { ID(PORT_B_WR_BE), ID(PORT_B2_WR_BE) }, - { ID(PORT_A_RD_DATA), ID(PORT_A2_RD_DATA) }, - { ID(PORT_B_RD_DATA), ID(PORT_B2_RD_DATA) } - }; - - if(second) - return bram2_map; - else - return bram1_map; - } - - void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2) - { - - // Create the new cell - RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type); - log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name)); - - for (auto &it : param_map(false)) - { - if(bram1->hasParam(it.first)) - merged->setParam(it.second, bram1->getParam(it.first)); - } - for (auto &it : param_map(true)) - { - if(bram2->hasParam(it.first)) - merged->setParam(it.second, bram2->getParam(it.first)); - } - - for (auto &it : port_map(false)) - { - if (bram1->hasPort(it.first)) - merged->setPort(it.second, bram1->getPort(it.first)); - else - log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name)); - } - for (auto &it : port_map(true)) - { - if (bram2->hasPort(it.first)) - merged->setPort(it.second, bram2->getPort(it.first)); - else - log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name)); - } - merged->attributes = bram1->attributes; - for (auto attr: bram2->attributes) - if (!merged->has_attribute(attr.first)) - merged->attributes.insert(attr); - - // Remove the old cells - module->remove(bram1); - module->remove(bram2); - - } - - void merge_bram_groups() - { - for (auto &it : mergeable_groups) - { - while (it.second.size() > 1) - { - merge_brams(it.second.pop(), it.second.pop()); - } - } - } + const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K); + const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED); + + // can be used to record parameter values that have to match on both sides + typedef dict MergeableGroupKeyType; + + RTLIL::Module *module; + dict> mergeable_groups; + + QlBramMergeWorker(RTLIL::Module* module) : module(module) + { + for (RTLIL::Cell* cell : module->selected_cells()) + { + if(cell->type != split_cell_type) continue; + if(!cell->hasParam(ID(OPTION_SPLIT))) continue; + if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue; + mergeable_groups[get_key(cell)].insert(cell); + } + } + + static MergeableGroupKeyType get_key(RTLIL::Cell* cell) + { + MergeableGroupKeyType key; + // For now, there are no restrictions on which cells can be merged + (void) cell; + return key; + } + + const dict& param_map(bool second) + { + static const dict bram1_map = { + { ID(INIT), ID(INIT1) }, + { ID(PORT_A_WIDTH), ID(PORT_A1_WIDTH) }, + { ID(PORT_B_WIDTH), ID(PORT_B1_WIDTH) }, + { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A1_WR_BE_WIDTH) }, + { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B1_WR_BE_WIDTH) } + }; + static const dict bram2_map = { + { ID(INIT), ID(INIT2) }, + { ID(PORT_A_WIDTH), ID(PORT_A2_WIDTH) }, + { ID(PORT_B_WIDTH), ID(PORT_B2_WIDTH) }, + { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A2_WR_BE_WIDTH) }, + { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B2_WR_BE_WIDTH) } + }; + + if(second) + return bram2_map; + else + return bram1_map; + } + + const dict& port_map(bool second) + { + static const dict bram1_map = { + { ID(PORT_A_CLK), ID(PORT_A1_CLK) }, + { ID(PORT_B_CLK), ID(PORT_B1_CLK) }, + { ID(PORT_A_CLK_EN), ID(PORT_A1_CLK_EN) }, + { ID(PORT_B_CLK_EN), ID(PORT_B1_CLK_EN) }, + { ID(PORT_A_ADDR), ID(PORT_A1_ADDR) }, + { ID(PORT_B_ADDR), ID(PORT_B1_ADDR) }, + { ID(PORT_A_WR_DATA), ID(PORT_A1_WR_DATA) }, + { ID(PORT_B_WR_DATA), ID(PORT_B1_WR_DATA) }, + { ID(PORT_A_WR_EN), ID(PORT_A1_WR_EN) }, + { ID(PORT_B_WR_EN), ID(PORT_B1_WR_EN) }, + { ID(PORT_A_WR_BE), ID(PORT_A1_WR_BE) }, + { ID(PORT_B_WR_BE), ID(PORT_B1_WR_BE) }, + { ID(PORT_A_RD_DATA), ID(PORT_A1_RD_DATA) }, + { ID(PORT_B_RD_DATA), ID(PORT_B1_RD_DATA) } + }; + static const dict bram2_map = { + { ID(PORT_A_CLK), ID(PORT_A2_CLK) }, + { ID(PORT_B_CLK), ID(PORT_B2_CLK) }, + { ID(PORT_A_CLK_EN), ID(PORT_A2_CLK_EN) }, + { ID(PORT_B_CLK_EN), ID(PORT_B2_CLK_EN) }, + { ID(PORT_A_ADDR), ID(PORT_A2_ADDR) }, + { ID(PORT_B_ADDR), ID(PORT_B2_ADDR) }, + { ID(PORT_A_WR_DATA), ID(PORT_A2_WR_DATA) }, + { ID(PORT_B_WR_DATA), ID(PORT_B2_WR_DATA) }, + { ID(PORT_A_WR_EN), ID(PORT_A2_WR_EN) }, + { ID(PORT_B_WR_EN), ID(PORT_B2_WR_EN) }, + { ID(PORT_A_WR_BE), ID(PORT_A2_WR_BE) }, + { ID(PORT_B_WR_BE), ID(PORT_B2_WR_BE) }, + { ID(PORT_A_RD_DATA), ID(PORT_A2_RD_DATA) }, + { ID(PORT_B_RD_DATA), ID(PORT_B2_RD_DATA) } + }; + + if(second) + return bram2_map; + else + return bram1_map; + } + + void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2) + { + + // Create the new cell + RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type); + log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name)); + + for (auto &it : param_map(false)) + { + if(bram1->hasParam(it.first)) + merged->setParam(it.second, bram1->getParam(it.first)); + } + for (auto &it : param_map(true)) + { + if(bram2->hasParam(it.first)) + merged->setParam(it.second, bram2->getParam(it.first)); + } + + for (auto &it : port_map(false)) + { + if (bram1->hasPort(it.first)) + merged->setPort(it.second, bram1->getPort(it.first)); + else + log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name)); + } + for (auto &it : port_map(true)) + { + if (bram2->hasPort(it.first)) + merged->setPort(it.second, bram2->getPort(it.first)); + else + log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name)); + } + merged->attributes = bram1->attributes; + for (auto attr: bram2->attributes) + if (!merged->has_attribute(attr.first)) + merged->attributes.insert(attr); + + // Remove the old cells + module->remove(bram1); + module->remove(bram2); + + } + + void merge_bram_groups() + { + for (auto &it : mergeable_groups) + { + while (it.second.size() > 1) + { + merge_brams(it.second.pop(), it.second.pop()); + } + } + } }; struct QlBramMergePass : public Pass { - - QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {} - - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" ql_bram_merge [selection]\n"); - log("\n"); - log(" This pass identifies k6n10f 18K BRAM cells and packs pairs of them together\n"); - log(" into a TDP36K cell operating in split mode\n"); - log("\n"); - } - - - - void execute(std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing QL_BRAM_MERGE pass.\n"); - - size_t argidx = 1; - extra_args(args, argidx, design); - - for (RTLIL::Module* module : design->selected_modules()) - { - QlBramMergeWorker worker(module); - worker.merge_bram_groups(); - } - } + + QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_bram_merge [selection]\n"); + log("\n"); + log(" This pass identifies k6n10f 18K BRAM cells and packs pairs of them together\n"); + log(" into a TDP36K cell operating in split mode\n"); + log("\n"); + } + + + + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing QL_BRAM_MERGE pass.\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (RTLIL::Module* module : design->selected_modules()) + { + QlBramMergeWorker worker(module); + worker.merge_bram_groups(); + } + } } QlBramMergePass; diff --git a/techlibs/quicklogic/ql-bram-types.cc b/techlibs/quicklogic/ql-bram-types.cc new file mode 100644 index 00000000000..cf42703aaac --- /dev/null +++ b/techlibs/quicklogic/ql-bram-types.cc @@ -0,0 +1,165 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2023 N. Engelhardt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +// ============================================================================ + + +struct QlBramTypesPass : public Pass { + + QlBramTypesPass() : Pass("ql_bram_types", "Change TDP36K type to subtypes") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_bram_types [selection]\n"); + log("\n"); + log(" This pass changes the type of TDP36K cells to different types based on the\n"); + log(" configuration of the cell.\n"); + log("\n"); + } + + int width_for_mode(int mode){ + // 1: mode = 3'b101; + // 2: mode = 3'b110; + // 4: mode = 3'b100; + // 8,9: mode = 3'b001; + // 16, 18: mode = 3'b010; + // 32, 36: mode = 3'b011; + switch (mode) + { + case 1: + return 9; + case 2: + return 18; + case 3: + return 36; + case 4: + return 4; + case 5: + return 1; + case 6: + return 2; + default: + log_error("Invalid mode: %x", mode); + } + } + + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing QL_BRAM_TYPES pass.\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (RTLIL::Module* module : design->selected_modules()) + for (RTLIL::Cell* cell: module->selected_cells()) + { + if (cell->type != ID(TDP36K) || !cell->hasParam(ID(MODE_BITS))) + continue; + + RTLIL::Const mode_bits = cell->getParam(ID(MODE_BITS)); + + bool split = mode_bits.extract(80).as_bool(); + + bool FMODE1_i = mode_bits.extract(13).as_bool(); + bool FMODE2_i = mode_bits.extract(54).as_bool(); + if (FMODE1_i != FMODE2_i) { + log_debug("Can't change type of mixed use TDP36K block: FMODE1_i = %s, FMODE2_i = %s\n", FMODE1_i ? "true" : "false", FMODE2_i ? "true" : "false"); + continue; + } + bool is_fifo = FMODE1_i; + + bool SYNC_FIFO1_i = mode_bits.extract(0).as_bool(); + bool SYNC_FIFO2_i = mode_bits.extract(41).as_bool(); + if (SYNC_FIFO1_i != SYNC_FIFO2_i) { + log_debug("Can't change type of mixed use TDP36K block: SYNC_FIFO1_i = %s, SYNC_FIFO2_i = %s\n", SYNC_FIFO1_i ? "true" : "false", SYNC_FIFO2_i ? "true" : "false"); + continue; + } + bool sync_fifo = SYNC_FIFO1_i; + + int RMODE_A1_i = mode_bits.extract(1, 3).as_int(); + int RMODE_B1_i = mode_bits.extract(4, 3).as_int(); + int WMODE_A1_i = mode_bits.extract(7, 3).as_int(); + int WMODE_B1_i = mode_bits.extract(10, 3).as_int(); + + int RMODE_A2_i = mode_bits.extract(42, 3).as_int(); + int RMODE_B2_i = mode_bits.extract(45, 3).as_int(); + int WMODE_A2_i = mode_bits.extract(48, 3).as_int(); + int WMODE_B2_i = mode_bits.extract(51, 3).as_int(); + + // TODO: should these be a warning or an error? + if (RMODE_A1_i != WMODE_A1_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port A1 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_A1_i), width_for_mode(WMODE_A1_i)); + continue; + } + if (RMODE_B1_i != WMODE_B1_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port B1 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_B1_i), width_for_mode(WMODE_B1_i)); + continue; + } + if (RMODE_A2_i != WMODE_A2_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port A2 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_A2_i), width_for_mode(WMODE_A2_i)); + continue; + } + if (RMODE_B2_i != WMODE_B2_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port B2 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_B2_i), width_for_mode(WMODE_B2_i)); + continue; + } + + // TODO: For nonsplit blocks, should RMODE_A1_i == RMODE_A2_i etc be checked/enforced? + + std::string type = "TDP36K"; + if (is_fifo) { + type += "_FIFO_"; + if (sync_fifo) + type += "SYNC_"; + else + type += "ASYNC_"; + } else + type += "_BRAM_"; + + if (split) { + type += stringf("A1_X%d_", width_for_mode(RMODE_A1_i)); + type += stringf("B1_X%d_", width_for_mode(RMODE_B1_i)); + type += stringf("A2_X%d_", width_for_mode(RMODE_A2_i)); + type += stringf("B2_X%d_", width_for_mode(RMODE_B2_i)); + type += "split"; + } else { + type += stringf("A_X%d_", width_for_mode(RMODE_A1_i)); + type += stringf("B_X%d_", width_for_mode(RMODE_B1_i)); + type += "nonsplit"; + } + + cell->type = RTLIL::escape_id(type); + log_debug("Changed type of memory cell %s to %s\n", log_id(cell->name), log_id(cell->type)); + } + } + + +} QlBramMergePass; + +PRIVATE_NAMESPACE_END \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/arith_map.v b/techlibs/quicklogic/qlf_k6n10f/arith_map.v index 908b17189c5..d39a3a19f9a 100644 --- a/techlibs/quicklogic/qlf_k6n10f/arith_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/arith_map.v @@ -56,43 +56,43 @@ module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO); (* force_downto *) wire [Y_WIDTH-1:0] S = {AA ^ BB}; assign CO[Y_WIDTH-1:0] = C[Y_WIDTH:1]; - //assign CO[Y_WIDTH-1] = co; + //assign CO[Y_WIDTH-1] = co; generate - adder_carry intermediate_adder ( - .cin ( ), - .cout (C[0]), - .p (1'b0), - .g (CI), - .sumout () - ); + adder_carry intermediate_adder ( + .cin ( ), + .cout (C[0]), + .p (1'b0), + .g (CI), + .sumout () + ); endgenerate genvar i; generate if (Y_WIDTH > 2) begin for (i = 0; i < Y_WIDTH-2; i = i + 1) begin:slice adder_carry my_adder ( - .cin(C[i]), - .g(AA[i]), - .p(S[i]), - .cout(C[i+1]), - .sumout(Y[i]) + .cin (C[i]), + .g (AA[i]), + .p (S[i]), + .cout (C[i+1]), + .sumout (Y[i]) ); - end + end end endgenerate generate - adder_carry final_adder ( - .cin (C[Y_WIDTH-2]), - .cout (), - .p (1'b0), - .g (1'b0), - .sumout (co) - ); + adder_carry final_adder ( + .cin (C[Y_WIDTH-2]), + .cout (), + .p (1'b0), + .g (1'b0), + .sumout (co) + ); endgenerate assign Y[Y_WIDTH-2] = S[Y_WIDTH-2] ^ co; - assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2]; + assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2]; assign Y[Y_WIDTH-1] = S[Y_WIDTH-1] ^ C[Y_WIDTH-1]; - assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1]; + assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1]; assign X = S; endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v b/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v index 3a06f676d68..39e59d43f08 100644 --- a/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v @@ -1,73373 +1,73374 @@ // **AUTOGENERATED FILE** **DO NOT EDIT** -// Generated by qlf_k6n10f/generate_bram_types_sim.py at 2023-05-02 10:42:53.971682+00:00 +// Generated by generate_bram_types_sim.py at 2023-08-17 16:34:43.930013+00:00 +`timescale 1ns /10ps module TDP36K_BRAM_A_X1_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v index 7d04c5dda6c..43f5dc95e94 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v @@ -15,27 +15,27 @@ // SPDX-License-Identifier: Apache-2.0 module BRAM2x18_SP ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o ); parameter WR1_ADDR_WIDTH = 10; @@ -161,10 +161,10 @@ wire [17:0] PORT_B2_RDATA; wire [17:0] PORT_A2_WDATA; wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -190,12 +190,12 @@ localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end endgenerate case (WR1_DATA_WIDTH) @@ -220,12 +220,12 @@ case (WR1_DATA_WIDTH) endcase generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end endgenerate case (RD1_DATA_WIDTH) @@ -250,12 +250,12 @@ case (RD1_DATA_WIDTH) endcase generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end endgenerate case (WR2_DATA_WIDTH) @@ -280,12 +280,12 @@ case (WR2_DATA_WIDTH) endcase generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end endgenerate case (RD2_DATA_WIDTH) @@ -344,49 +344,49 @@ assign WEN_B2_i = 1'b0; assign BE_B2_i = 4'h0; generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA[17:0]; assign WDATA_B1_i = 18'h0; generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA[17:0]; assign WDATA_B2_i = 18'h0; generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; @@ -442,44 +442,44 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module BRAM2x18_dP ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o ); parameter PORT_A1_AWIDTH = 10; parameter PORT_A1_DWIDTH = 18; parameter PORT_A1_WR_BE_WIDTH = 2; - + parameter PORT_B1_AWIDTH = 10; parameter PORT_B1_DWIDTH = 18; parameter PORT_B1_WR_BE_WIDTH = 2; @@ -487,7 +487,7 @@ parameter PORT_B1_WR_BE_WIDTH = 2; parameter PORT_A2_AWIDTH = 10; parameter PORT_A2_DWIDTH = 18; parameter PORT_A2_WR_BE_WIDTH = 2; - + parameter PORT_B2_AWIDTH = 10; parameter PORT_B2_DWIDTH = 18; parameter PORT_B2_WR_BE_WIDTH = 2; @@ -621,11 +621,11 @@ wire [17:0] PORT_A2_WDATA; wire [17:0] PORT_A2_RDATA; wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - +wire [13:0] PORT_B2_ADDR_INT; + wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -661,12 +661,12 @@ assign PORT_A2_CLK = PORT_A2_CLK_i; assign PORT_B2_CLK = PORT_B2_CLK_i; generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end endgenerate case (PORT_A1_DWIDTH) @@ -691,12 +691,12 @@ case (PORT_A1_DWIDTH) endcase generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end endgenerate case (PORT_B1_DWIDTH) @@ -721,12 +721,12 @@ case (PORT_B1_DWIDTH) endcase generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end endgenerate case (PORT_A2_DWIDTH) @@ -751,12 +751,12 @@ case (PORT_A2_DWIDTH) endcase generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end endgenerate case (PORT_B2_DWIDTH) @@ -837,93 +837,93 @@ assign WEN_B2_i = PORT_B2_WEN_i; assign BE_B2_i = PORT_B2_WR_BE; generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA; generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA; generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end endgenerate assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end endgenerate assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B1_WDATA; generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end endgenerate assign WDATA_B2_i = PORT_B2_WDATA; generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; @@ -981,209 +981,209 @@ endmodule module BRAM2x18_SFIFO ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input CLK1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input CLK2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = PORT_A1_WRWIDTH *) - (* port_b_dwidth = PORT_B1_WRWIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -1224,207 +1224,207 @@ endmodule module BRAM2x18_AFIFO ( - DIN1, - PUSH1, - POP1, - Push_Clk1, + DIN1, + PUSH1, + POP1, + Push_Clk1, Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input Push_Clk1, Pop_Clk1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input Push_Clk2, Pop_Clk2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = PORT_A1_WRWIDTH *) - (* port_b_dwidth = PORT_B1_WRWIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_map.v index 42e1fc98b85..82bbceeff52 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_map.v @@ -15,15 +15,15 @@ // SPDX-License-Identifier: Apache-2.0 module RAM_36K_BLK ( - WEN_i, - REN_i, - WR_CLK_i, - RD_CLK_i, - WR_BE_i, - WR_ADDR_i, - RD_ADDR_i, - WDATA_i, - RDATA_o + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o ); parameter WR_ADDR_WIDTH = 10; @@ -130,7 +130,7 @@ wire [35:0] PORT_B_RDATA; wire [35:0] PORT_A_WDATA; wire [14:0] WR_ADDR_INT; -wire [14:0] RD_ADDR_INT; +wire [14:0] RD_ADDR_INT; wire [14:0] PORT_A_ADDR; wire [14:0] PORT_B_ADDR; @@ -156,12 +156,12 @@ assign PORT_A_CLK = WR_CLK_i; assign PORT_B_CLK = RD_CLK_i; generate - if (WR_ADDR_WIDTH == 15) begin - assign WR_ADDR_INT = WR_ADDR_i; - end else begin - assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; - assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; - end + if (WR_ADDR_WIDTH == 15) begin + assign WR_ADDR_INT = WR_ADDR_i; + end else begin + assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; + assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; + end endgenerate case (WR_DATA_WIDTH) @@ -189,12 +189,12 @@ case (WR_DATA_WIDTH) endcase generate - if (RD_ADDR_WIDTH == 15) begin - assign RD_ADDR_INT = RD_ADDR_i; - end else begin - assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; - assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; - end + if (RD_ADDR_WIDTH == 15) begin + assign RD_ADDR_INT = RD_ADDR_i; + end else begin + assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; + assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; + end endgenerate case (RD_DATA_WIDTH) @@ -240,17 +240,17 @@ assign WEN_B1_i = 1'b0; assign {BE_B2_i, BE_B1_i} = 4'h0; generate - if (WR_DATA_WIDTH == 36) begin - assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; - assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; - end else begin - assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; - assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; - end + if (WR_DATA_WIDTH == 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A_WDATA[17:0]; @@ -260,15 +260,15 @@ assign WDATA_B1_i = 18'h0; assign WDATA_B2_i = 18'h0; generate - if (RD_DATA_WIDTH == 36) begin - assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; - end + if (RD_DATA_WIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end endgenerate assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0]; @@ -326,15 +326,15 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module RAM_18K_BLK ( - WEN_i, - REN_i, - WR_CLK_i, - RD_CLK_i, - WR_BE_i, - WR_ADDR_i, - RD_ADDR_i, - WDATA_i, - RDATA_o + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o ); parameter WR_ADDR_WIDTH = 10; @@ -353,69 +353,69 @@ input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; input wire [WR_DATA_WIDTH-1 :0] WDATA_i; output wire [RD_DATA_WIDTH-1 :0] RDATA_o; - (* is_inferred = 0 *) - (* is_split = 0 *) - (* is_fifo = 0 *) - BRAM2x18_SP #( - .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), - .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .BE1_WIDTH(BE_WIDTH), - .WR2_ADDR_WIDTH(), - .RD2_ADDR_WIDTH(), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .BE2_WIDTH() - ) U1 - ( - .RESET_ni(1'b1), - - .WEN1_i(WEN_i), - .REN1_i(REN_i), - .WR1_CLK_i(WR_CLK_i), - .RD1_CLK_i(RD_CLK_i), - .WR1_BE_i(WR_BE_i), - .WR1_ADDR_i(WR_ADDR_i), - .RD1_ADDR_i(RD_ADDR_i), - .WDATA1_i(WDATA_i), - .RDATA1_o(RDATA_o), - - .WEN2_i(1'b0), - .REN2_i(1'b0), - .WR2_CLK_i(1'b0), - .RD2_CLK_i(1'b0), - .WR2_BE_i(2'b00), - .WR2_ADDR_i(14'h0), - .RD2_ADDR_i(14'h0), - .WDATA2_i(18'h0), - .RDATA2_o() - ); - + (* is_inferred = 0 *) + (* is_split = 0 *) + (* is_fifo = 0 *) + BRAM2x18_SP #( + .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), + .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .BE1_WIDTH(BE_WIDTH), + .WR2_ADDR_WIDTH(), + .RD2_ADDR_WIDTH(), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .BE2_WIDTH() + ) U1 + ( + .RESET_ni(1'b1), + + .WEN1_i(WEN_i), + .REN1_i(REN_i), + .WR1_CLK_i(WR_CLK_i), + .RD1_CLK_i(RD_CLK_i), + .WR1_BE_i(WR_BE_i), + .WR1_ADDR_i(WR_ADDR_i), + .RD1_ADDR_i(RD_ADDR_i), + .WDATA1_i(WDATA_i), + .RDATA1_o(RDATA_o), + + .WEN2_i(1'b0), + .REN2_i(1'b0), + .WR2_CLK_i(1'b0), + .RD2_CLK_i(1'b0), + .WR2_BE_i(2'b00), + .WR2_ADDR_i(14'h0), + .RD2_ADDR_i(14'h0), + .WDATA2_i(18'h0), + .RDATA2_o() + ); + endmodule module RAM_18K_X2_BLK ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o ); parameter WR1_ADDR_WIDTH = 10; @@ -541,10 +541,10 @@ wire [17:0] PORT_B2_RDATA; wire [17:0] PORT_A2_WDATA; wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -570,12 +570,12 @@ localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end endgenerate case (WR1_DATA_WIDTH) @@ -600,12 +600,12 @@ case (WR1_DATA_WIDTH) endcase generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end endgenerate case (RD1_DATA_WIDTH) @@ -630,12 +630,12 @@ case (RD1_DATA_WIDTH) endcase generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end endgenerate case (WR2_DATA_WIDTH) @@ -660,12 +660,12 @@ case (WR2_DATA_WIDTH) endcase generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end endgenerate case (RD2_DATA_WIDTH) @@ -724,49 +724,49 @@ assign WEN_B2_i = 1'b0; assign BE_B2_i = 4'h0; generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA[17:0]; assign WDATA_B1_i = 18'h0; generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA[17:0]; assign WDATA_B2_i = 18'h0; generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; @@ -824,22 +824,22 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module DPRAM_36K_BLK ( - PORT_A_CLK_i, - PORT_A_WEN_i, - PORT_A_WR_BE_i, - PORT_A_REN_i, - PORT_A_ADDR_i, - PORT_A_WR_DATA_i, - PORT_A_RD_DATA_o, - - PORT_B_CLK_i, - PORT_B_WEN_i, - PORT_B_WR_BE_i, - PORT_B_REN_i, - PORT_B_ADDR_i, - PORT_B_WR_DATA_i, - PORT_B_RD_DATA_o +module DPRAM_36K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o ); parameter PORT_A_AWIDTH = 10; @@ -956,7 +956,7 @@ wire [35:0] PORT_A_WDATA; wire [35:0] PORT_A_RDATA; wire [14:0] PORT_A_ADDR_INT; -wire [14:0] PORT_B_ADDR_INT; +wire [14:0] PORT_B_ADDR_INT; wire [14:0] PORT_A_ADDR; wire [14:0] PORT_B_ADDR; @@ -982,12 +982,12 @@ assign PORT_A_CLK = PORT_A_CLK_i; assign PORT_B_CLK = PORT_B_CLK_i; generate - if (PORT_A_AWIDTH == 15) begin - assign PORT_A_ADDR_INT = PORT_A_ADDR_i; - end else begin - assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; - assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; - end + if (PORT_A_AWIDTH == 15) begin + assign PORT_A_ADDR_INT = PORT_A_ADDR_i; + end else begin + assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; + assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; + end endgenerate case (PORT_A_DWIDTH) @@ -1015,12 +1015,12 @@ case (PORT_A_DWIDTH) endcase generate - if (PORT_B_AWIDTH == 15) begin - assign PORT_B_ADDR_INT = PORT_B_ADDR_i; - end else begin - assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; - assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; - end + if (PORT_B_AWIDTH == 15) begin + assign PORT_B_ADDR_INT = PORT_B_ADDR_i; + end else begin + assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; + assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; + end endgenerate case (PORT_B_DWIDTH) @@ -1076,63 +1076,63 @@ assign WEN_B1_i = PORT_B_WEN_i; assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; generate - if (PORT_A_DWIDTH == 36) begin - assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; - end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin - assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; - assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; - end else if (PORT_A_DWIDTH == 9) begin - assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; - end else begin - assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; - assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; - end + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A_WDATA[17:0]; assign WDATA_A2_i = PORT_A_WDATA[35:18]; generate - if (PORT_A_DWIDTH == 36) begin - assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; - end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin - assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; - end else if (PORT_A_DWIDTH == 9) begin - assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; - end + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; + end endgenerate assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0]; generate - if (PORT_B_DWIDTH == 36) begin - assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; - end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin - assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; - assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; - end else if (PORT_B_DWIDTH == 9) begin - assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; - end else begin - assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; - assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; - end + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; + assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; + end else begin + assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B_WDATA[17:0]; assign WDATA_B2_i = PORT_B_WDATA[35:18]; generate - if (PORT_B_DWIDTH == 36) begin - assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; - end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin - assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; - end else if (PORT_B_DWIDTH == 9) begin - assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; - end + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end endgenerate assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0]; @@ -1188,22 +1188,22 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module DPRAM_18K_BLK ( - PORT_A_CLK_i, - PORT_A_WEN_i, - PORT_A_WR_BE_i, - PORT_A_REN_i, - PORT_A_ADDR_i, - PORT_A_WR_DATA_i, - PORT_A_RD_DATA_o, - - PORT_B_CLK_i, - PORT_B_WEN_i, - PORT_B_WR_BE_i, - PORT_B_REN_i, - PORT_B_ADDR_i, - PORT_B_WR_DATA_i, - PORT_B_RD_DATA_o +module DPRAM_18K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o ); parameter PORT_A_AWIDTH = 10; @@ -1248,80 +1248,80 @@ BRAM2x18_dP #( .PORT_B2_DWIDTH(), .PORT_B2_WR_BE_WIDTH() ) U1 ( - .PORT_A1_CLK_i(PORT_A_CLK_i), - .PORT_A1_WEN_i(PORT_A_WEN_i), - .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), - .PORT_A1_REN_i(PORT_A_REN_i), - .PORT_A1_ADDR_i(PORT_A_ADDR_i), - .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), - .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), - - .PORT_B1_CLK_i(PORT_B_CLK_i), - .PORT_B1_WEN_i(PORT_B_WEN_i), - .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), - .PORT_B1_REN_i(PORT_B_REN_i), - .PORT_B1_ADDR_i(PORT_B_ADDR_i), - .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), - .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), - - .PORT_A2_CLK_i(1'b0), - .PORT_A2_WEN_i(1'b0), - .PORT_A2_WR_BE_i(2'b00), - .PORT_A2_REN_i(1'b0), - .PORT_A2_ADDR_i(14'h0), - .PORT_A2_WR_DATA_i(18'h0), - .PORT_A2_RD_DATA_o(), - - .PORT_B2_CLK_i(1'b0), - .PORT_B2_WEN_i(1'b0), - .PORT_B2_WR_BE_i(2'b00), - .PORT_B2_REN_i(1'b0), - .PORT_B2_ADDR_i(14'h0), - .PORT_B2_WR_DATA_i(18'h0), - .PORT_B2_RD_DATA_o() + .PORT_A1_CLK_i(PORT_A_CLK_i), + .PORT_A1_WEN_i(PORT_A_WEN_i), + .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), + .PORT_A1_REN_i(PORT_A_REN_i), + .PORT_A1_ADDR_i(PORT_A_ADDR_i), + .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), + .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), + + .PORT_B1_CLK_i(PORT_B_CLK_i), + .PORT_B1_WEN_i(PORT_B_WEN_i), + .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), + .PORT_B1_REN_i(PORT_B_REN_i), + .PORT_B1_ADDR_i(PORT_B_ADDR_i), + .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), + .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), + + .PORT_A2_CLK_i(1'b0), + .PORT_A2_WEN_i(1'b0), + .PORT_A2_WR_BE_i(2'b00), + .PORT_A2_REN_i(1'b0), + .PORT_A2_ADDR_i(14'h0), + .PORT_A2_WR_DATA_i(18'h0), + .PORT_A2_RD_DATA_o(), + + .PORT_B2_CLK_i(1'b0), + .PORT_B2_WEN_i(1'b0), + .PORT_B2_WR_BE_i(2'b00), + .PORT_B2_REN_i(1'b0), + .PORT_B2_ADDR_i(14'h0), + .PORT_B2_WR_DATA_i(18'h0), + .PORT_B2_RD_DATA_o() ); endmodule -module DPRAM_18K_X2_BLK ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o +module DPRAM_18K_X2_BLK ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o ); parameter PORT_A1_AWIDTH = 10; parameter PORT_A1_DWIDTH = 18; parameter PORT_A1_WR_BE_WIDTH = 2; - + parameter PORT_B1_AWIDTH = 10; parameter PORT_B1_DWIDTH = 18; parameter PORT_B1_WR_BE_WIDTH = 2; @@ -1329,7 +1329,7 @@ parameter PORT_B1_WR_BE_WIDTH = 2; parameter PORT_A2_AWIDTH = 10; parameter PORT_A2_DWIDTH = 18; parameter PORT_A2_WR_BE_WIDTH = 2; - + parameter PORT_B2_AWIDTH = 10; parameter PORT_B2_DWIDTH = 18; parameter PORT_B2_WR_BE_WIDTH = 2; @@ -1464,11 +1464,11 @@ wire [17:0] PORT_A2_WDATA; wire [17:0] PORT_A2_RDATA; wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - +wire [13:0] PORT_B2_ADDR_INT; + wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -1504,12 +1504,12 @@ assign PORT_A2_CLK = PORT_A2_CLK_i; assign PORT_B2_CLK = PORT_B2_CLK_i; generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end endgenerate case (PORT_A1_DWIDTH) @@ -1534,12 +1534,12 @@ case (PORT_A1_DWIDTH) endcase generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end endgenerate case (PORT_B1_DWIDTH) @@ -1564,12 +1564,12 @@ case (PORT_B1_DWIDTH) endcase generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end endgenerate case (PORT_A2_DWIDTH) @@ -1594,12 +1594,12 @@ case (PORT_A2_DWIDTH) endcase generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end endgenerate case (PORT_B2_DWIDTH) @@ -1680,93 +1680,93 @@ assign WEN_B2_i = PORT_B2_WEN_i; assign BE_B2_i = PORT_B2_WR_BE; generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA; generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA; generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end endgenerate assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end endgenerate assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B1_WDATA; generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end endgenerate assign WDATA_B2_i = PORT_B2_WDATA; generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; @@ -1825,154 +1825,154 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module SFIFO_36K_BLK ( - DIN, - PUSH, - POP, - CLK, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - parameter WR_DATA_WIDTH = 36; - parameter RD_DATA_WIDTH = 36; - parameter UPAE_DBITS = 12'd10; - parameter UPAF_DBITS = 12'd10; - - input wire CLK; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS; - localparam [11:0] UPAF1_i = UPAF_DBITS; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd0; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = 11'd10; - localparam [10:0] UPAF2_i = 11'd10; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - 32, 36: rwmode = 36; - default: rwmode = 36; - endcase - endfunction - - wire [35:0] in_reg; - wire [35:0] out_reg; - wire [17:0] fifo_flags; - - wire [35:0] RD_DATA_INT; - - wire Push_Clk, Pop_Clk; - - assign Push_Clk = CLK; - assign Pop_Clk = CLK; - - assign Overrun_Error = fifo_flags[0]; - assign Full_Watermark = fifo_flags[1]; - assign Almost_Full = fifo_flags[2]; - assign Full = fifo_flags[3]; - assign Underrun_Error = fifo_flags[4]; - assign Empty_Watermark = fifo_flags[5]; - assign Almost_Empty = fifo_flags[6]; - assign Empty = fifo_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); - - localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); - localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); - - generate - if (WR_DATA_WIDTH == 36) begin - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; - assign in_reg[17:0] = {2'b00,DIN[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; - end else begin - assign in_reg[35:WR_DATA_WIDTH] = 0; - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD_DATA_WIDTH == 36) begin - assign RD_DATA_INT = out_reg; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; - end else begin - assign RD_DATA_INT = {18'h0, out_reg[17:0]}; - end - endgenerate - - assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + 32, 36: rwmode = 36; + default: rwmode = 36; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + + wire Push_Clk, Pop_Clk; + + assign Push_Clk = CLK; + assign Pop_Clk = CLK; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); + localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_inferred = 0 *) - (* is_split = 0 *) - (* port_a_dwidth = PORT_A_WRWIDTH *) - (* port_b_dwidth = PORT_B_WRWIDTH *) - TDP36K _TECHMAP_REPLACE_ ( + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = PORT_A_WRWIDTH *) + (* port_b_dwidth = PORT_B_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg[17:0]), .WDATA_A2_i(in_reg[35:18]), @@ -2008,155 +2008,155 @@ module SFIFO_36K_BLK ( .FLUSH2_i(1'b0) ); - -endmodule + +endmodule module AFIFO_36K_BLK ( - DIN, - PUSH, - POP, - Push_Clk, - Pop_Clk, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - parameter WR_DATA_WIDTH = 36; - parameter RD_DATA_WIDTH = 36; - parameter UPAE_DBITS = 12'd10; - parameter UPAF_DBITS = 12'd10; - - input wire Push_Clk, Pop_Clk; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS; - localparam [11:0] UPAF1_i = UPAF_DBITS; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd0; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = 11'd10; - localparam [10:0] UPAF2_i = 11'd10; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - 32, 36: rwmode = 36; - default: rwmode = 36; - endcase - endfunction - - wire [35:0] in_reg; - wire [35:0] out_reg; - wire [17:0] fifo_flags; - - wire [35:0] RD_DATA_INT; - wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; - - assign Overrun_Error = fifo_flags[0]; - assign Full_Watermark = fifo_flags[1]; - assign Almost_Full = fifo_flags[2]; - assign Full = fifo_flags[3]; - assign Underrun_Error = fifo_flags[4]; - assign Empty_Watermark = fifo_flags[5]; - assign Almost_Empty = fifo_flags[6]; - assign Empty = fifo_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); - - localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); - localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); - - generate - if (WR_DATA_WIDTH == 36) begin - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; - assign in_reg[17:0] = {2'b00,DIN[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; - end else begin - assign in_reg[35:WR_DATA_WIDTH] = 0; - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD_DATA_WIDTH == 36) begin - assign RD_DATA_INT = out_reg; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; - end else begin - assign RD_DATA_INT = {18'h0, out_reg[17:0]}; - end - endgenerate - - assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + 32, 36: rwmode = 36; + default: rwmode = 36; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); + localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_inferred = 0 *) - (* is_split = 0 *) - (* port_a_dwidth = PORT_A_WRWIDTH *) - (* port_b_dwidth = PORT_B_WRWIDTH *) + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = PORT_A_WRWIDTH *) + (* port_b_dwidth = PORT_B_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg[17:0]), @@ -2193,292 +2193,292 @@ module AFIFO_36K_BLK ( .FLUSH2_i(1'b0) ); - -endmodule + +endmodule module SFIFO_18K_BLK ( - DIN, - PUSH, - POP, - CLK, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - - parameter WR_DATA_WIDTH = 18; - parameter RD_DATA_WIDTH = 18; - parameter UPAE_DBITS = 11'd10; - parameter UPAF_DBITS = 11'd10; - - input wire CLK; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + BRAM2x18_SFIFO #( - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .UPAE_DBITS1(UPAE_DBITS), - .UPAF_DBITS1(UPAF_DBITS), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .UPAE_DBITS2(), - .UPAF_DBITS2() - ) U1 - ( - .DIN1(DIN), - .PUSH1(PUSH), - .POP1(POP), - .CLK1(CLK), - .Async_Flush1(Async_Flush), - .Overrun_Error1(Overrun_Error), - .Full_Watermark1(Full_Watermark), - .Almost_Full1(Almost_Full), - .Full1(Full), - .Underrun_Error1(Underrun_Error), - .Empty_Watermark1(Empty_Watermark), - .Almost_Empty1(Almost_Empty), - .Empty1(Empty), - .DOUT1(DOUT), - - .DIN2(18'h0), - .PUSH2(1'b0), - .POP2(1'b0), - .CLK2(1'b0), - .Async_Flush2(1'b0), - .Overrun_Error2(), - .Full_Watermark2(), - .Almost_Full2(), - .Full2(), - .Underrun_Error2(), - .Empty_Watermark2(), - .Almost_Empty2(), - .Empty2(), - .DOUT2() + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .CLK1(CLK), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .CLK2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() ); endmodule module SFIFO_18K_X2_BLK ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input CLK1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input CLK2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 1 *) - (* is_inferred = 0 *) - (* port_a1_dwidth = PORT_A1_WRWIDTH *) - (* port_a2_dwidth = PORT_A2_WRWIDTH *) - (* port_b1_dwidth = PORT_B1_WRWIDTH *) - (* port_b2_dwidth = PORT_B2_WRWIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = PORT_A1_WRWIDTH *) + (* port_a2_dwidth = PORT_A2_WRWIDTH *) + (* port_b1_dwidth = PORT_B1_WRWIDTH *) + (* port_b2_dwidth = PORT_B2_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -2518,288 +2518,288 @@ module SFIFO_18K_X2_BLK ( endmodule module AFIFO_18K_BLK ( - DIN, - PUSH, - POP, - Push_Clk, - Pop_Clk, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - - parameter WR_DATA_WIDTH = 18; - parameter RD_DATA_WIDTH = 18; - parameter UPAE_DBITS = 11'd10; - parameter UPAF_DBITS = 11'd10; - - input wire Push_Clk, Pop_Clk; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + BRAM2x18_AFIFO #( - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .UPAE_DBITS1(UPAE_DBITS), - .UPAF_DBITS1(UPAF_DBITS), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .UPAE_DBITS2(), - .UPAF_DBITS2() - ) U1 - ( - .DIN1(DIN), - .PUSH1(PUSH), - .POP1(POP), - .Push_Clk1(Push_Clk), - .Pop_Clk1(Pop_Clk), - .Async_Flush1(Async_Flush), - .Overrun_Error1(Overrun_Error), - .Full_Watermark1(Full_Watermark), - .Almost_Full1(Almost_Full), - .Full1(Full), - .Underrun_Error1(Underrun_Error), - .Empty_Watermark1(Empty_Watermark), - .Almost_Empty1(Almost_Empty), - .Empty1(Empty), - .DOUT1(DOUT), - - .DIN2(18'h0), - .PUSH2(1'b0), - .POP2(1'b0), - .Push_Clk2(1'b0), - .Pop_Clk2(1'b0), - .Async_Flush2(1'b0), - .Overrun_Error2(), - .Full_Watermark2(), - .Almost_Full2(), - .Full2(), - .Underrun_Error2(), - .Empty_Watermark2(), - .Almost_Empty2(), - .Empty2(), - .DOUT2() + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .Push_Clk1(Push_Clk), + .Pop_Clk1(Pop_Clk), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .Push_Clk2(1'b0), + .Pop_Clk2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() ); endmodule module AFIFO_18K_X2_BLK ( - DIN1, - PUSH1, - POP1, - Push_Clk1, + DIN1, + PUSH1, + POP1, + Push_Clk1, Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input Push_Clk1, Pop_Clk1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input Push_Clk2, Pop_Clk2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 1 *) - (* is_inferred = 0 *) - (* port_a1_dwidth = PORT_A1_WRWIDTH *) - (* port_a2_dwidth = PORT_A2_WRWIDTH *) - (* port_b1_dwidth = PORT_B1_WRWIDTH *) - (* port_b2_dwidth = PORT_B2_WRWIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = PORT_A1_WRWIDTH *) + (* port_a2_dwidth = PORT_A2_WRWIDTH *) + (* port_b1_dwidth = PORT_B1_WRWIDTH *) + (* port_b2_dwidth = PORT_B2_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_sim.v b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v index 2c2b814abb1..5f04c0e7fac 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v @@ -18,685 +18,685 @@ `default_nettype none module TDP36K ( - RESET_ni, - WEN_A1_i, - WEN_B1_i, - REN_A1_i, - REN_B1_i, - CLK_A1_i, - CLK_B1_i, - BE_A1_i, - BE_B1_i, - ADDR_A1_i, - ADDR_B1_i, - WDATA_A1_i, - WDATA_B1_i, - RDATA_A1_o, - RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, - WEN_B2_i, - REN_A2_i, - REN_B2_i, - CLK_A2_i, - CLK_B2_i, - BE_A2_i, - BE_B2_i, - ADDR_A2_i, - ADDR_B2_i, - WDATA_A2_i, - WDATA_B2_i, - RDATA_A2_o, - RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, + WEN_B1_i, + REN_A1_i, + REN_B1_i, + CLK_A1_i, + CLK_B1_i, + BE_A1_i, + BE_B1_i, + ADDR_A1_i, + ADDR_B1_i, + WDATA_A1_i, + WDATA_B1_i, + RDATA_A1_o, + RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, + WEN_B2_i, + REN_A2_i, + REN_B2_i, + CLK_A2_i, + CLK_B2_i, + BE_A2_i, + BE_B2_i, + ADDR_A2_i, + ADDR_B2_i, + WDATA_A2_i, + WDATA_B2_i, + RDATA_A2_o, + RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - // First 18K RAMFIFO (41 bits) - localparam [ 0:0] SYNC_FIFO1_i = MODE_BITS[0]; - localparam [ 2:0] RMODE_A1_i = MODE_BITS[3 : 1]; - localparam [ 2:0] RMODE_B1_i = MODE_BITS[6 : 4]; - localparam [ 2:0] WMODE_A1_i = MODE_BITS[9 : 7]; - localparam [ 2:0] WMODE_B1_i = MODE_BITS[12:10]; - localparam [ 0:0] FMODE1_i = MODE_BITS[13]; - localparam [ 0:0] POWERDN1_i = MODE_BITS[14]; - localparam [ 0:0] SLEEP1_i = MODE_BITS[15]; - localparam [ 0:0] PROTECT1_i = MODE_BITS[16]; - localparam [11:0] UPAE1_i = MODE_BITS[28:17]; - localparam [11:0] UPAF1_i = MODE_BITS[40:29]; - - // Second 18K RAMFIFO (39 bits) - localparam [ 0:0] SYNC_FIFO2_i = MODE_BITS[41]; - localparam [ 2:0] RMODE_A2_i = MODE_BITS[44:42]; - localparam [ 2:0] RMODE_B2_i = MODE_BITS[47:45]; - localparam [ 2:0] WMODE_A2_i = MODE_BITS[50:48]; - localparam [ 2:0] WMODE_B2_i = MODE_BITS[53:51]; - localparam [ 0:0] FMODE2_i = MODE_BITS[54]; - localparam [ 0:0] POWERDN2_i = MODE_BITS[55]; - localparam [ 0:0] SLEEP2_i = MODE_BITS[56]; - localparam [ 0:0] PROTECT2_i = MODE_BITS[57]; - localparam [10:0] UPAE2_i = MODE_BITS[68:58]; - localparam [10:0] UPAF2_i = MODE_BITS[79:69]; - - // Split (1 bit) - localparam [ 0:0] SPLIT_i = MODE_BITS[80]; - - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - input wire RESET_ni; - input wire WEN_A1_i; - input wire WEN_B1_i; - input wire REN_A1_i; - input wire REN_B1_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - input wire [1:0] BE_A1_i; - input wire [1:0] BE_B1_i; - input wire [14:0] ADDR_A1_i; - input wire [14:0] ADDR_B1_i; - input wire [17:0] WDATA_A1_i; - input wire [17:0] WDATA_B1_i; - output reg [17:0] RDATA_A1_o; - output reg [17:0] RDATA_B1_o; - input wire FLUSH1_i; - input wire WEN_A2_i; - input wire WEN_B2_i; - input wire REN_A2_i; - input wire REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - input wire [1:0] BE_A2_i; - input wire [1:0] BE_B2_i; - input wire [13:0] ADDR_A2_i; - input wire [13:0] ADDR_B2_i; - input wire [17:0] WDATA_A2_i; - input wire [17:0] WDATA_B2_i; - output reg [17:0] RDATA_A2_o; - output reg [17:0] RDATA_B2_o; - input wire FLUSH2_i; - wire EMPTY2; - wire EPO2; - wire EWM2; - wire FULL2; - wire FMO2; - wire FWM2; - wire EMPTY1; - wire EPO1; - wire EWM1; - wire FULL1; - wire FMO1; - wire FWM1; - wire UNDERRUN1; - wire OVERRUN1; - wire UNDERRUN2; - wire OVERRUN2; - wire UNDERRUN3; - wire OVERRUN3; - wire EMPTY3; - wire EPO3; - wire EWM3; - wire FULL3; - wire FMO3; - wire FWM3; - wire ram_fmode1; - wire ram_fmode2; - wire [17:0] ram_rdata_a1; - wire [17:0] ram_rdata_b1; - wire [17:0] ram_rdata_a2; - wire [17:0] ram_rdata_b2; - reg [17:0] ram_wdata_a1; - reg [17:0] ram_wdata_b1; - reg [17:0] ram_wdata_a2; - reg [17:0] ram_wdata_b2; - reg [14:0] laddr_a1; - reg [14:0] laddr_b1; - wire [13:0] ram_addr_a1; - wire [13:0] ram_addr_b1; - wire [13:0] ram_addr_a2; - wire [13:0] ram_addr_b2; - wire smux_clk_a1; - wire smux_clk_b1; - wire smux_clk_a2; - wire smux_clk_b2; - reg [1:0] ram_be_a1; - reg [1:0] ram_be_a2; - reg [1:0] ram_be_b1; - reg [1:0] ram_be_b2; - wire [2:0] ram_rmode_a1; - wire [2:0] ram_wmode_a1; - wire [2:0] ram_rmode_b1; - wire [2:0] ram_wmode_b1; - wire [2:0] ram_rmode_a2; - wire [2:0] ram_wmode_a2; - wire [2:0] ram_rmode_b2; - wire [2:0] ram_wmode_b2; - wire ram_ren_a1; - wire ram_ren_b1; - wire ram_ren_a2; - wire ram_ren_b2; - wire ram_wen_a1; - wire ram_wen_b1; - wire ram_wen_a2; - wire ram_wen_b2; - wire ren_o; - wire [11:0] ff_raddr; - wire [11:0] ff_waddr; - reg [35:0] fifo_rdata; - wire [1:0] fifo_rmode; - wire [1:0] fifo_wmode; - wire [1:0] bwl; - wire [17:0] pl_dout0; - wire [17:0] pl_dout1; - wire sclk_a1; - wire sclk_b1; - wire sclk_a2; - wire sclk_b2; - wire sreset; - wire flush1; - wire flush2; - assign sreset = RESET_ni; - assign flush1 = ~FLUSH1_i; - assign flush2 = ~FLUSH2_i; - assign ram_fmode1 = FMODE1_i & SPLIT_i; - assign ram_fmode2 = FMODE2_i & SPLIT_i; - assign smux_clk_a1 = CLK_A1_i; - assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i); - assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i); - assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); - assign sclk_a1 = smux_clk_a1; - assign sclk_a2 = smux_clk_a2; - assign sclk_b1 = smux_clk_b1; - assign sclk_b2 = smux_clk_b2; - assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i)); - assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i)); - assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i)); - assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i)); - localparam MODE_36 = 3'b011; - assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4]))); - assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4]))); - assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4])); - assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4])); - assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); - assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); - assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); - assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); - assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3])); - localparam MODE_18 = 3'b010; - localparam MODE_9 = 3'b001; - always @(*) begin : WDATA_SEL - case (SPLIT_i) - 1: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A2_i; - ram_wdata_b1 = WDATA_B1_i; - ram_wdata_b2 = WDATA_B2_i; - ram_be_a2 = BE_A2_i; - ram_be_b2 = BE_B2_i; - ram_be_a1 = BE_A1_i; - ram_be_b1 = BE_B1_i; - end - 0: begin - case (WMODE_A1_i) - MODE_36: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A2_i; - ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i); - ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); - end - MODE_18: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A1_i; - ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i); - ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i); - end - MODE_9: begin - ram_wdata_a1[7:0] = WDATA_A1_i[7:0]; - ram_wdata_a1[16] = WDATA_A1_i[16]; - ram_wdata_a1[15:8] = WDATA_A1_i[7:0]; - ram_wdata_a1[17] = WDATA_A1_i[16]; - ram_wdata_a2[7:0] = WDATA_A1_i[7:0]; - ram_wdata_a2[16] = WDATA_A1_i[16]; - ram_wdata_a2[15:8] = WDATA_A1_i[7:0]; - ram_wdata_a2[17] = WDATA_A1_i[16]; - case (bwl) - 0: {ram_be_a2, ram_be_a1} = 4'b0001; - 1: {ram_be_a2, ram_be_a1} = 4'b0010; - 2: {ram_be_a2, ram_be_a1} = 4'b0100; - 3: {ram_be_a2, ram_be_a1} = 4'b1000; - endcase - end - default: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A1_i; - ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i); - ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); - end - endcase - case (WMODE_B1_i) - MODE_36: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i); - ram_be_b2 = BE_B2_i; - ram_be_b1 = BE_B1_i; - end - MODE_18: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_be_b1 = BE_B1_i; - ram_be_b2 = BE_B1_i; - end - MODE_9: begin - ram_wdata_b1[7:0] = WDATA_B1_i[7:0]; - ram_wdata_b1[16] = WDATA_B1_i[16]; - ram_wdata_b1[15:8] = WDATA_B1_i[7:0]; - ram_wdata_b1[17] = WDATA_B1_i[16]; - ram_wdata_b2[7:0] = WDATA_B1_i[7:0]; - ram_wdata_b2[16] = WDATA_B1_i[16]; - ram_wdata_b2[15:8] = WDATA_B1_i[7:0]; - ram_wdata_b2[17] = WDATA_B1_i[16]; - case (ADDR_B1_i[4:3]) - 0: {ram_be_b2, ram_be_b1} = 4'b0001; - 1: {ram_be_b2, ram_be_b1} = 4'b0010; - 2: {ram_be_b2, ram_be_b1} = 4'b0100; - 3: {ram_be_b2, ram_be_b1} = 4'b1000; - endcase - end - default: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_be_b2 = BE_B1_i; - ram_be_b1 = BE_B1_i; - end - endcase - end - endcase - end - assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); - assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); - assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); - assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); - assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); - assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); - assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); - assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); - always @(*) begin : FIFO_READ_SEL - case (RMODE_B1_i) - MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; - MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1}); - MODE_9: - case (ff_raddr[1:0]) - 0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}; - 1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]}; - 2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]}; - 3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]}; - endcase - default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1}; - endcase - end - localparam MODE_1 = 3'b101; - localparam MODE_2 = 3'b110; - localparam MODE_4 = 3'b100; - always @(*) begin : RDATA_SEL - case (SPLIT_i) - 1: begin - RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1); - RDATA_B1_o = ram_rdata_b1; - RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2); - RDATA_B2_o = ram_rdata_b2; - end - 0: begin - if (FMODE1_i) begin - RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3}; - RDATA_A2_o = 18'b000000000000000000; - end - else - case (RMODE_A1_i) - MODE_36: begin - RDATA_A1_o = {ram_rdata_a1[17:0]}; - RDATA_A2_o = {ram_rdata_a2[17:0]}; - end - MODE_18: begin - RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1); - RDATA_A2_o = 18'b000000000000000000; - end - MODE_9: begin - RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}}); - RDATA_A2_o = 18'b000000000000000000; - end - MODE_4: begin - RDATA_A2_o = 18'b000000000000000000; - RDATA_A1_o[17:4] = 14'b00000000000000; - RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]); - end - MODE_2: begin - RDATA_A2_o = 18'b000000000000000000; - RDATA_A1_o[17:2] = 16'b0000000000000000; - RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]); - end - MODE_1: begin - RDATA_A2_o = 18'b000000000000000000; - RDATA_A1_o[17:1] = 17'b00000000000000000; - RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]); - end - default: begin - RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]}; - RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]}; - end - endcase - case (RMODE_B1_i) - MODE_36: begin - RDATA_B1_o = {ram_rdata_b1}; - RDATA_B2_o = {ram_rdata_b2}; - end - MODE_18: begin - RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1)); - RDATA_B2_o = 18'b000000000000000000; - end - MODE_9: begin - RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]})); - RDATA_B2_o = 18'b000000000000000000; - end - MODE_4: begin - RDATA_B2_o = 18'b000000000000000000; - RDATA_B1_o[17:4] = 14'b00000000000000; - RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]); - end - MODE_2: begin - RDATA_B2_o = 18'b000000000000000000; - RDATA_B1_o[17:2] = 16'b0000000000000000; - RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]); - end - MODE_1: begin - RDATA_B2_o = 18'b000000000000000000; - RDATA_B1_o[17:1] = 17'b00000000000000000; - RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]); - end - default: begin - RDATA_B1_o = ram_rdata_b1; - RDATA_B2_o = ram_rdata_b2; - end - endcase - end - endcase - end - always @(posedge sclk_a1 or negedge sreset) - if (sreset == 0) - laddr_a1 <= 1'sb0; - else - laddr_a1 <= ADDR_A1_i; - always @(posedge sclk_b1 or negedge sreset) - if (sreset == 0) - laddr_b1 <= 1'sb0; - else - laddr_b1 <= ADDR_B1_i; - assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00))); - assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00))); - fifo_ctl #( - .ADDR_WIDTH(12), - .FIFO_WIDTH(3'd4), - .DEPTH(7) - ) fifo36_ctl( - .rclk(sclk_b1), - .rst_R_n(flush1), - .wclk(sclk_a1), - .rst_W_n(flush1), - .ren(REN_B1_i), - .wen(ram_wen_a1), - .sync(SYNC_FIFO1_i), - .rmode(fifo_rmode), - .wmode(fifo_wmode), - .ren_o(ren_o), - .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}), - .raddr(ff_raddr), - .waddr(ff_waddr), - .upaf(UPAF1_i), - .upae(UPAE1_i) - ); - TDP18K_FIFO #( - .UPAF_i(UPAF1_i[10:0]), - .UPAE_i(UPAE1_i[10:0]), - .SYNC_FIFO_i(SYNC_FIFO1_i), - .POWERDN_i(POWERDN1_i), - .SLEEP_i(SLEEP1_i), - .PROTECT_i(PROTECT1_i) - )u1( - .RMODE_A_i(ram_rmode_a1), - .RMODE_B_i(ram_rmode_b1), - .WMODE_A_i(ram_wmode_a1), - .WMODE_B_i(ram_wmode_b1), - .WEN_A_i(ram_wen_a1), - .WEN_B_i(ram_wen_b1), - .REN_A_i(ram_ren_a1), - .REN_B_i(ram_ren_b1), - .CLK_A_i(sclk_a1), - .CLK_B_i(sclk_b1), - .BE_A_i(ram_be_a1), - .BE_B_i(ram_be_b1), - .ADDR_A_i(ram_addr_a1), - .ADDR_B_i(ram_addr_b1), - .WDATA_A_i(ram_wdata_a1), - .WDATA_B_i(ram_wdata_b1), - .RDATA_A_o(ram_rdata_a1), - .RDATA_B_o(ram_rdata_b1), - .EMPTY_o(EMPTY1), - .EPO_o(EPO1), - .EWM_o(EWM1), - .UNDERRUN_o(UNDERRUN1), - .FULL_o(FULL1), - .FMO_o(FMO1), - .FWM_o(FWM1), - .OVERRUN_o(OVERRUN1), - .FLUSH_ni(flush1), - .FMODE_i(ram_fmode1) - ); - TDP18K_FIFO #( - .UPAF_i(UPAF2_i), - .UPAE_i(UPAE2_i), - .SYNC_FIFO_i(SYNC_FIFO2_i), - .POWERDN_i(POWERDN2_i), - .SLEEP_i(SLEEP2_i), - .PROTECT_i(PROTECT2_i) - )u2( - .RMODE_A_i(ram_rmode_a2), - .RMODE_B_i(ram_rmode_b2), - .WMODE_A_i(ram_wmode_a2), - .WMODE_B_i(ram_wmode_b2), - .WEN_A_i(ram_wen_a2), - .WEN_B_i(ram_wen_b2), - .REN_A_i(ram_ren_a2), - .REN_B_i(ram_ren_b2), - .CLK_A_i(sclk_a2), - .CLK_B_i(sclk_b2), - .BE_A_i(ram_be_a2), - .BE_B_i(ram_be_b2), - .ADDR_A_i(ram_addr_a2), - .ADDR_B_i(ram_addr_b2), - .WDATA_A_i(ram_wdata_a2), - .WDATA_B_i(ram_wdata_b2), - .RDATA_A_o(ram_rdata_a2), - .RDATA_B_o(ram_rdata_b2), - .EMPTY_o(EMPTY2), - .EPO_o(EPO2), - .EWM_o(EWM2), - .UNDERRUN_o(UNDERRUN2), - .FULL_o(FULL2), - .FMO_o(FMO2), - .FWM_o(FWM2), - .OVERRUN_o(OVERRUN2), - .FLUSH_ni(flush2), - .FMODE_i(ram_fmode2) - ); + parameter [80:0] MODE_BITS = 81'd0; + + // First 18K RAMFIFO (41 bits) + localparam [ 0:0] SYNC_FIFO1_i = MODE_BITS[0]; + localparam [ 2:0] RMODE_A1_i = MODE_BITS[3 : 1]; + localparam [ 2:0] RMODE_B1_i = MODE_BITS[6 : 4]; + localparam [ 2:0] WMODE_A1_i = MODE_BITS[9 : 7]; + localparam [ 2:0] WMODE_B1_i = MODE_BITS[12:10]; + localparam [ 0:0] FMODE1_i = MODE_BITS[13]; + localparam [ 0:0] POWERDN1_i = MODE_BITS[14]; + localparam [ 0:0] SLEEP1_i = MODE_BITS[15]; + localparam [ 0:0] PROTECT1_i = MODE_BITS[16]; + localparam [11:0] UPAE1_i = MODE_BITS[28:17]; + localparam [11:0] UPAF1_i = MODE_BITS[40:29]; + + // Second 18K RAMFIFO (39 bits) + localparam [ 0:0] SYNC_FIFO2_i = MODE_BITS[41]; + localparam [ 2:0] RMODE_A2_i = MODE_BITS[44:42]; + localparam [ 2:0] RMODE_B2_i = MODE_BITS[47:45]; + localparam [ 2:0] WMODE_A2_i = MODE_BITS[50:48]; + localparam [ 2:0] WMODE_B2_i = MODE_BITS[53:51]; + localparam [ 0:0] FMODE2_i = MODE_BITS[54]; + localparam [ 0:0] POWERDN2_i = MODE_BITS[55]; + localparam [ 0:0] SLEEP2_i = MODE_BITS[56]; + localparam [ 0:0] PROTECT2_i = MODE_BITS[57]; + localparam [10:0] UPAE2_i = MODE_BITS[68:58]; + localparam [10:0] UPAF2_i = MODE_BITS[79:69]; + + // Split (1 bit) + localparam [ 0:0] SPLIT_i = MODE_BITS[80]; + + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + input wire RESET_ni; + input wire WEN_A1_i; + input wire WEN_B1_i; + input wire REN_A1_i; + input wire REN_B1_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + input wire [1:0] BE_A1_i; + input wire [1:0] BE_B1_i; + input wire [14:0] ADDR_A1_i; + input wire [14:0] ADDR_B1_i; + input wire [17:0] WDATA_A1_i; + input wire [17:0] WDATA_B1_i; + output reg [17:0] RDATA_A1_o; + output reg [17:0] RDATA_B1_o; + input wire FLUSH1_i; + input wire WEN_A2_i; + input wire WEN_B2_i; + input wire REN_A2_i; + input wire REN_B2_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + input wire [1:0] BE_A2_i; + input wire [1:0] BE_B2_i; + input wire [13:0] ADDR_A2_i; + input wire [13:0] ADDR_B2_i; + input wire [17:0] WDATA_A2_i; + input wire [17:0] WDATA_B2_i; + output reg [17:0] RDATA_A2_o; + output reg [17:0] RDATA_B2_o; + input wire FLUSH2_i; + wire EMPTY2; + wire EPO2; + wire EWM2; + wire FULL2; + wire FMO2; + wire FWM2; + wire EMPTY1; + wire EPO1; + wire EWM1; + wire FULL1; + wire FMO1; + wire FWM1; + wire UNDERRUN1; + wire OVERRUN1; + wire UNDERRUN2; + wire OVERRUN2; + wire UNDERRUN3; + wire OVERRUN3; + wire EMPTY3; + wire EPO3; + wire EWM3; + wire FULL3; + wire FMO3; + wire FWM3; + wire ram_fmode1; + wire ram_fmode2; + wire [17:0] ram_rdata_a1; + wire [17:0] ram_rdata_b1; + wire [17:0] ram_rdata_a2; + wire [17:0] ram_rdata_b2; + reg [17:0] ram_wdata_a1; + reg [17:0] ram_wdata_b1; + reg [17:0] ram_wdata_a2; + reg [17:0] ram_wdata_b2; + reg [14:0] laddr_a1; + reg [14:0] laddr_b1; + wire [13:0] ram_addr_a1; + wire [13:0] ram_addr_b1; + wire [13:0] ram_addr_a2; + wire [13:0] ram_addr_b2; + wire smux_clk_a1; + wire smux_clk_b1; + wire smux_clk_a2; + wire smux_clk_b2; + reg [1:0] ram_be_a1; + reg [1:0] ram_be_a2; + reg [1:0] ram_be_b1; + reg [1:0] ram_be_b2; + wire [2:0] ram_rmode_a1; + wire [2:0] ram_wmode_a1; + wire [2:0] ram_rmode_b1; + wire [2:0] ram_wmode_b1; + wire [2:0] ram_rmode_a2; + wire [2:0] ram_wmode_a2; + wire [2:0] ram_rmode_b2; + wire [2:0] ram_wmode_b2; + wire ram_ren_a1; + wire ram_ren_b1; + wire ram_ren_a2; + wire ram_ren_b2; + wire ram_wen_a1; + wire ram_wen_b1; + wire ram_wen_a2; + wire ram_wen_b2; + wire ren_o; + wire [11:0] ff_raddr; + wire [11:0] ff_waddr; + reg [35:0] fifo_rdata; + wire [1:0] fifo_rmode; + wire [1:0] fifo_wmode; + wire [1:0] bwl; + wire [17:0] pl_dout0; + wire [17:0] pl_dout1; + wire sclk_a1; + wire sclk_b1; + wire sclk_a2; + wire sclk_b2; + wire sreset; + wire flush1; + wire flush2; + assign sreset = RESET_ni; + assign flush1 = ~FLUSH1_i; + assign flush2 = ~FLUSH2_i; + assign ram_fmode1 = FMODE1_i & SPLIT_i; + assign ram_fmode2 = FMODE2_i & SPLIT_i; + assign smux_clk_a1 = CLK_A1_i; + assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i); + assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i); + assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); + assign sclk_a1 = smux_clk_a1; + assign sclk_a2 = smux_clk_a2; + assign sclk_b1 = smux_clk_b1; + assign sclk_b2 = smux_clk_b2; + assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i)); + assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i)); + localparam MODE_36 = 3'b011; + assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4]))); + assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4]))); + assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4])); + assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4])); + assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3])); + localparam MODE_18 = 3'b010; + localparam MODE_9 = 3'b001; + always @(*) begin : WDATA_SEL + case (SPLIT_i) + 1: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_wdata_b1 = WDATA_B1_i; + ram_wdata_b2 = WDATA_B2_i; + ram_be_a2 = BE_A2_i; + ram_be_b2 = BE_B2_i; + ram_be_a1 = BE_A1_i; + ram_be_b1 = BE_B1_i; + end + 0: begin + case (WMODE_A1_i) + MODE_36: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + MODE_18: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i); + ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i); + end + MODE_9: begin + ram_wdata_a1[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a1[16] = WDATA_A1_i[16]; + ram_wdata_a1[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a1[17] = WDATA_A1_i[16]; + ram_wdata_a2[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a2[16] = WDATA_A1_i[16]; + ram_wdata_a2[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a2[17] = WDATA_A1_i[16]; + case (bwl) + 0: {ram_be_a2, ram_be_a1} = 4'b0001; + 1: {ram_be_a2, ram_be_a1} = 4'b0010; + 2: {ram_be_a2, ram_be_a1} = 4'b0100; + 3: {ram_be_a2, ram_be_a1} = 4'b1000; + endcase + end + default: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + endcase + case (WMODE_B1_i) + MODE_36: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i); + ram_be_b2 = BE_B2_i; + ram_be_b1 = BE_B1_i; + end + MODE_18: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b1 = BE_B1_i; + ram_be_b2 = BE_B1_i; + end + MODE_9: begin + ram_wdata_b1[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b1[16] = WDATA_B1_i[16]; + ram_wdata_b1[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b1[17] = WDATA_B1_i[16]; + ram_wdata_b2[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b2[16] = WDATA_B1_i[16]; + ram_wdata_b2[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b2[17] = WDATA_B1_i[16]; + case (ADDR_B1_i[4:3]) + 0: {ram_be_b2, ram_be_b1} = 4'b0001; + 1: {ram_be_b2, ram_be_b1} = 4'b0010; + 2: {ram_be_b2, ram_be_b1} = 4'b0100; + 3: {ram_be_b2, ram_be_b1} = 4'b1000; + endcase + end + default: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b2 = BE_B1_i; + ram_be_b1 = BE_B1_i; + end + endcase + end + endcase + end + assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + always @(*) begin : FIFO_READ_SEL + case (RMODE_B1_i) + MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; + MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1}); + MODE_9: + case (ff_raddr[1:0]) + 0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}; + 1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]}; + 2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]}; + 3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]}; + endcase + default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1}; + endcase + end + localparam MODE_1 = 3'b101; + localparam MODE_2 = 3'b110; + localparam MODE_4 = 3'b100; + always @(*) begin : RDATA_SEL + case (SPLIT_i) + 1: begin + RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1); + RDATA_B1_o = ram_rdata_b1; + RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2); + RDATA_B2_o = ram_rdata_b2; + end + 0: begin + if (FMODE1_i) begin + RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3}; + RDATA_A2_o = 18'b000000000000000000; + end + else + case (RMODE_A1_i) + MODE_36: begin + RDATA_A1_o = {ram_rdata_a1[17:0]}; + RDATA_A2_o = {ram_rdata_a2[17:0]}; + end + MODE_18: begin + RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}}); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:4] = 14'b00000000000000; + RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]); + end + MODE_2: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:2] = 16'b0000000000000000; + RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]); + end + MODE_1: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:1] = 17'b00000000000000000; + RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]); + end + default: begin + RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]}; + RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]}; + end + endcase + case (RMODE_B1_i) + MODE_36: begin + RDATA_B1_o = {ram_rdata_b1}; + RDATA_B2_o = {ram_rdata_b2}; + end + MODE_18: begin + RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1)); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]})); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:4] = 14'b00000000000000; + RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]); + end + MODE_2: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:2] = 16'b0000000000000000; + RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]); + end + MODE_1: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:1] = 17'b00000000000000000; + RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]); + end + default: begin + RDATA_B1_o = ram_rdata_b1; + RDATA_B2_o = ram_rdata_b2; + end + endcase + end + endcase + end + always @(posedge sclk_a1 or negedge sreset) + if (sreset == 0) + laddr_a1 <= 1'sb0; + else + laddr_a1 <= ADDR_A1_i; + always @(posedge sclk_b1 or negedge sreset) + if (sreset == 0) + laddr_b1 <= 1'sb0; + else + laddr_b1 <= ADDR_B1_i; + assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00))); + assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00))); + fifo_ctl #( + .ADDR_WIDTH(12), + .FIFO_WIDTH(3'd4), + .DEPTH(7) + ) fifo36_ctl( + .rclk(sclk_b1), + .rst_R_n(flush1), + .wclk(sclk_a1), + .rst_W_n(flush1), + .ren(REN_B1_i), + .wen(ram_wen_a1), + .sync(SYNC_FIFO1_i), + .rmode(fifo_rmode), + .wmode(fifo_wmode), + .ren_o(ren_o), + .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}), + .raddr(ff_raddr), + .waddr(ff_waddr), + .upaf(UPAF1_i), + .upae(UPAE1_i) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF1_i[10:0]), + .UPAE_i(UPAE1_i[10:0]), + .SYNC_FIFO_i(SYNC_FIFO1_i), + .POWERDN_i(POWERDN1_i), + .SLEEP_i(SLEEP1_i), + .PROTECT_i(PROTECT1_i) + )u1( + .RMODE_A_i(ram_rmode_a1), + .RMODE_B_i(ram_rmode_b1), + .WMODE_A_i(ram_wmode_a1), + .WMODE_B_i(ram_wmode_b1), + .WEN_A_i(ram_wen_a1), + .WEN_B_i(ram_wen_b1), + .REN_A_i(ram_ren_a1), + .REN_B_i(ram_ren_b1), + .CLK_A_i(sclk_a1), + .CLK_B_i(sclk_b1), + .BE_A_i(ram_be_a1), + .BE_B_i(ram_be_b1), + .ADDR_A_i(ram_addr_a1), + .ADDR_B_i(ram_addr_b1), + .WDATA_A_i(ram_wdata_a1), + .WDATA_B_i(ram_wdata_b1), + .RDATA_A_o(ram_rdata_a1), + .RDATA_B_o(ram_rdata_b1), + .EMPTY_o(EMPTY1), + .EPO_o(EPO1), + .EWM_o(EWM1), + .UNDERRUN_o(UNDERRUN1), + .FULL_o(FULL1), + .FMO_o(FMO1), + .FWM_o(FWM1), + .OVERRUN_o(OVERRUN1), + .FLUSH_ni(flush1), + .FMODE_i(ram_fmode1) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF2_i), + .UPAE_i(UPAE2_i), + .SYNC_FIFO_i(SYNC_FIFO2_i), + .POWERDN_i(POWERDN2_i), + .SLEEP_i(SLEEP2_i), + .PROTECT_i(PROTECT2_i) + )u2( + .RMODE_A_i(ram_rmode_a2), + .RMODE_B_i(ram_rmode_b2), + .WMODE_A_i(ram_wmode_a2), + .WMODE_B_i(ram_wmode_b2), + .WEN_A_i(ram_wen_a2), + .WEN_B_i(ram_wen_b2), + .REN_A_i(ram_ren_a2), + .REN_B_i(ram_ren_b2), + .CLK_A_i(sclk_a2), + .CLK_B_i(sclk_b2), + .BE_A_i(ram_be_a2), + .BE_B_i(ram_be_b2), + .ADDR_A_i(ram_addr_a2), + .ADDR_B_i(ram_addr_b2), + .WDATA_A_i(ram_wdata_a2), + .WDATA_B_i(ram_wdata_b2), + .RDATA_A_o(ram_rdata_a2), + .RDATA_B_o(ram_rdata_b2), + .EMPTY_o(EMPTY2), + .EPO_o(EPO2), + .EWM_o(EWM2), + .UNDERRUN_o(UNDERRUN2), + .FULL_o(FULL2), + .FMO_o(FMO2), + .FWM_o(FWM2), + .OVERRUN_o(OVERRUN2), + .FLUSH_ni(flush2), + .FMODE_i(ram_fmode2) + ); endmodule module RAM_18K_X2_BLK ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o ); parameter WR1_ADDR_WIDTH = 10; @@ -810,10 +810,10 @@ wire [17:0] PORT_B2_RDATA; wire [17:0] PORT_A2_WDATA; wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -834,12 +834,12 @@ localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end endgenerate case (WR1_DATA_WIDTH) @@ -864,12 +864,12 @@ case (WR1_DATA_WIDTH) endcase generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end endgenerate case (RD1_DATA_WIDTH) @@ -894,12 +894,12 @@ case (RD1_DATA_WIDTH) endcase generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end endgenerate case (WR2_DATA_WIDTH) @@ -924,12 +924,12 @@ case (WR2_DATA_WIDTH) endcase generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end endgenerate case (RD2_DATA_WIDTH) @@ -982,55 +982,55 @@ assign BE_A2_i = WR2_BE; assign REN_B1_i = REN1_i; assign WEN_B1_i = 1'b0; -assign BE_B1_i = 4'h0; +assign BE_B1_i = 2'h0; assign REN_B2_i = REN2_i; assign WEN_B2_i = 1'b0; -assign BE_B2_i = 4'h0; +assign BE_B2_i = 2'h0; generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA[17:0]; assign WDATA_B1_i = 18'h0; generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA[17:0]; assign WDATA_B2_i = 18'h0; generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; @@ -1088,27 +1088,27 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module BRAM2x18_SP ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o ); parameter WR1_ADDR_WIDTH = 10; @@ -1222,10 +1222,10 @@ wire [17:0] PORT_B2_RDATA; wire [17:0] PORT_A2_WDATA; wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -1246,12 +1246,12 @@ localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end endgenerate case (WR1_DATA_WIDTH) @@ -1276,12 +1276,12 @@ case (WR1_DATA_WIDTH) endcase generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end endgenerate case (RD1_DATA_WIDTH) @@ -1306,12 +1306,12 @@ case (RD1_DATA_WIDTH) endcase generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end endgenerate case (WR2_DATA_WIDTH) @@ -1336,12 +1336,12 @@ case (WR2_DATA_WIDTH) endcase generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end endgenerate case (RD2_DATA_WIDTH) @@ -1394,55 +1394,55 @@ assign BE_A2_i = WR2_BE; assign REN_B1_i = REN1_i; assign WEN_B1_i = 1'b0; -assign BE_B1_i = 4'h0; +assign BE_B1_i = 2'h0; assign REN_B2_i = REN2_i; assign WEN_B2_i = 1'b0; -assign BE_B2_i = 4'h0; +assign BE_B2_i = 2'h0; generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA[17:0]; assign WDATA_B1_i = 18'h0; generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA[17:0]; assign WDATA_B2_i = 18'h0; generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; @@ -1498,15 +1498,15 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module RAM_18K_BLK ( - WEN_i, - REN_i, - WR_CLK_i, - RD_CLK_i, - WR_BE_i, - WR_ADDR_i, - RD_ADDR_i, - WDATA_i, - RDATA_o + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o ); parameter WR_ADDR_WIDTH = 10; @@ -1525,56 +1525,56 @@ input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; input wire [WR_DATA_WIDTH-1 :0] WDATA_i; output wire [RD_DATA_WIDTH-1 :0] RDATA_o; - (* is_inferred = 0 *) - (* is_split = 0 *) - BRAM2x18_SP #( - .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), - .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .BE1_WIDTH(BE_WIDTH), - .WR2_ADDR_WIDTH(), - .RD2_ADDR_WIDTH(), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .BE2_WIDTH() - ) U1 - ( - .RESET_ni(1'b1), - - .WEN1_i(WEN_i), - .REN1_i(REN_i), - .WR1_CLK_i(WR_CLK_i), - .RD1_CLK_i(RD_CLK_i), - .WR1_BE_i(WR_BE_i), - .WR1_ADDR_i(WR_ADDR_i), - .RD1_ADDR_i(RD_ADDR_i), - .WDATA1_i(WDATA_i), - .RDATA1_o(RDATA_o), - - .WEN2_i(1'b0), - .REN2_i(1'b0), - .WR2_CLK_i(1'b0), - .RD2_CLK_i(1'b0), - .WR2_BE_i(2'b00), - .WR2_ADDR_i(14'h0), - .RD2_ADDR_i(14'h0), - .WDATA2_i(18'h0), - .RDATA2_o() - ); - + (* is_inferred = 0 *) + (* is_split = 0 *) + BRAM2x18_SP #( + .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), + .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .BE1_WIDTH(BE_WIDTH), + .WR2_ADDR_WIDTH(), + .RD2_ADDR_WIDTH(), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .BE2_WIDTH() + ) U1 + ( + .RESET_ni(1'b1), + + .WEN1_i(WEN_i), + .REN1_i(REN_i), + .WR1_CLK_i(WR_CLK_i), + .RD1_CLK_i(RD_CLK_i), + .WR1_BE_i(WR_BE_i), + .WR1_ADDR_i(WR_ADDR_i), + .RD1_ADDR_i(RD_ADDR_i), + .WDATA1_i(WDATA_i), + .RDATA1_o(RDATA_o), + + .WEN2_i(1'b0), + .REN2_i(1'b0), + .WR2_CLK_i(1'b0), + .RD2_CLK_i(1'b0), + .WR2_BE_i(2'b00), + .WR2_ADDR_i(14'h0), + .RD2_ADDR_i(14'h0), + .WDATA2_i(18'h0), + .RDATA2_o() + ); + endmodule module RAM_36K_BLK ( - WEN_i, - REN_i, - WR_CLK_i, - RD_CLK_i, - WR_BE_i, - WR_ADDR_i, - RD_ADDR_i, - WDATA_i, - RDATA_o + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o ); parameter WR_ADDR_WIDTH = 10; @@ -1668,7 +1668,7 @@ wire [35:0] PORT_B_RDATA; wire [35:0] PORT_A_WDATA; wire [14:0] WR_ADDR_INT; -wire [14:0] RD_ADDR_INT; +wire [14:0] RD_ADDR_INT; wire [14:0] PORT_A_ADDR; wire [14:0] PORT_B_ADDR; @@ -1691,12 +1691,12 @@ assign PORT_A_CLK = WR_CLK_i; assign PORT_B_CLK = RD_CLK_i; generate - if (WR_ADDR_WIDTH == 15) begin - assign WR_ADDR_INT = WR_ADDR_i; - end else begin - assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; - assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; - end + if (WR_ADDR_WIDTH == 15) begin + assign WR_ADDR_INT = WR_ADDR_i; + end else begin + assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; + assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; + end endgenerate case (WR_DATA_WIDTH) @@ -1724,12 +1724,12 @@ case (WR_DATA_WIDTH) endcase generate - if (RD_ADDR_WIDTH == 15) begin - assign RD_ADDR_INT = RD_ADDR_i; - end else begin - assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; - assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; - end + if (RD_ADDR_WIDTH == 15) begin + assign RD_ADDR_INT = RD_ADDR_i; + end else begin + assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; + assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; + end endgenerate case (RD_DATA_WIDTH) @@ -1775,17 +1775,17 @@ assign WEN_B1_i = 1'b0; assign {BE_B2_i, BE_B1_i} = 4'h0; generate - if (WR_DATA_WIDTH == 36) begin - assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; - assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; - end else begin - assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; - assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; - end + if (WR_DATA_WIDTH == 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A_WDATA[17:0]; @@ -1795,15 +1795,15 @@ assign WDATA_B1_i = 18'h0; assign WDATA_B2_i = 18'h0; generate - if (RD_DATA_WIDTH == 36) begin - assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; - end + if (RD_DATA_WIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end endgenerate assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0]; @@ -1859,44 +1859,44 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module DPRAM_18K_X2_BLK ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o +module DPRAM_18K_X2_BLK ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o ); parameter PORT_A1_AWIDTH = 10; parameter PORT_A1_DWIDTH = 18; parameter PORT_A1_WR_BE_WIDTH = 2; - + parameter PORT_B1_AWIDTH = 10; parameter PORT_B1_DWIDTH = 18; parameter PORT_B1_WR_BE_WIDTH = 2; @@ -1904,7 +1904,7 @@ parameter PORT_B1_WR_BE_WIDTH = 2; parameter PORT_A2_AWIDTH = 10; parameter PORT_A2_DWIDTH = 18; parameter PORT_A2_WR_BE_WIDTH = 2; - + parameter PORT_B2_AWIDTH = 10; parameter PORT_B2_DWIDTH = 18; parameter PORT_B2_WR_BE_WIDTH = 2; @@ -2027,11 +2027,11 @@ wire [17:0] PORT_A2_WDATA; wire [17:0] PORT_A2_RDATA; wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - +wire [13:0] PORT_B2_ADDR_INT; + wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -2062,12 +2062,12 @@ assign PORT_A2_CLK = PORT_A2_CLK_i; assign PORT_B2_CLK = PORT_B2_CLK_i; generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end endgenerate case (PORT_A1_DWIDTH) @@ -2092,12 +2092,12 @@ case (PORT_A1_DWIDTH) endcase generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end endgenerate case (PORT_B1_DWIDTH) @@ -2122,12 +2122,12 @@ case (PORT_B1_DWIDTH) endcase generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end endgenerate case (PORT_A2_DWIDTH) @@ -2152,12 +2152,12 @@ case (PORT_A2_DWIDTH) endcase generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end endgenerate case (PORT_B2_DWIDTH) @@ -2238,93 +2238,93 @@ assign WEN_B2_i = PORT_B2_WEN_i; assign BE_B2_i = PORT_B2_WR_BE; generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA; generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA; generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end endgenerate assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end endgenerate assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B1_WDATA; generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end endgenerate assign WDATA_B2_i = PORT_B2_WDATA; generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; @@ -2381,44 +2381,44 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module BRAM2x18_dP ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o ); parameter PORT_A1_AWIDTH = 10; parameter PORT_A1_DWIDTH = 18; parameter PORT_A1_WR_BE_WIDTH = 2; - + parameter PORT_B1_AWIDTH = 10; parameter PORT_B1_DWIDTH = 18; parameter PORT_B1_WR_BE_WIDTH = 2; @@ -2426,7 +2426,7 @@ parameter PORT_B1_WR_BE_WIDTH = 2; parameter PORT_A2_AWIDTH = 10; parameter PORT_A2_DWIDTH = 18; parameter PORT_A2_WR_BE_WIDTH = 2; - + parameter PORT_B2_AWIDTH = 10; parameter PORT_B2_DWIDTH = 18; parameter PORT_B2_WR_BE_WIDTH = 2; @@ -2548,11 +2548,11 @@ wire [17:0] PORT_A2_WDATA; wire [17:0] PORT_A2_RDATA; wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - +wire [13:0] PORT_B2_ADDR_INT; + wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -2583,12 +2583,12 @@ assign PORT_A2_CLK = PORT_A2_CLK_i; assign PORT_B2_CLK = PORT_B2_CLK_i; generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end endgenerate case (PORT_A1_DWIDTH) @@ -2613,12 +2613,12 @@ case (PORT_A1_DWIDTH) endcase generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end endgenerate case (PORT_B1_DWIDTH) @@ -2643,12 +2643,12 @@ case (PORT_B1_DWIDTH) endcase generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end endgenerate case (PORT_A2_DWIDTH) @@ -2673,12 +2673,12 @@ case (PORT_A2_DWIDTH) endcase generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end endgenerate case (PORT_B2_DWIDTH) @@ -2759,93 +2759,93 @@ assign WEN_B2_i = PORT_B2_WEN_i; assign BE_B2_i = PORT_B2_WR_BE; generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA; generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA; generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end endgenerate assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end endgenerate assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B1_WDATA; generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end endgenerate assign WDATA_B2_i = PORT_B2_WDATA; generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; @@ -2900,22 +2900,22 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module DPRAM_18K_BLK ( - PORT_A_CLK_i, - PORT_A_WEN_i, - PORT_A_WR_BE_i, - PORT_A_REN_i, - PORT_A_ADDR_i, - PORT_A_WR_DATA_i, - PORT_A_RD_DATA_o, - - PORT_B_CLK_i, - PORT_B_WEN_i, - PORT_B_WR_BE_i, - PORT_B_REN_i, - PORT_B_ADDR_i, - PORT_B_WR_DATA_i, - PORT_B_RD_DATA_o +module DPRAM_18K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o ); parameter PORT_A_AWIDTH = 10; @@ -2959,57 +2959,57 @@ BRAM2x18_dP #( .PORT_B2_DWIDTH(), .PORT_B2_WR_BE_WIDTH() ) U1 ( - .PORT_A1_CLK_i(PORT_A_CLK_i), - .PORT_A1_WEN_i(PORT_A_WEN_i), - .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), - .PORT_A1_REN_i(PORT_A_REN_i), - .PORT_A1_ADDR_i(PORT_A_ADDR_i), - .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), - .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), - - .PORT_B1_CLK_i(PORT_B_CLK_i), - .PORT_B1_WEN_i(PORT_B_WEN_i), - .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), - .PORT_B1_REN_i(PORT_B_REN_i), - .PORT_B1_ADDR_i(PORT_B_ADDR_i), - .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), - .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), - - .PORT_A2_CLK_i(1'b0), - .PORT_A2_WEN_i(1'b0), - .PORT_A2_WR_BE_i(2'b00), - .PORT_A2_REN_i(1'b0), - .PORT_A2_ADDR_i(14'h0), - .PORT_A2_WR_DATA_i(18'h0), - .PORT_A2_RD_DATA_o(), - - .PORT_B2_CLK_i(1'b0), - .PORT_B2_WEN_i(1'b0), - .PORT_B2_WR_BE_i(2'b00), - .PORT_B2_REN_i(1'b0), - .PORT_B2_ADDR_i(14'h0), - .PORT_B2_WR_DATA_i(18'h0), - .PORT_B2_RD_DATA_o() + .PORT_A1_CLK_i(PORT_A_CLK_i), + .PORT_A1_WEN_i(PORT_A_WEN_i), + .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), + .PORT_A1_REN_i(PORT_A_REN_i), + .PORT_A1_ADDR_i(PORT_A_ADDR_i), + .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), + .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), + + .PORT_B1_CLK_i(PORT_B_CLK_i), + .PORT_B1_WEN_i(PORT_B_WEN_i), + .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), + .PORT_B1_REN_i(PORT_B_REN_i), + .PORT_B1_ADDR_i(PORT_B_ADDR_i), + .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), + .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), + + .PORT_A2_CLK_i(1'b0), + .PORT_A2_WEN_i(1'b0), + .PORT_A2_WR_BE_i(2'b00), + .PORT_A2_REN_i(1'b0), + .PORT_A2_ADDR_i(14'h0), + .PORT_A2_WR_DATA_i(18'h0), + .PORT_A2_RD_DATA_o(), + + .PORT_B2_CLK_i(1'b0), + .PORT_B2_WEN_i(1'b0), + .PORT_B2_WR_BE_i(2'b00), + .PORT_B2_REN_i(1'b0), + .PORT_B2_ADDR_i(14'h0), + .PORT_B2_WR_DATA_i(18'h0), + .PORT_B2_RD_DATA_o() ); endmodule -module DPRAM_36K_BLK ( - PORT_A_CLK_i, - PORT_A_WEN_i, - PORT_A_WR_BE_i, - PORT_A_REN_i, - PORT_A_ADDR_i, - PORT_A_WR_DATA_i, - PORT_A_RD_DATA_o, - - PORT_B_CLK_i, - PORT_B_WEN_i, - PORT_B_WR_BE_i, - PORT_B_REN_i, - PORT_B_ADDR_i, - PORT_B_WR_DATA_i, - PORT_B_RD_DATA_o +module DPRAM_36K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o ); parameter PORT_A_AWIDTH = 10; @@ -3113,7 +3113,7 @@ wire [35:0] PORT_A_WDATA; wire [35:0] PORT_A_RDATA; wire [14:0] PORT_A_ADDR_INT; -wire [14:0] PORT_B_ADDR_INT; +wire [14:0] PORT_B_ADDR_INT; wire [14:0] PORT_A_ADDR; wire [14:0] PORT_B_ADDR; @@ -3136,12 +3136,12 @@ assign PORT_A_CLK = PORT_A_CLK_i; assign PORT_B_CLK = PORT_B_CLK_i; generate - if (PORT_A_AWIDTH == 15) begin - assign PORT_A_ADDR_INT = PORT_A_ADDR_i; - end else begin - assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; - assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; - end + if (PORT_A_AWIDTH == 15) begin + assign PORT_A_ADDR_INT = PORT_A_ADDR_i; + end else begin + assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; + assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; + end endgenerate case (PORT_A_DWIDTH) @@ -3169,12 +3169,12 @@ case (PORT_A_DWIDTH) endcase generate - if (PORT_B_AWIDTH == 15) begin - assign PORT_B_ADDR_INT = PORT_B_ADDR_i; - end else begin - assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; - assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; - end + if (PORT_B_AWIDTH == 15) begin + assign PORT_B_ADDR_INT = PORT_B_ADDR_i; + end else begin + assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; + assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; + end endgenerate case (PORT_B_DWIDTH) @@ -3230,63 +3230,63 @@ assign WEN_B1_i = PORT_B_WEN_i; assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; generate - if (PORT_A_DWIDTH == 36) begin - assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; - end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin - assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; - assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; - end else if (PORT_A_DWIDTH == 9) begin - assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; - end else begin - assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; - assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; - end + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A_WDATA[17:0]; assign WDATA_A2_i = PORT_A_WDATA[35:18]; generate - if (PORT_A_DWIDTH == 36) begin - assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; - end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin - assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; - end else if (PORT_A_DWIDTH == 9) begin - assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; - end + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; + end endgenerate assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0]; generate - if (PORT_B_DWIDTH == 36) begin - assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; - end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin - assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; - assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; - end else if (PORT_B_DWIDTH == 9) begin - assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; - end else begin - assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; - assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; - end + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; + assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; + end else begin + assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B_WDATA[17:0]; assign WDATA_B2_i = PORT_B_WDATA[35:18]; generate - if (PORT_B_DWIDTH == 36) begin - assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; - end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin - assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; - end else if (PORT_B_DWIDTH == 9) begin - assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; - end + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end endgenerate assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0]; @@ -3342,192 +3342,192 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module BRAM2x18_SFIFO ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input wire CLK1; - input wire PUSH1, POP1; - input wire [WR1_DATA_WIDTH-1:0] DIN1; - input wire Async_Flush1; - output wire [RD1_DATA_WIDTH-1:0] DOUT1; - output wire Almost_Full1, Almost_Empty1; - output wire Full1, Empty1; - output wire Full_Watermark1, Empty_Watermark1; - output wire Overrun_Error1, Underrun_Error1; - - input wire CLK2; - input wire PUSH2, POP2; - input wire [WR2_DATA_WIDTH-1:0] DIN2; - input wire Async_Flush2; - output wire [RD2_DATA_WIDTH-1:0] DOUT2; - output wire Almost_Full2, Almost_Empty2; - output wire Full2, Empty2; - output wire Full_Watermark2, Empty_Watermark2; - output wire Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire CLK1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire CLK2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = WR1_DATA_WIDTH *) - (* port_b_dwidth = RD1_DATA_WIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = WR1_DATA_WIDTH *) + (* port_b_dwidth = RD1_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -3567,270 +3567,270 @@ module BRAM2x18_SFIFO ( endmodule module SFIFO_18K_BLK ( - DIN, - PUSH, - POP, - CLK, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - - parameter WR_DATA_WIDTH = 18; - parameter RD_DATA_WIDTH = 18; - parameter UPAE_DBITS = 11'd10; - parameter UPAF_DBITS = 11'd10; - - input wire CLK; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + BRAM2x18_SFIFO #( - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .UPAE_DBITS1(UPAE_DBITS), - .UPAF_DBITS1(UPAF_DBITS), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .UPAE_DBITS2(), - .UPAF_DBITS2() - ) U1 - ( - .DIN1(DIN), - .PUSH1(PUSH), - .POP1(POP), - .CLK1(CLK), - .Async_Flush1(Async_Flush), - .Overrun_Error1(Overrun_Error), - .Full_Watermark1(Full_Watermark), - .Almost_Full1(Almost_Full), - .Full1(Full), - .Underrun_Error1(Underrun_Error), - .Empty_Watermark1(Empty_Watermark), - .Almost_Empty1(Almost_Empty), - .Empty1(Empty), - .DOUT1(DOUT), - - .DIN2(18'h0), - .PUSH2(1'b0), - .POP2(1'b0), - .CLK2(1'b0), - .Async_Flush2(1'b0), - .Overrun_Error2(), - .Full_Watermark2(), - .Almost_Full2(), - .Full2(), - .Underrun_Error2(), - .Empty_Watermark2(), - .Almost_Empty2(), - .Empty2(), - .DOUT2() + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .CLK1(CLK), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .CLK2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() ); endmodule module SFIFO_18K_X2_BLK ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input wire CLK1; - input wire PUSH1, POP1; - input wire [WR1_DATA_WIDTH-1:0] DIN1; - input wire Async_Flush1; - output wire [RD1_DATA_WIDTH-1:0] DOUT1; - output wire Almost_Full1, Almost_Empty1; - output wire Full1, Empty1; - output wire Full_Watermark1, Empty_Watermark1; - output wire Overrun_Error1, Underrun_Error1; - - input wire CLK2; - input wire PUSH2, POP2; - input wire [WR2_DATA_WIDTH-1:0] DIN2; - input wire Async_Flush2; - output wire [RD2_DATA_WIDTH-1:0] DOUT2; - output wire Almost_Full2, Almost_Empty2; - output wire Full2, Empty2; - output wire Full_Watermark2, Empty_Watermark2; - output wire Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire CLK1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire CLK2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 1 *) - (* is_inferred = 0 *) - (* port_a1_dwidth = WR1_DATA_WIDTH *) - (* port_a2_dwidth = WR2_DATA_WIDTH *) - (* port_b1_dwidth = RD1_DATA_WIDTH *) - (* port_b2_dwidth = RD2_DATA_WIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = WR1_DATA_WIDTH *) + (* port_a2_dwidth = WR2_DATA_WIDTH *) + (* port_b1_dwidth = RD1_DATA_WIDTH *) + (* port_b2_dwidth = RD2_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -3871,187 +3871,187 @@ endmodule module BRAM2x18_AFIFO ( - DIN1, - PUSH1, - POP1, - Push_Clk1, + DIN1, + PUSH1, + POP1, + Push_Clk1, Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input wire Push_Clk1, Pop_Clk1; - input wire PUSH1, POP1; - input wire [WR1_DATA_WIDTH-1:0] DIN1; - input wire Async_Flush1; - output wire [RD1_DATA_WIDTH-1:0] DOUT1; - output wire Almost_Full1, Almost_Empty1; - output wire Full1, Empty1; - output wire Full_Watermark1, Empty_Watermark1; - output wire Overrun_Error1, Underrun_Error1; - - input wire Push_Clk2, Pop_Clk2; - input wire PUSH2, POP2; - input wire [WR2_DATA_WIDTH-1:0] DIN2; - input wire Async_Flush2; - output wire [RD2_DATA_WIDTH-1:0] DOUT2; - output wire Almost_Full2, Almost_Empty2; - output wire Full2, Empty2; - output wire Full_Watermark2, Empty_Watermark2; - output wire Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire Push_Clk1, Pop_Clk1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire Push_Clk2, Pop_Clk2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = WR1_DATA_WIDTH *) - (* port_b_dwidth = RD1_DATA_WIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = WR1_DATA_WIDTH *) + (* port_b_dwidth = RD1_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -4091,268 +4091,268 @@ module BRAM2x18_AFIFO ( endmodule module AFIFO_18K_BLK ( - DIN, - PUSH, - POP, - Push_Clk, - Pop_Clk, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - - parameter WR_DATA_WIDTH = 18; - parameter RD_DATA_WIDTH = 18; - parameter UPAE_DBITS = 11'd10; - parameter UPAF_DBITS = 11'd10; - - input wire Push_Clk, Pop_Clk; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + BRAM2x18_AFIFO #( - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .UPAE_DBITS1(UPAE_DBITS), - .UPAF_DBITS1(UPAF_DBITS), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .UPAE_DBITS2(), - .UPAF_DBITS2() - ) U1 - ( - .DIN1(DIN), - .PUSH1(PUSH), - .POP1(POP), - .Push_Clk1(Push_Clk), - .Pop_Clk1(Pop_Clk), - .Async_Flush1(Async_Flush), - .Overrun_Error1(Overrun_Error), - .Full_Watermark1(Full_Watermark), - .Almost_Full1(Almost_Full), - .Full1(Full), - .Underrun_Error1(Underrun_Error), - .Empty_Watermark1(Empty_Watermark), - .Almost_Empty1(Almost_Empty), - .Empty1(Empty), - .DOUT1(DOUT), - - .DIN2(18'h0), - .PUSH2(1'b0), - .POP2(1'b0), - .Push_Clk2(1'b0), - .Pop_Clk2(1'b0), - .Async_Flush2(1'b0), - .Overrun_Error2(), - .Full_Watermark2(), - .Almost_Full2(), - .Full2(), - .Underrun_Error2(), - .Empty_Watermark2(), - .Almost_Empty2(), - .Empty2(), - .DOUT2() + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .Push_Clk1(Push_Clk), + .Pop_Clk1(Pop_Clk), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .Push_Clk2(1'b0), + .Pop_Clk2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() ); endmodule module AFIFO_18K_X2_BLK ( - DIN1, - PUSH1, - POP1, - Push_Clk1, + DIN1, + PUSH1, + POP1, + Push_Clk1, Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input wire Push_Clk1, Pop_Clk1; - input wire PUSH1, POP1; - input wire [WR1_DATA_WIDTH-1:0] DIN1; - input wire Async_Flush1; - output wire [RD1_DATA_WIDTH-1:0] DOUT1; - output wire Almost_Full1, Almost_Empty1; - output wire Full1, Empty1; - output wire Full_Watermark1, Empty_Watermark1; - output wire Overrun_Error1, Underrun_Error1; - - input wire Push_Clk2, Pop_Clk2; - input wire PUSH2, POP2; - input wire [WR2_DATA_WIDTH-1:0] DIN2; - input wire Async_Flush2; - output wire [RD2_DATA_WIDTH-1:0] DOUT2; - output wire Almost_Full2, Almost_Empty2; - output wire Full2, Empty2; - output wire Full_Watermark2, Empty_Watermark2; - output wire Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire Push_Clk1, Pop_Clk1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire Push_Clk2, Pop_Clk2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 1 *) - (* is_inferred = 0 *) - (* port_a1_dwidth = WR1_DATA_WIDTH *) - (* port_a2_dwidth = WR2_DATA_WIDTH *) - (* port_b1_dwidth = RD1_DATA_WIDTH *) - (* port_b2_dwidth = RD2_DATA_WIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = WR1_DATA_WIDTH *) + (* port_a2_dwidth = WR2_DATA_WIDTH *) + (* port_b1_dwidth = RD1_DATA_WIDTH *) + (* port_b2_dwidth = RD2_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -4392,138 +4392,138 @@ module AFIFO_18K_X2_BLK ( endmodule module SFIFO_36K_BLK ( - DIN, - PUSH, - POP, - CLK, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - parameter WR_DATA_WIDTH = 36; - parameter RD_DATA_WIDTH = 36; - parameter UPAE_DBITS = 12'd10; - parameter UPAF_DBITS = 12'd10; - - input wire CLK; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS; - localparam [11:0] UPAF1_i = UPAF_DBITS; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd0; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = 11'd10; - localparam [10:0] UPAF2_i = 11'd10; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [35:0] in_reg; - wire [35:0] out_reg; - wire [17:0] fifo_flags; - - wire [35:0] RD_DATA_INT; - - wire Push_Clk, Pop_Clk; - - assign Push_Clk = CLK; - assign Pop_Clk = CLK; - - assign Overrun_Error = fifo_flags[0]; - assign Full_Watermark = fifo_flags[1]; - assign Almost_Full = fifo_flags[2]; - assign Full = fifo_flags[3]; - assign Underrun_Error = fifo_flags[4]; - assign Empty_Watermark = fifo_flags[5]; - assign Almost_Empty = fifo_flags[6]; - assign Empty = fifo_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); - - generate - if (WR_DATA_WIDTH == 36) begin - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; - assign in_reg[17:0] = {2'b00,DIN[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; - end else begin - assign in_reg[35:WR_DATA_WIDTH] = 0; - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD_DATA_WIDTH == 36) begin - assign RD_DATA_INT = out_reg; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; - end else begin - assign RD_DATA_INT = {18'h0, out_reg[17:0]}; - end - endgenerate - - assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + + wire Push_Clk, Pop_Clk; + + assign Push_Clk = CLK; + assign Pop_Clk = CLK; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_inferred = 0 *) - (* is_split = 0 *) - (* port_a_dwidth = WR_DATA_WIDTH *) - (* port_b_dwidth = RD_DATA_WIDTH *) - TDP36K _TECHMAP_REPLACE_ ( + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = WR_DATA_WIDTH *) + (* port_b_dwidth = RD_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg[17:0]), .WDATA_A2_i(in_reg[35:18]), @@ -4559,138 +4559,138 @@ module SFIFO_36K_BLK ( .FLUSH2_i(1'b0) ); -endmodule +endmodule module AFIFO_36K_BLK ( - DIN, - PUSH, - POP, - Push_Clk, - Pop_Clk, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - parameter WR_DATA_WIDTH = 36; - parameter RD_DATA_WIDTH = 36; - parameter UPAE_DBITS = 12'd10; - parameter UPAF_DBITS = 12'd10; - - input wire Push_Clk, Pop_Clk; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS; - localparam [11:0] UPAF1_i = UPAF_DBITS; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd0; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = 11'd10; - localparam [10:0] UPAF2_i = 11'd10; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [35:0] in_reg; - wire [35:0] out_reg; - wire [17:0] fifo_flags; - - wire [35:0] RD_DATA_INT; - wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; - - assign Overrun_Error = fifo_flags[0]; - assign Full_Watermark = fifo_flags[1]; - assign Almost_Full = fifo_flags[2]; - assign Full = fifo_flags[3]; - assign Underrun_Error = fifo_flags[4]; - assign Empty_Watermark = fifo_flags[5]; - assign Almost_Empty = fifo_flags[6]; - assign Empty = fifo_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); - - generate - if (WR_DATA_WIDTH == 36) begin - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; - assign in_reg[17:0] = {2'b00,DIN[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; - end else begin - assign in_reg[35:WR_DATA_WIDTH] = 0; - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD_DATA_WIDTH == 36) begin - assign RD_DATA_INT = out_reg; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; - end else begin - assign RD_DATA_INT = {18'h0, out_reg[17:0]}; - end - endgenerate - - assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_inferred = 0 *) - (* is_split = 0 *) - (* port_a_dwidth = WR_DATA_WIDTH *) - (* port_b_dwidth = RD_DATA_WIDTH *) + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = WR_DATA_WIDTH *) + (* port_b_dwidth = RD_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg[17:0]), @@ -4727,97 +4727,97 @@ module AFIFO_36K_BLK ( .FLUSH2_i(1'b0) ); -endmodule +endmodule //=============================================================================== module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -4826,27 +4826,27 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -4858,93 +4858,93 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -4953,27 +4953,27 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -4985,93 +4985,93 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5080,27 +5080,27 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5112,93 +5112,93 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5207,27 +5207,27 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5239,93 +5239,93 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5334,27 +5334,27 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5366,93 +5366,93 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5461,27 +5461,27 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5493,93 +5493,93 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5588,27 +5588,27 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5620,93 +5620,93 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5715,27 +5715,27 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5747,93 +5747,93 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5842,27 +5842,27 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5874,93 +5874,93 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5969,27 +5969,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6001,93 +6001,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6096,27 +6096,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6128,93 +6128,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6223,27 +6223,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6255,93 +6255,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6350,27 +6350,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6382,93 +6382,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6477,27 +6477,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6509,93 +6509,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6604,27 +6604,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6636,93 +6636,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6731,27 +6731,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6763,93 +6763,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6858,27 +6858,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6890,93 +6890,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6985,27 +6985,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7017,93 +7017,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7112,27 +7112,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7144,93 +7144,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7239,27 +7239,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7271,93 +7271,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7366,27 +7366,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7398,93 +7398,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7493,27 +7493,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7525,93 +7525,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7620,27 +7620,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7652,93 +7652,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7747,27 +7747,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7779,93 +7779,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7874,27 +7874,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7906,93 +7906,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8001,27 +8001,27 @@ module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8033,93 +8033,93 @@ module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8128,27 +8128,27 @@ module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8160,93 +8160,93 @@ module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8255,27 +8255,27 @@ module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8287,93 +8287,93 @@ module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8382,27 +8382,27 @@ module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8414,93 +8414,93 @@ module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8509,27 +8509,27 @@ module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8541,93 +8541,93 @@ module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8636,27 +8636,27 @@ module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8668,93 +8668,93 @@ module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8763,27 +8763,27 @@ module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8795,93 +8795,93 @@ module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8890,27 +8890,27 @@ module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8922,93 +8922,93 @@ module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9017,27 +9017,27 @@ module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9049,93 +9049,93 @@ module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9144,27 +9144,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9176,93 +9176,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9271,27 +9271,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9303,93 +9303,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9398,27 +9398,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9430,93 +9430,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9525,27 +9525,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9557,93 +9557,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9652,27 +9652,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9684,93 +9684,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9779,27 +9779,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9811,93 +9811,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9906,27 +9906,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9938,93 +9938,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10033,27 +10033,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10065,93 +10065,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10160,27 +10160,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10192,93 +10192,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10287,27 +10287,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10319,93 +10319,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10414,27 +10414,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10446,93 +10446,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10541,27 +10541,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10573,93 +10573,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10668,27 +10668,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10700,93 +10700,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10795,27 +10795,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10827,93 +10827,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10922,27 +10922,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10954,93 +10954,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -11049,27 +11049,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); diff --git a/techlibs/quicklogic/qlf_k6n10f/cells_sim.v b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v index 645a62f833a..b9f40625646 100644 --- a/techlibs/quicklogic/qlf_k6n10f/cells_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v @@ -19,104 +19,104 @@ `default_nettype none (* abc9_lut=1 *) module LUT1(output wire O, input wire I0); - parameter [1:0] INIT = 0; - assign O = I0 ? INIT[1] : INIT[0]; - specify - (I0 => O) = 74; - endspecify + parameter [1:0] INIT = 0; + assign O = I0 ? INIT[1] : INIT[0]; + specify + (I0 => O) = 74; + endspecify endmodule (* abc9_lut=2 *) module LUT2(output wire O, input wire I0, I1); - parameter [3:0] INIT = 0; - wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 116; - (I1 => O) = 74; - endspecify + parameter [3:0] INIT = 0; + wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 116; + (I1 => O) = 74; + endspecify endmodule (* abc9_lut=3 *) module LUT3(output wire O, input wire I0, I1, I2); - parameter [7:0] INIT = 0; - wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 162; - (I1 => O) = 116; - (I2 => O) = 174; - endspecify + parameter [7:0] INIT = 0; + wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 162; + (I1 => O) = 116; + (I2 => O) = 174; + endspecify endmodule (* abc9_lut=3 *) module LUT4(output wire O, input wire I0, I1, I2, I3); - parameter [15:0] INIT = 0; - wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 201; - (I1 => O) = 162; - (I2 => O) = 116; - (I3 => O) = 74; - endspecify + parameter [15:0] INIT = 0; + wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 201; + (I1 => O) = 162; + (I2 => O) = 116; + (I3 => O) = 74; + endspecify endmodule (* abc9_lut=3 *) module LUT5(output wire O, input wire I0, I1, I2, I3, I4); - parameter [31:0] INIT = 0; - wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; - wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 228; - (I1 => O) = 189; - (I2 => O) = 143; - (I3 => O) = 100; - (I4 => O) = 55; - endspecify + parameter [31:0] INIT = 0; + wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 228; + (I1 => O) = 189; + (I2 => O) = 143; + (I3 => O) = 100; + (I4 => O) = 55; + endspecify endmodule (* abc9_lut=5 *) module LUT6(output wire O, input wire I0, I1, I2, I3, I4, I5); - parameter [63:0] INIT = 0; - wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; - wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; - wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 251; - (I1 => O) = 212; - (I2 => O) = 166; - (I3 => O) = 123; - (I4 => O) = 77; - (I5 => O) = 43; - endspecify + parameter [63:0] INIT = 0; + wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; + wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 251; + (I1 => O) = 212; + (I2 => O) = 166; + (I3 => O) = 123; + (I4 => O) = 77; + (I5 => O) = 43; + endspecify endmodule (* abc9_flop, lib_whitebox *) module sh_dff( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C ); - initial Q <= 1'b0; - always @(posedge C) - Q <= D; - - specify - (posedge C => (Q +: D)) = 0; - $setuphold(posedge C, D, 0, 0); - endspecify + initial Q = 1'b0; + always @(posedge C) + Q <= D; + + specify + (posedge C => (Q +: D)) = 0; + $setuphold(posedge C, D, 0, 0); + endspecify endmodule @@ -124,253 +124,253 @@ endmodule (* blackbox *) (* keep *) module adder_carry( - output wire sumout, - (* abc9_carry *) - output wire cout, - input wire p, - input wire g, - (* abc9_carry *) - input wire cin + output wire sumout, + (* abc9_carry *) + output wire cout, + input wire p, + input wire g, + (* abc9_carry *) + input wire cin ); - assign sumout = p ^ cin; - assign cout = p ? cin : g; - - specify - (p => sumout) = 35; - (g => sumout) = 35; - (cin => sumout) = 40; - (p => cout) = 67; - (g => cout) = 65; - (cin => cout) = 69; - endspecify + assign sumout = p ^ cin; + assign cout = p ? cin : g; + + specify + (p => sumout) = 35; + (g => sumout) = 35; + (cin => sumout) = 40; + (p => cout) = 67; + (g => cout) = 65; + (cin => cout) = 69; + endspecify endmodule (* abc9_flop, lib_whitebox *) module dff( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C ); - initial Q <= 1'b0; + initial Q = 1'b0; - always @(posedge C) - Q <= D; + always @(posedge C) + Q <= D; - specify - (posedge C=>(Q+:D)) = 285; - $setuphold(posedge C, D, 56, 0); - endspecify + specify + (posedge C=>(Q+:D)) = 285; + $setuphold(posedge C, D, 56, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module dffn( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C ); - initial Q <= 1'b0; + initial Q = 1'b0; + + always @(negedge C) + Q <= D; - always @(negedge C) - Q <= D; - - specify - (negedge C=>(Q+:D)) = 285; - $setuphold(negedge C, D, 56, 0); - endspecify + specify + (negedge C=>(Q+:D)) = 285; + $setuphold(negedge C, D, 56, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module dffsre( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C, - input wire E, - input wire R, - input wire S + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S ); - initial Q <= 1'b0; - - always @(posedge C or negedge S or negedge R) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - - specify - (posedge C => (Q +: D)) = 280; - (R => Q) = 0; - (S => Q) = 0; - $setuphold(posedge C, D, 56, 0); - $setuphold(posedge C, E, 32, 0); - $setuphold(posedge C, R, 0, 0); - $setuphold(posedge C, S, 0, 0); - $recrem(posedge R, posedge C, 0, 0); - $recrem(posedge S, posedge C, 0, 0); - endspecify + initial Q = 1'b0; + + always @(posedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (posedge C => (Q +: D)) = 280; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(posedge C, D, 56, 0); + $setuphold(posedge C, E, 32, 0); + $setuphold(posedge C, R, 0, 0); + $setuphold(posedge C, S, 0, 0); + $recrem(posedge R, posedge C, 0, 0); + $recrem(posedge S, posedge C, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module dffnsre( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C, - input wire E, - input wire R, - input wire S + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S ); - initial Q <= 1'b0; - - always @(negedge C or negedge S or negedge R) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - - specify - (negedge C => (Q +: D)) = 280; - (R => Q) = 0; - (S => Q) = 0; - $setuphold(negedge C, D, 56, 0); - $setuphold(negedge C, E, 32, 0); - $setuphold(negedge C, R, 0, 0); - $setuphold(negedge C, S, 0, 0); - $recrem(posedge R, negedge C, 0, 0); - $recrem(posedge S, negedge C, 0, 0); - endspecify + initial Q = 1'b0; + + always @(negedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (negedge C => (Q +: D)) = 280; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(negedge C, D, 56, 0); + $setuphold(negedge C, E, 32, 0); + $setuphold(negedge C, R, 0, 0); + $setuphold(negedge C, S, 0, 0); + $recrem(posedge R, negedge C, 0, 0); + $recrem(posedge S, negedge C, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module sdffsre( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C, - input wire E, - input wire R, - input wire S + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S ); - initial Q <= 1'b0; - - always @(posedge C) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - - specify - (posedge C => (Q +: D)) = 280; - $setuphold(posedge C, D, 56, 0); - $setuphold(posedge C, R, 32, 0); - $setuphold(posedge C, S, 0, 0); - $setuphold(posedge C, E, 0, 0); - endspecify + initial Q = 1'b0; + + always @(posedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (posedge C => (Q +: D)) = 280; + $setuphold(posedge C, D, 56, 0); + $setuphold(posedge C, R, 32, 0); + $setuphold(posedge C, S, 0, 0); + $setuphold(posedge C, E, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module sdffnsre( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C, - input wire E, - input wire R, - input wire S + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S ); - initial Q <= 1'b0; - - always @(negedge C) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - - specify - (negedge C => (Q +: D)) = 280; - $setuphold(negedge C, D, 56, 0); - $setuphold(negedge C, R, 32, 0); - $setuphold(negedge C, S, 0, 0); - $setuphold(negedge C, E, 0, 0); - endspecify + initial Q = 1'b0; + + always @(negedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (negedge C => (Q +: D)) = 280; + $setuphold(negedge C, D, 56, 0); + $setuphold(negedge C, R, 32, 0); + $setuphold(negedge C, S, 0, 0); + $setuphold(negedge C, E, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module latchsre ( - output reg Q, - input wire S, - input wire R, - input wire D, - input wire G, - input wire E + output reg Q, + input wire S, + input wire R, + input wire D, + input wire G, + input wire E ); - initial Q <= 1'b0; - - always @* - begin - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E && G) - Q <= D; - end - - specify - (posedge G => (Q +: D)) = 0; - $setuphold(posedge G, D, 0, 0); - $setuphold(posedge G, E, 0, 0); - $setuphold(posedge G, R, 0, 0); - $setuphold(posedge G, S, 0, 0); - endspecify + initial Q = 1'b0; + + always @* + begin + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E && G) + Q <= D; + end + + specify + (posedge G => (Q +: D)) = 0; + $setuphold(posedge G, D, 0, 0); + $setuphold(posedge G, E, 0, 0); + $setuphold(posedge G, R, 0, 0); + $setuphold(posedge G, S, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module latchnsre ( - output reg Q, - input wire S, - input wire R, - input wire D, - input wire G, - input wire E + output reg Q, + input wire S, + input wire R, + input wire D, + input wire G, + input wire E ); - initial Q <= 1'b0; - - always @* - begin - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E && !G) - Q <= D; - end - - specify - (negedge G => (Q +: D)) = 0; - $setuphold(negedge G, D, 0, 0); - $setuphold(negedge G, E, 0, 0); - $setuphold(negedge G, R, 0, 0); - $setuphold(negedge G, S, 0, 0); - endspecify + initial Q = 1'b0; + + always @* + begin + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E && !G) + Q <= D; + end + + specify + (negedge G => (Q +: D)) = 0; + $setuphold(negedge G, D, 0, 0); + $setuphold(negedge G, E, 0, 0); + $setuphold(negedge G, R, 0, 0); + $setuphold(negedge G, S, 0, 0); + endspecify endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/ffs_map.v b/techlibs/quicklogic/qlf_k6n10f/ffs_map.v index 26fa6ed3604..43a71b425a1 100644 --- a/techlibs/quicklogic/qlf_k6n10f/ffs_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/ffs_map.v @@ -16,116 +16,116 @@ // DFF, asynchronous set/reset, enable module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q); - input C; - input S; - input R; - input E; - input D; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); + input C; + input S; + input R; + input E; + input D; + output Q; + dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); endmodule module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q); - input C; - input S; - input R; - input E; - input D; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); + input C; + input S; + input R; + input E; + input D; + output Q; + dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); endmodule // DFF, synchronous set or reset, enable module \$_SDFFE_PN0P_ (D, C, R, E, Q); - input D; - input C; - input R; - input E; - output Q; - sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); + input D; + input C; + input R; + input E; + output Q; + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); endmodule module \$_SDFFE_PN1P_ (D, C, R, E, Q); - input D; - input C; - input R; - input E; - output Q; - sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); + input D; + input C; + input R; + input E; + output Q; + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); endmodule module \$_SDFFE_NN0P_ (D, C, R, E, Q); - input D; - input C; - input R; - input E; - output Q; - sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); + input D; + input C; + input R; + input E; + output Q; + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); endmodule module \$_SDFFE_NN1P_ (D, C, R, E, Q); - input D; - input C; - input R; - input E; - output Q; - sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); + input D; + input C; + input R; + input E; + output Q; + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); endmodule // Latch, no set/reset, no enable module \$_DLATCH_P_ (input E, D, output Q); - latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); endmodule module \$_DLATCH_N_ (input E, D, output Q); - latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); endmodule // Latch with async set and reset and enable module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q); - latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); endmodule module \$_DLATCHSR_NPP_ (input E, S, R, D, output Q); - latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); endmodule module \$__SHREG_DFF_P_ (D, Q, C); - input D; - input C; - output Q; - - parameter DEPTH = 2; - - reg [DEPTH-2:0] q; - - genvar i; - generate for (i = 0; i < DEPTH; i = i + 1) begin: slice - - // First in chain - generate if (i == 0) begin - sh_dff #() shreg_beg ( - .Q(q[i]), - .D(D), - .C(C) - ); - end endgenerate - // Middle in chain - generate if (i > 0 && i != DEPTH-1) begin - sh_dff #() shreg_mid ( - .Q(q[i]), - .D(q[i-1]), - .C(C) - ); - end endgenerate - // Last in chain - generate if (i == DEPTH-1) begin - sh_dff #() shreg_end ( - .Q(Q), - .D(q[i-1]), - .C(C) - ); - end endgenerate + input D; + input C; + output Q; + + parameter DEPTH = 2; + + reg [DEPTH-2:0] q; + + genvar i; + generate for (i = 0; i < DEPTH; i = i + 1) begin: slice + + // First in chain + generate if (i == 0) begin + sh_dff #() shreg_beg ( + .Q(q[i]), + .D(D), + .C(C) + ); + end endgenerate + // Middle in chain + generate if (i > 0 && i != DEPTH-1) begin + sh_dff #() shreg_mid ( + .Q(q[i]), + .D(q[i-1]), + .C(C) + ); + end endgenerate + // Last in chain + generate if (i == DEPTH-1) begin + sh_dff #() shreg_end ( + .Q(Q), + .D(q[i-1]), + .C(C) + ); + end endgenerate end: slice endgenerate diff --git a/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py b/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py new file mode 100644 index 00000000000..5f7da90977e --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py @@ -0,0 +1,246 @@ +import sys +from datetime import datetime, timezone + +def generate(filename): + with open(filename, "w") as f: + f.write("// **AUTOGENERATED FILE** **DO NOT EDIT**\n") + f.write(f"// Generated by {sys.argv[0]} at {datetime.now(timezone.utc)}\n") + + f.write("`timescale 1ns /10ps\n") + for a_width in [1,2,4,9,18,36]: + for b_width in [1,2,4,9,18,36]: + f.write(f""" +module TDP36K_BRAM_A_X{a_width}_B_X{b_width}_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule +""") + + for a1_width in [1,2,4,9,18]: + for b1_width in [1,2,4,9,18]: + for a2_width in [1,2,4,9,18]: + for b2_width in [1,2,4,9,18]: + f.write(f""" +module TDP36K_BRAM_A1_X{a1_width}_B1_X{b1_width}_A2_X{a2_width}_B2_X{b2_width}_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule +""") + +if __name__ == "__main__": + filename = "bram_types_sim.v" + if len(sys.argv) > 1: + filename = sys.argv[1] + generate(filename) diff --git a/techlibs/quicklogic/quicklogic_eqn.cc b/techlibs/quicklogic/quicklogic_eqn.cc deleted file mode 100644 index b82a1b2866e..00000000000 --- a/techlibs/quicklogic/quicklogic_eqn.cc +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright 2020-2022 F4PGA Authors - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -#include "kernel/sigtools.h" -#include "kernel/yosys.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct QuicklogicEqnPass : public Pass { - QuicklogicEqnPass() : Pass("quicklogic_eqn", "Quicklogic: Calculate equations for luts") {} - void help() override - { - log("\n"); - log(" quicklogic_eqn [selection]\n"); - log("\n"); - log("Calculate equations for luts since bitstream generator depends on it.\n"); - log("\n"); - } - - Const init2eqn(Const init, int inputs) - { - std::string init_bits = init.as_string(); - const char *names[] = {"I0", "I1", "I2", "I3", "I4"}; - - std::string eqn; - int width = (int)pow(2, inputs); - for (int i = 0; i < width; i++) { - if (init_bits[width - 1 - i] == '1') { - eqn += "("; - for (int j = 0; j < inputs; j++) { - if (i & (1 << j)) - eqn += names[j]; - else - eqn += std::string("~") + names[j]; - - if (j != (inputs - 1)) - eqn += "*"; - } - eqn += ")+"; - } - } - if (eqn.empty()) - return Const("0"); - eqn = eqn.substr(0, eqn.length() - 1); - return Const(eqn); - } - - void execute(std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing Quicklogic_EQN pass (calculate equations for luts).\n"); - - extra_args(args, args.size(), design); - - int cnt = 0; - for (auto module : design->selected_modules()) { - for (auto cell : module->selected_cells()) { - if (cell->type == ID(LUT1)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 1)); - cnt++; - } - if (cell->type == ID(LUT2)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 2)); - cnt++; - } - if (cell->type == ID(LUT3)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 3)); - cnt++; - } - if (cell->type == ID(LUT4)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 4)); - cnt++; - } - if (cell->type == ID(LUT5)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 5)); - cnt++; - } - } - } - log_header(design, "Updated %d of LUT* elements with equation.\n", cnt); - } -} QuicklogicEqnPass; - -PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 15ab68a3f72..d2df6bcff15 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -129,10 +129,6 @@ struct SynthQuickLogicPass : public ScriptPass { blif_file = args[++argidx]; continue; } - if (args[argidx] == "-edif" && argidx + 1 < args.size()) { - edif_file = args[++argidx]; - continue; - } if (args[argidx] == "-verilog" && argidx+1 < args.size()) { verilog_file = args[++argidx]; continue; @@ -141,15 +137,15 @@ struct SynthQuickLogicPass : public ScriptPass { abc9 = false; continue; } - if (args[argidx] == "-nocarry") { + if (args[argidx] == "-nocarry" || args[argidx] == "-no_adder") { inferAdder = false; continue; } - if (args[argidx] == "-nobram") { + if (args[argidx] == "-nobram" || args[argidx] == "-no_bram") { nobram = true; continue; } - if (args[argidx] == "-bramtypes") { + if (args[argidx] == "-bramtypes" || args[argidx] == "-bram_types") { bramTypes = true; continue; } @@ -230,61 +226,8 @@ struct SynthQuickLogicPass : public ScriptPass { run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); run("techmap -map " + lib_path + family + "/brams_final_map.v"); - if (help_mode) { - run("chtype -set TDP36K_ t:TDP36K a:", "(if -bram_types)"); - } - else if (bramTypes) { - for (int a_dwidth : {1, 2, 4, 9, 18, 36}) - for (int b_dwidth: {1, 2, 4, 9, 18, 36}) { - run(stringf("chtype -set TDP36K_BRAM_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " - "a:is_fifo=0 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", - a_dwidth, b_dwidth, a_dwidth, b_dwidth)); - - run(stringf("chtype -set TDP36K_FIFO_ASYNC_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " - "a:is_fifo=1 %%i a:sync_fifo=0 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", - a_dwidth, b_dwidth, a_dwidth, b_dwidth)); - - run(stringf("chtype -set TDP36K_FIFO_SYNC_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " - "a:is_fifo=1 %%i a:sync_fifo=1 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", - a_dwidth, b_dwidth, a_dwidth, b_dwidth)); - } - - for (int a1_dwidth : {1, 2, 4, 9, 18}) - for (int b1_dwidth: {1, 2, 4, 9, 18}) - for (int a2_dwidth : {1, 2, 4, 9, 18}) - for (int b2_dwidth: {1, 2, 4, 9, 18}) { - run(stringf("chtype -set TDP36K_BRAM_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " - "a:is_split=1 %%i a:is_fifo=0 %%i " - "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", - a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); - - run(stringf("chtype -set TDP36K_FIFO_ASYNC_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " - "a:is_split=1 %%i a:is_fifo=1 %%i a:sync_fifo=0 %%i " - "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", - a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); - - run(stringf("chtype -set TDP36K_FIFO_SYNC_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " - "a:is_split=1 %%i a:is_fifo=1 %%i a:sync_fifo=1 %%i " - "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", - a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); - } - - - for (int a_width : {1, 2, 4, 9, 18, 36}) - for (int b_width: {1, 2, 4, 9, 18, 36}) { - run(stringf("chtype -set TDP36K_BRAM_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=1 %%i " - "a:port_a_width=%d %%i a:port_b_width=%d %%i", - a_width, b_width, a_width, b_width)); - } - - for (int a1_width : {1, 2, 4, 9, 18}) - for (int b1_width: {1, 2, 4, 9, 18}) - for (int a2_width : {1, 2, 4, 9, 18}) - for (int b2_width: {1, 2, 4, 9, 18}) { - run(stringf("chtype -set TDP36K_BRAM_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=1 %%i " - "a:port_a1_width=%d %%i a:port_b1_width=%d %%i a:port_a2_width=%d %%i a:port_b2_width=%d %%i", - a1_width, b1_width, a2_width, b2_width, a1_width, b1_width, a2_width, b2_width)); - } + if (help_mode || bramTypes) { + run("ql_bram_types"); } } @@ -393,13 +336,6 @@ struct SynthQuickLogicPass : public ScriptPass { run(stringf("write_verilog -noattr -nohex %s", help_mode ? "" : verilog_file.c_str())); } } - - if (check_label("edif", "(if -edif)")) { - if (!edif_file.empty() || help_mode) { - run("splitnets -ports -format ()"); - run(stringf("write_edif -nogndvcc -attrprop -pvector par %s %s", top_opt.c_str(), edif_file.c_str())); - } - } } } SynthQuicklogicPass; From 20d864bbdeee0b7854e5a6816159a12b21cb4861 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 27 Nov 2023 10:35:29 +0100 Subject: [PATCH 170/240] add dsp inference --- techlibs/quicklogic/.gitignore | 1 + techlibs/quicklogic/Makefile.inc | 23 +- .../{ql-bram-merge.cc => ql_bram_merge.cc} | 0 .../{ql-bram-types.cc => ql_bram_types.cc} | 0 techlibs/quicklogic/ql_dsp_io_regs.cc | 244 + techlibs/quicklogic/ql_dsp_macc.cc | 307 + techlibs/quicklogic/ql_dsp_macc.pmg | 50 + techlibs/quicklogic/ql_dsp_simd.cc | 359 + .../quicklogic/qlf_k6n10f/dsp_final_map.v | 265 + techlibs/quicklogic/qlf_k6n10f/dsp_map.v | 147 + techlibs/quicklogic/qlf_k6n10f/dsp_sim.v | 5753 +++++++++++++++++ techlibs/quicklogic/synth_quicklogic.cc | 47 +- 12 files changed, 7189 insertions(+), 7 deletions(-) create mode 100644 techlibs/quicklogic/.gitignore rename techlibs/quicklogic/{ql-bram-merge.cc => ql_bram_merge.cc} (100%) rename techlibs/quicklogic/{ql-bram-types.cc => ql_bram_types.cc} (100%) create mode 100644 techlibs/quicklogic/ql_dsp_io_regs.cc create mode 100644 techlibs/quicklogic/ql_dsp_macc.cc create mode 100644 techlibs/quicklogic/ql_dsp_macc.pmg create mode 100644 techlibs/quicklogic/ql_dsp_simd.cc create mode 100644 techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/dsp_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/dsp_sim.v diff --git a/techlibs/quicklogic/.gitignore b/techlibs/quicklogic/.gitignore new file mode 100644 index 00000000000..e52f3282f7f --- /dev/null +++ b/techlibs/quicklogic/.gitignore @@ -0,0 +1 @@ +/*_pm.h diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index df69a3fc32c..ce5ff859b2e 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,6 +1,20 @@ +%_pm.h: passes/pmgen/pmgen.py %.pmg + $(P) mkdir -p pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^) + OBJS += techlibs/quicklogic/synth_quicklogic.o -OBJS += techlibs/quicklogic/ql-bram-merge.o -OBJS += techlibs/quicklogic/ql-bram-types.o +OBJS += techlibs/quicklogic/ql_bram_merge.o +OBJS += techlibs/quicklogic/ql_bram_types.o +OBJS += techlibs/quicklogic/ql_dsp_simd.o +OBJS += techlibs/quicklogic/ql_dsp_io_regs.o + +# -------------------------------------- + +OBJS += techlibs/quicklogic/ql_dsp_macc.o +GENFILES += techlibs/quicklogic/ql_dsp_macc_pm.h +techlibs/quicklogic/ql_dsp_macc.o: techlibs/quicklogic/ql_dsp_macc_pm.h +$(eval $(call add_extra_objs,techlibs/quicklogic/ql_dsp_macc_pm.h)) + +# -------------------------------------- $(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v)) @@ -21,4 +35,7 @@ $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v)) -$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v)) \ No newline at end of file +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_sim.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v)) \ No newline at end of file diff --git a/techlibs/quicklogic/ql-bram-merge.cc b/techlibs/quicklogic/ql_bram_merge.cc similarity index 100% rename from techlibs/quicklogic/ql-bram-merge.cc rename to techlibs/quicklogic/ql_bram_merge.cc diff --git a/techlibs/quicklogic/ql-bram-types.cc b/techlibs/quicklogic/ql_bram_types.cc similarity index 100% rename from techlibs/quicklogic/ql-bram-types.cc rename to techlibs/quicklogic/ql_bram_types.cc diff --git a/techlibs/quicklogic/ql_dsp_io_regs.cc b/techlibs/quicklogic/ql_dsp_io_regs.cc new file mode 100644 index 00000000000..217a5aa5573 --- /dev/null +++ b/techlibs/quicklogic/ql_dsp_io_regs.cc @@ -0,0 +1,244 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#define MODE_BITS_REGISTER_INPUTS_ID 92 +#define MODE_BITS_OUTPUT_SELECT_START_ID 81 +#define MODE_BITS_OUTPUT_SELECT_WIDTH 3 + +// ============================================================================ + +struct QlDspIORegs : public Pass { + + const std::vector ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b"}; + const std::vector ports2del_mult_acc = {"acc_fir", "dly_b"}; + const std::vector ports2del_mult_add = {"dly_b"}; + const std::vector ports2del_extension = {"saturate_enable", "shift_right", "round"}; + + /// Temporary SigBit to SigBit helper map. + SigMap m_SigMap; + + // .......................................... + + QlDspIORegs() : Pass("ql_dsp_io_regs", "Changes types of QL_DSP2/QL_DSP3 depending on their configuration.") {} + + void help() override + { + log("\n"); + log(" ql_dsp_io_regs [options] [selection]\n"); + log("\n"); + log("Looks for QL_DSP2/QL_DSP3 cells and changes their types depending\n"); + log("on their configuration.\n"); + } + + void execute(std::vector a_Args, RTLIL::Design *a_Design) override + { + log_header(a_Design, "Executing QL_DSP_IO_REGS pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < a_Args.size(); argidx++) { + break; + } + extra_args(a_Args, argidx, a_Design); + + for (auto module : a_Design->selected_modules()) { + ql_dsp_io_regs_pass(module); + } + } + + // Returns a pair of mask and value describing constant bit connections of + // a SigSpec + std::pair get_constant_mask_value(const RTLIL::SigSpec *sigspec) + { + uint32_t mask = 0L; + uint32_t value = 0L; + + auto sigbits = sigspec->bits(); + for (ssize_t i = (sigbits.size() - 1); i >= 0; --i) { + auto other = m_SigMap(sigbits[i]); + + mask <<= 1; + value <<= 1; + + // A known constant + if (!other.is_wire() && other.data != RTLIL::Sx) { + mask |= 0x1; + value |= (other.data == RTLIL::S1); + } + } + + return std::make_pair(mask, value); + } + + void ql_dsp_io_regs_pass(RTLIL::Module *module) + { + // Setup the SigMap + m_SigMap.clear(); + m_SigMap.set(module); + + for (auto cell : module->cells_) { + std::string cell_type = cell.second->type.str(); + if (cell_type == RTLIL::escape_id("QL_DSP2") || cell_type == RTLIL::escape_id("QL_DSP3")) { + auto dsp = cell.second; + + // If the cell does not have the "is_inferred" attribute set + // then don't touch it. + if (!dsp->has_attribute(RTLIL::escape_id("is_inferred")) || dsp->get_bool_attribute(RTLIL::escape_id("is_inferred")) == false) { + continue; + } + + bool del_clk = true; + bool use_dsp_cfg_params = (cell_type == RTLIL::escape_id("QL_DSP3")); + + int reg_in_i; + int out_sel_i; + + // Get DSP configuration + if (use_dsp_cfg_params) { + // Read MODE_BITS at correct indexes + auto mode_bits = &dsp->getParam(RTLIL::escape_id("MODE_BITS")); + RTLIL::Const register_inputs; + register_inputs = mode_bits->bits.at(MODE_BITS_REGISTER_INPUTS_ID); + reg_in_i = register_inputs.as_int(); + + RTLIL::Const output_select; + output_select = mode_bits->extract(MODE_BITS_OUTPUT_SELECT_START_ID, MODE_BITS_OUTPUT_SELECT_WIDTH); + out_sel_i = output_select.as_int(); + } else { + // Read dedicated configuration ports + const RTLIL::SigSpec *register_inputs; + register_inputs = &dsp->getPort(RTLIL::escape_id("register_inputs")); + if (!register_inputs) + log_error("register_inputs port not found!"); + auto reg_in_c = register_inputs->as_const(); + reg_in_i = reg_in_c.as_int(); + + const RTLIL::SigSpec *output_select; + output_select = &dsp->getPort(RTLIL::escape_id("output_select")); + if (!output_select) + log_error("output_select port not found!"); + auto out_sel_c = output_select->as_const(); + out_sel_i = out_sel_c.as_int(); + } + + // Get the feedback port + const RTLIL::SigSpec *feedback; + feedback = &dsp->getPort(RTLIL::escape_id("feedback")); + if (!feedback) + log_error("feedback port not found!"); + + // Check if feedback is or can be set to 0 which implies MACC + auto feedback_con = get_constant_mask_value(feedback); + bool have_macc = (feedback_con.second == 0x0); + // log("mask=0x%08X value=0x%08X\n", consts.first, consts.second); + // log_error("=== END HERE ===\n"); + + // Build new type name + std::string new_type = cell_type; + new_type += "_MULT"; + + if (have_macc) { + switch (out_sel_i) { + case 1: + case 2: + case 3: + case 5: + case 7: + del_clk = false; + new_type += "ACC"; + break; + default: + break; + } + } else { + switch (out_sel_i) { + case 1: + case 2: + case 3: + case 5: + case 7: + new_type += "ADD"; + break; + default: + break; + } + } + + if (reg_in_i) { + del_clk = false; + new_type += "_REGIN"; + } + + if (out_sel_i > 3) { + del_clk = false; + new_type += "_REGOUT"; + } + + // Set new type name + dsp->type = RTLIL::IdString(new_type); + + std::vector ports2del; + + if (del_clk) + ports2del.push_back("clk"); + + switch (out_sel_i) { + case 0: + case 4: + case 6: + ports2del.insert(ports2del.end(), ports2del_mult.begin(), ports2del_mult.end()); + // Mark for deleton additional configuration ports + if (!use_dsp_cfg_params) { + ports2del.insert(ports2del.end(), ports2del_extension.begin(), ports2del_extension.end()); + } + break; + case 1: + case 2: + case 3: + case 5: + case 7: + if (have_macc) { + ports2del.insert(ports2del.end(), ports2del_mult_acc.begin(), ports2del_mult_acc.end()); + } else { + ports2del.insert(ports2del.end(), ports2del_mult_add.begin(), ports2del_mult_add.end()); + } + break; + } + + for (auto portname : ports2del) { + const RTLIL::SigSpec *port = &dsp->getPort(RTLIL::escape_id(portname)); + if (!port) + log_error("%s port not found!", portname.c_str()); + dsp->connections_.erase(RTLIL::escape_id(portname)); + } + } + } + + // Clear the sigmap + m_SigMap.clear(); + } + +} QlDspIORegs; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc new file mode 100644 index 00000000000..ca898d9d0c2 --- /dev/null +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -0,0 +1,307 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#include "ql_dsp_macc_pm.h" + +// ============================================================================ + +bool use_dsp_cfg_params; + +static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) +{ + auto &st = pm.st_ql_dsp_macc; + + // Reject if multiplier drives anything else than either $add or $add and + // $mux + if (st.mux == nullptr && st.mul_nusers > 2) { + return; + } + + // Determine whether the output is taken from before or after the ff + bool out_ff; + if (st.ff_d_nusers == 2 && st.ff_q_nusers == 3) { + out_ff = true; + } else if (st.ff_d_nusers == 3 && st.ff_q_nusers == 2) { + out_ff = false; + } else { + // Illegal, cannot take the two outputs simulataneously + return; + } + + // No mux, the adder can driver either the ff or the ff + output + if (st.mux == nullptr) { + if (out_ff && st.add_nusers != 2) { + return; + } + if (!out_ff && st.add_nusers != 3) { + return; + } + } + // Mux present, the adder cannot drive anything else + else { + if (st.add_nusers != 2) { + return; + } + } + + // Mux can driver either the ff or the ff + output + if (st.mux != nullptr) { + if (out_ff && st.mux_nusers != 2) { + return; + } + if (!out_ff && st.mux_nusers != 3) { + return; + } + } + + // Accept only posedge clocked FFs + if (st.ff->getParam(ID(CLK_POLARITY)).as_int() != 1) { + return; + } + + // Get port widths + size_t a_width = GetSize(st.mul->getPort(ID(A))); + size_t b_width = GetSize(st.mul->getPort(ID(B))); + size_t z_width = GetSize(st.ff->getPort(ID(Q))); + + size_t min_width = std::min(a_width, b_width); + size_t max_width = std::max(a_width, b_width); + + // Signed / unsigned + bool a_signed = st.mul->getParam(ID(A_SIGNED)).as_bool(); + bool b_signed = st.mul->getParam(ID(B_SIGNED)).as_bool(); + + // Determine DSP type or discard if too narrow / wide + RTLIL::IdString type; + size_t tgt_a_width; + size_t tgt_b_width; + size_t tgt_z_width; + + string cell_base_name = "dsp_t1"; + string cell_size_name = ""; + string cell_cfg_name = ""; + string cell_full_name = ""; + + if (min_width <= 2 && max_width <= 2 && z_width <= 4) { + // Too narrow + return; + } else if (min_width <= 9 && max_width <= 10 && z_width <= 19) { + cell_size_name = "_10x9x32"; + tgt_a_width = 10; + tgt_b_width = 9; + tgt_z_width = 19; + } else if (min_width <= 18 && max_width <= 20 && z_width <= 38) { + cell_size_name = "_20x18x64"; + tgt_a_width = 20; + tgt_b_width = 18; + tgt_z_width = 38; + } else { + // Too wide + return; + } + + if (use_dsp_cfg_params) + cell_cfg_name = "_cfg_params"; + else + cell_cfg_name = "_cfg_ports"; + + cell_full_name = cell_base_name + cell_size_name + cell_cfg_name; + + type = RTLIL::escape_id(cell_full_name); + log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, RTLIL::unescape_id(type).c_str()); + + for (auto cell : {st.mul, st.add, st.mux, st.ff}) { + if (cell != nullptr) { + log(" %s (%s)\n", RTLIL::unescape_id(cell->name).c_str(), RTLIL::unescape_id(cell->type).c_str()); + } + } + + // Build the DSP cell name + std::string name; + name += RTLIL::unescape_id(st.mul->name) + "_"; + name += RTLIL::unescape_id(st.add->name) + "_"; + if (st.mux != nullptr) { + name += RTLIL::unescape_id(st.mux->name) + "_"; + } + name += RTLIL::unescape_id(st.ff->name); + + // Add the DSP cell + RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id(name), type); + + // Set attributes + cell->set_bool_attribute(RTLIL::escape_id("is_inferred"), true); + + // Get input/output data signals + RTLIL::SigSpec sig_a; + RTLIL::SigSpec sig_b; + RTLIL::SigSpec sig_z; + + if (a_width >= b_width) { + sig_a = st.mul->getPort(ID(A)); + sig_b = st.mul->getPort(ID(B)); + } else { + sig_a = st.mul->getPort(ID(B)); + sig_b = st.mul->getPort(ID(A)); + } + + sig_z = out_ff ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D)); + + // Connect input data ports, sign extend / pad with zeros + sig_a.extend_u0(tgt_a_width, a_signed); + sig_b.extend_u0(tgt_b_width, b_signed); + cell->setPort(RTLIL::escape_id("a_i"), sig_a); + cell->setPort(RTLIL::escape_id("b_i"), sig_b); + + // Connect output data port, pad if needed + if ((size_t)GetSize(sig_z) < tgt_z_width) { + auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z)); + sig_z.append(wire); + } + cell->setPort(RTLIL::escape_id("z_o"), sig_z); + + // Connect clock, reset and enable + cell->setPort(RTLIL::escape_id("clock_i"), st.ff->getPort(ID(CLK))); + + RTLIL::SigSpec rst; + RTLIL::SigSpec ena; + + if (st.ff->hasPort(ID(ARST))) { + if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) { + rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST))); + } else { + rst = st.ff->getPort(ID(ARST)); + } + } else { + rst = RTLIL::SigSpec(RTLIL::S0); + } + + if (st.ff->hasPort(ID(EN))) { + if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) { + ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN))); + } else { + ena = st.ff->getPort(ID(EN)); + } + } else { + ena = RTLIL::SigSpec(RTLIL::S1); + } + + cell->setPort(RTLIL::escape_id("reset_i"), rst); + cell->setPort(RTLIL::escape_id("load_acc_i"), ena); + + // Insert feedback_i control logic used for clearing / loading the accumulator + if (st.mux != nullptr) { + RTLIL::SigSpec sig_s = st.mux->getPort(ID(S)); + + // Depending on the mux port ordering insert inverter if needed + log_assert(st.mux_ab == ID(A) || st.mux_ab == ID(B)); + if (st.mux_ab == ID(A)) { + sig_s = pm.module->Not(NEW_ID, sig_s); + } + + // Assemble the full control signal for the feedback_i port + RTLIL::SigSpec sig_f; + sig_f.append(sig_s); + sig_f.append(RTLIL::S0); + sig_f.append(RTLIL::S0); + cell->setPort(RTLIL::escape_id("feedback_i"), sig_f); + } + // No acc clear/load + else { + cell->setPort(RTLIL::escape_id("feedback_i"), RTLIL::SigSpec(RTLIL::S0, 3)); + } + + // Connect control ports + cell->setPort(RTLIL::escape_id("unsigned_a_i"), RTLIL::SigSpec(a_signed ? RTLIL::S0 : RTLIL::S1)); + cell->setPort(RTLIL::escape_id("unsigned_b_i"), RTLIL::SigSpec(b_signed ? RTLIL::S0 : RTLIL::S1)); + + // Connect config bits + if (use_dsp_cfg_params) { + cell->setParam(RTLIL::escape_id("SATURATE_ENABLE"), RTLIL::Const(RTLIL::S0)); + cell->setParam(RTLIL::escape_id("SHIFT_RIGHT"), RTLIL::Const(RTLIL::S0, 6)); + cell->setParam(RTLIL::escape_id("ROUND"), RTLIL::Const(RTLIL::S0)); + cell->setParam(RTLIL::escape_id("REGISTER_INPUTS"), RTLIL::Const(RTLIL::S0)); + // 3 - output post acc; 1 - output pre acc + cell->setParam(RTLIL::escape_id("OUTPUT_SELECT"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); + } else { + cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6)); + cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0)); + // 3 - output post acc; 1 - output pre acc + cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); + } + + bool subtract = (st.add->type == RTLIL::escape_id("$sub")); + cell->setPort(RTLIL::escape_id("subtract_i"), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); + + // Mark the cells for removal + pm.autoremove(st.mul); + pm.autoremove(st.add); + if (st.mux != nullptr) { + pm.autoremove(st.mux); + } + pm.autoremove(st.ff); +} + +struct QlDspMacc : public Pass { + + QlDspMacc() : Pass("ql_dsp_macc", "Does something") {} + + void help() override + { + log("\n"); + log(" ql_dsp_macc [options] [selection]\n"); + log("\n"); + log(" -use_dsp_cfg_params\n"); + log(" By default use DSP blocks with configuration bits available at module ports.\n"); + log(" Specifying this forces usage of DSP block with configuration bits available as module parameters\n"); + log("\n"); + } + + void clear_flags() override { use_dsp_cfg_params = false; } + + void execute(std::vector a_Args, RTLIL::Design *a_Design) override + { + log_header(a_Design, "Executing QL_DSP_MACC pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < a_Args.size(); argidx++) { + if (a_Args[argidx] == "-use_dsp_cfg_params") { + use_dsp_cfg_params = true; + continue; + } + + break; + } + extra_args(a_Args, argidx, a_Design); + + for (auto module : a_Design->selected_modules()) { + ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp); + } + } + +} QlDspMacc; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/ql_dsp_macc.pmg b/techlibs/quicklogic/ql_dsp_macc.pmg new file mode 100644 index 00000000000..4cfd15a2436 --- /dev/null +++ b/techlibs/quicklogic/ql_dsp_macc.pmg @@ -0,0 +1,50 @@ +pattern ql_dsp_macc + +state add_ba +state mux_ab + +state mul_nusers +state add_nusers +state mux_nusers +state ff_d_nusers +state ff_q_nusers + +match mul + select mul->type.in($mul) + select nusers(port(mul, \Y)) <= 3 + set mul_nusers nusers(port(mul, \Y)) +endmatch + +match add + select add->type.in($add, $sub) + choice AB {\A, \B} + define BA (AB == \A ? \B : \A) + index port(add, AB) === port(mul, \Y) + select nusers(port(add, \Y)) <= 3 + set add_nusers nusers(port(add, \Y)) + set add_ba BA +endmatch + +match mux + select mux->type.in($mux) + choice AB {\A, \B} + define BA (AB == \A ? \B : \A) + index port(mux, AB) === port(mul, \Y) + index port(mux, BA) === port(add, \Y) + select nusers(port(mux, \Y)) <= 3 + set mux_nusers nusers(port(mux, \Y)) + set mux_ab AB + optional +endmatch + +match ff + select ff->type.in($dff, $adff, $dffe, $adffe) + index port(ff, \D) === (mux == nullptr ? port(add, \Y) : port(mux, \Y)) + index port(ff, \Q) === port(add, add_ba) + set ff_d_nusers nusers(port(ff, \D)) + set ff_q_nusers nusers(port(ff, \Q)) +endmatch + +code + accept; +endcode diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc new file mode 100644 index 00000000000..5213aa1c4ac --- /dev/null +++ b/techlibs/quicklogic/ql_dsp_simd.cc @@ -0,0 +1,359 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#define MODE_BITS_BASE_SIZE 80 +#define MODE_BITS_EXTENSION_SIZE 13 + +// ============================================================================ + +struct QlDspSimdPass : public Pass { + + QlDspSimdPass() : Pass("ql_dsp_simd", "Infers QuickLogic k6n10f DSP pairs that can operate in SIMD mode") {} + + void help() override + { + log("\n"); + log(" ql_dsp_simd [selection]\n"); + log("\n"); + log(" This pass identifies k6n10f DSP cells with identical configuration\n"); + log(" and packs pairs of them together into other DSP cells that can\n"); + log(" perform SIMD operation.\n"); + } + + // .......................................... + + /// Describes DSP config unique to a whole DSP cell + struct DspConfig { + + // Port connections + dict connections; + + // Whether DSPs pass configuration bits through ports of parameters + bool use_cfg_params; + + // TODO: Possibly include parameters here. For now we have just + // connections. + + DspConfig() = default; + + DspConfig(const DspConfig &ref) = default; + DspConfig(DspConfig &&ref) = default; + + unsigned int hash() const { return connections.hash(); } + + bool operator==(const DspConfig &ref) const { return connections == ref.connections && use_cfg_params == ref.use_cfg_params; } + }; + + // .......................................... + + // DSP control and config ports to consider and how to map them to ports + // of the target DSP cell + const std::vector> m_DspCfgPorts = {std::make_pair("clock_i", "clk"), + std::make_pair("reset_i", "reset"), + + std::make_pair("feedback_i", "feedback"), + std::make_pair("load_acc_i", "load_acc"), + std::make_pair("unsigned_a_i", "unsigned_a"), + std::make_pair("unsigned_b_i", "unsigned_b"), + + std::make_pair("subtract_i", "subtract")}; + // For QL_DSP2 expand with configuration ports + const std::vector> m_DspCfgPorts_expand = { + std::make_pair("output_select_i", "output_select"), std::make_pair("saturate_enable_i", "saturate_enable"), + std::make_pair("shift_right_i", "shift_right"), std::make_pair("round_i", "round"), std::make_pair("register_inputs_i", "register_inputs")}; + + // For QL_DSP3 use parameters instead + const std::vector m_DspParams2Mode = {"OUTPUT_SELECT", "SATURATE_ENABLE", "SHIFT_RIGHT", "ROUND", "REGISTER_INPUTS"}; + + // DSP data ports and how to map them to ports of the target DSP cell + const std::vector> m_DspDataPorts = { + std::make_pair("a_i", "a"), std::make_pair("b_i", "b"), std::make_pair("acc_fir_i", "acc_fir"), + std::make_pair("z_o", "z"), std::make_pair("dly_b_o", "dly_b"), + }; + + // DSP parameters + const std::vector m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"}; + + // Source DSP cell type (SISD) + const std::string m_SisdDspType = "dsp_t1_10x9x32"; + // Suffix for DSP cell with configuration parameters + const std::string m_SisdDspType_cfg_params_suffix = "_cfg_params"; + + // Target DSP cell types for the SIMD mode + const std::string m_SimdDspType_cfg_ports = "QL_DSP2"; + const std::string m_SimdDspType_cfg_params = "QL_DSP3"; + + /// Temporary SigBit to SigBit helper map. + SigMap m_SigMap; + + // .......................................... + + void execute(std::vector a_Args, RTLIL::Design *a_Design) override + { + log_header(a_Design, "Executing QL_DSP_SIMD pass.\n"); + + // Parse args + extra_args(a_Args, 1, a_Design); + + // Process modules + for (auto module : a_Design->selected_modules()) { + + // Setup the SigMap + m_SigMap.clear(); + m_SigMap.set(module); + + // Assemble DSP cell groups + dict> groups; + for (auto cell : module->selected_cells()) { + + // Check if this is a DSP cell we are looking for (type starts with m_SisdDspType) + if (strncmp(cell->type.c_str(), RTLIL::escape_id(m_SisdDspType).c_str(), RTLIL::escape_id(m_SisdDspType).size()) != 0) { + continue; + } + + // Skip if it has the (* keep *) attribute set + if (cell->has_keep_attr()) { + continue; + } + + // Add to a group + const auto key = getDspConfig(cell); + groups[key].push_back(cell); + } + + std::vector cellsToRemove; + + // Map cell pairs to the target DSP SIMD cell + for (const auto &it : groups) { + const auto &group = it.second; + const auto &config = it.first; + + bool use_cfg_params = config.use_cfg_params; + // Ensure an even number + size_t count = group.size(); + if (count & 1) + count--; + + // Map SIMD pairs + for (size_t i = 0; i < count; i += 2) { + const RTLIL::Cell *dsp_a = group[i]; + const RTLIL::Cell *dsp_b = group[i + 1]; + + std::string name = stringf("simd%ld", i / 2); + std::string SimdDspType; + + if (use_cfg_params) + SimdDspType = m_SimdDspType_cfg_params; + else + SimdDspType = m_SimdDspType_cfg_ports; + + log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", RTLIL::unescape_id(dsp_a->name).c_str(), RTLIL::unescape_id(dsp_a->type).c_str(), + RTLIL::unescape_id(dsp_b->name).c_str(), RTLIL::unescape_id(dsp_b->type).c_str(), RTLIL::unescape_id(name).c_str(), + SimdDspType.c_str()); + + // Create the new cell + RTLIL::Cell *simd = module->addCell(RTLIL::escape_id(name), RTLIL::escape_id(SimdDspType)); + + // Check if the target cell is known (important to know + // its port widths) + if (!simd->known()) { + log_error(" The target cell type '%s' is not known!", SimdDspType.c_str()); + } + + std::vector> DspCfgPorts = m_DspCfgPorts; + if (!use_cfg_params) + DspCfgPorts.insert(DspCfgPorts.end(), m_DspCfgPorts_expand.begin(), m_DspCfgPorts_expand.end()); + + // Connect common ports + for (const auto &it : DspCfgPorts) { + auto sport = RTLIL::escape_id(it.first); + auto dport = RTLIL::escape_id(it.second); + + simd->setPort(dport, config.connections.at(sport)); + } + + // Connect data ports + for (const auto &it : m_DspDataPorts) { + auto sport = RTLIL::escape_id(it.first); + auto dport = RTLIL::escape_id(it.second); + + size_t width; + bool isOutput; + + std::tie(width, isOutput) = getPortInfo(simd, dport); + + auto getConnection = [&](const RTLIL::Cell *cell) { + RTLIL::SigSpec sigspec; + if (cell->hasPort(sport)) { + const auto &sig = cell->getPort(sport); + sigspec.append(sig); + } + if (sigspec.bits().size() < width / 2) { + if (isOutput) { + for (size_t i = 0; i < width / 2 - sigspec.bits().size(); ++i) { + sigspec.append(RTLIL::SigSpec()); + } + } else { + sigspec.append(RTLIL::SigSpec(RTLIL::Sx, width / 2 - sigspec.bits().size())); + } + } + return sigspec; + }; + + RTLIL::SigSpec sigspec; + sigspec.append(getConnection(dsp_a)); + sigspec.append(getConnection(dsp_b)); + simd->setPort(dport, sigspec); + } + + // Concatenate FIR coefficient parameters into the single + // MODE_BITS parameter + std::vector mode_bits; + for (const auto &it : m_DspParams) { + auto val_a = dsp_a->getParam(RTLIL::escape_id(it)); + auto val_b = dsp_b->getParam(RTLIL::escape_id(it)); + + mode_bits.insert(mode_bits.end(), val_a.begin(), val_a.end()); + mode_bits.insert(mode_bits.end(), val_b.begin(), val_b.end()); + } + long unsigned int mode_bits_size = MODE_BITS_BASE_SIZE; + if (use_cfg_params) { + // Add additional config parameters if necessary + mode_bits.push_back(RTLIL::S1); // MODE_BITS[80] == F_MODE : Enable fractured mode + for (const auto &it : m_DspParams2Mode) { + log_assert(dsp_a->getParam(RTLIL::escape_id(it)) == dsp_b->getParam(RTLIL::escape_id(it))); + auto param = dsp_a->getParam(RTLIL::escape_id(it)); + if (param.size() > 1) { + mode_bits.insert(mode_bits.end(), param.bits.begin(), param.bits.end()); + } else { + mode_bits.push_back(param.bits[0]); + } + } + mode_bits_size += MODE_BITS_EXTENSION_SIZE; + } else { + // Enable the fractured mode by connecting the control + // port. + simd->setPort(RTLIL::escape_id("f_mode"), RTLIL::S1); + } + simd->setParam(RTLIL::escape_id("MODE_BITS"), RTLIL::Const(mode_bits)); + log_assert(mode_bits.size() == mode_bits_size); + + // Handle the "is_inferred" attribute. If one of the fragments + // is not inferred mark the whole DSP as not inferred + bool is_inferred_a = + dsp_a->has_attribute(RTLIL::escape_id("is_inferred")) ? dsp_a->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false; + bool is_inferred_b = + dsp_b->has_attribute(RTLIL::escape_id("is_inferred")) ? dsp_b->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false; + + simd->set_bool_attribute(RTLIL::escape_id("is_inferred"), is_inferred_a && is_inferred_b); + + // Mark DSP parts for removal + cellsToRemove.push_back(dsp_a); + cellsToRemove.push_back(dsp_b); + } + } + + // Remove old cells + for (const auto &cell : cellsToRemove) { + module->remove(const_cast(cell)); + } + } + + // Clear + m_SigMap.clear(); + } + + // .......................................... + + /// Looks up port width and direction in the cell definition and returns it. + /// Returns (0, false) if it cannot be determined. + std::pair getPortInfo(RTLIL::Cell *a_Cell, RTLIL::IdString a_Port) + { + if (!a_Cell->known()) { + return std::make_pair(0, false); + } + + // Get the module defining the cell (the previous condition ensures + // that the pointers are valid) + RTLIL::Module *mod = a_Cell->module->design->module(a_Cell->type); + if (mod == nullptr) { + return std::make_pair(0, false); + } + + // Get the wire representing the port + RTLIL::Wire *wire = mod->wire(a_Port); + if (wire == nullptr) { + return std::make_pair(0, false); + } + + return std::make_pair(wire->width, wire->port_output); + } + + /// Given a DSP cell populates and returns a DspConfig struct for it. + DspConfig getDspConfig(RTLIL::Cell *a_Cell) + { + DspConfig config; + + string cell_type = a_Cell->type.str(); + string suffix = m_SisdDspType_cfg_params_suffix; + + bool use_cfg_params = cell_type.size() >= suffix.size() && 0 == cell_type.compare(cell_type.size() - suffix.size(), suffix.size(), suffix); + + std::vector> DspCfgPorts = m_DspCfgPorts; + if (!use_cfg_params) + DspCfgPorts.insert(DspCfgPorts.end(), m_DspCfgPorts_expand.begin(), m_DspCfgPorts_expand.end()); + + config.use_cfg_params = use_cfg_params; + + for (const auto &it : DspCfgPorts) { + auto port = RTLIL::escape_id(it.first); + + // Port unconnected + if (!a_Cell->hasPort(port)) { + config.connections[port] = RTLIL::SigSpec(RTLIL::Sx); + continue; + } + + // Get the port connection and map it to unique SigBits + const auto &orgSigSpec = a_Cell->getPort(port); + const auto &orgSigBits = orgSigSpec.bits(); + + RTLIL::SigSpec newSigSpec; + for (size_t i = 0; i < orgSigBits.size(); ++i) { + auto newSigBit = m_SigMap(orgSigBits[i]); + newSigSpec.append(newSigBit); + } + + // Store + config.connections[port] = newSigSpec; + } + + return config; + } + +} QlDspSimdPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v b/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v new file mode 100644 index 00000000000..9eae617b90f --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v @@ -0,0 +1,265 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module dsp_t1_20x18x64_cfg_ports ( + input [19:0] a_i, + input [17:0] b_i, + input [ 5:0] acc_fir_i, + output [37:0] z_o, + output [17:0] dly_b_o, + + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + + input [2:0] output_select_i, + input saturate_enable_i, + input [5:0] shift_right_i, + input round_i, + input subtract_i, + input register_inputs_i +); + + parameter [19:0] COEFF_0 = 20'd0; + parameter [19:0] COEFF_1 = 20'd0; + parameter [19:0] COEFF_2 = 20'd0; + parameter [19:0] COEFF_3 = 20'd0; + + QL_DSP2 # ( + .MODE_BITS ({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) _TECHMAP_REPLACE_ ( + .a (a_i), + .b (b_i), + .acc_fir (acc_fir_i), + .z (z_o), + .dly_b (dly_b_o), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + + .f_mode (1'b0), // No fracturation + .output_select (output_select_i), + .saturate_enable (saturate_enable_i), + .shift_right (shift_right_i), + .round (round_i), + .subtract (subtract_i), + .register_inputs (register_inputs_i) + ); + +endmodule + +module dsp_t1_10x9x32_cfg_ports ( + input [ 9:0] a_i, + input [ 8:0] b_i, + input [ 5:0] acc_fir_i, + output [18:0] z_o, + output [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + + input [2:0] output_select_i, + input saturate_enable_i, + input [5:0] shift_right_i, + input round_i, + input subtract_i, + input register_inputs_i +); + + parameter [9:0] COEFF_0 = 10'd0; + parameter [9:0] COEFF_1 = 10'd0; + parameter [9:0] COEFF_2 = 10'd0; + parameter [9:0] COEFF_3 = 10'd0; + + wire [37:0] z; + wire [17:0] dly_b; + + QL_DSP2 # ( + .MODE_BITS ({10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0}) + ) _TECHMAP_REPLACE_ ( + .a ({10'd0, a_i}), + .b ({ 9'd0, b_i}), + .acc_fir (acc_fir_i), + .z (z), + .dly_b (dly_b), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + + .f_mode (1'b1), // Enable fractuation, Use the lower half + .output_select (output_select_i), + .saturate_enable (saturate_enable_i), + .shift_right (shift_right_i), + .round (round_i), + .subtract (subtract_i), + .register_inputs (register_inputs_i) + ); + + assign z_o = z[18:0]; + assign dly_b_o = dly_b_o[8:0]; + +endmodule + +module dsp_t1_20x18x64_cfg_params ( + input [19:0] a_i, + input [17:0] b_i, + input [ 5:0] acc_fir_i, + output [37:0] z_o, + output [17:0] dly_b_o, + + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + input subtract_i +); + + parameter [19:0] COEFF_0 = 20'd0; + parameter [19:0] COEFF_1 = 20'd0; + parameter [19:0] COEFF_2 = 20'd0; + parameter [19:0] COEFF_3 = 20'd0; + + parameter [2:0] OUTPUT_SELECT = 3'd0; + parameter [0:0] SATURATE_ENABLE = 1'd0; + parameter [5:0] SHIFT_RIGHT = 6'd0; + parameter [0:0] ROUND = 1'd0; + parameter [0:0] REGISTER_INPUTS = 1'd0; + + QL_DSP3 # ( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b0, // Not fractured + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) _TECHMAP_REPLACE_ ( + .a (a_i), + .b (b_i), + .acc_fir (acc_fir_i), + .z (z_o), + .dly_b (dly_b_o), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + .subtract (subtract_i) + ); + +endmodule + +module dsp_t1_10x9x32_cfg_params ( + input [ 9:0] a_i, + input [ 8:0] b_i, + input [ 5:0] acc_fir_i, + output [18:0] z_o, + output [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + input subtract_i +); + + parameter [9:0] COEFF_0 = 10'd0; + parameter [9:0] COEFF_1 = 10'd0; + parameter [9:0] COEFF_2 = 10'd0; + parameter [9:0] COEFF_3 = 10'd0; + + parameter [2:0] OUTPUT_SELECT = 3'd0; + parameter [0:0] SATURATE_ENABLE = 1'd0; + parameter [5:0] SHIFT_RIGHT = 6'd0; + parameter [0:0] ROUND = 1'd0; + parameter [0:0] REGISTER_INPUTS = 1'd0; + + wire [37:0] z; + wire [17:0] dly_b; + + QL_DSP3 # ( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b1, // Fractured + 10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0 + }) + ) _TECHMAP_REPLACE_ ( + .a ({10'd0, a_i}), + .b ({ 9'd0, b_i}), + .acc_fir (acc_fir_i), + .z (z), + .dly_b (dly_b), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + .subtract (subtract_i) + ); + + assign z_o = z[18:0]; + assign dly_b_o = dly_b_o[8:0]; + +endmodule + diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_map.v b/techlibs/quicklogic/qlf_k6n10f/dsp_map.v new file mode 100644 index 00000000000..bb9f05283e7 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_map.v @@ -0,0 +1,147 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [19:0] a; + wire [17:0] b; + wire [37:0] z; + + assign a = (A_WIDTH == 20) ? A : + (A_SIGNED) ? {{(20 - A_WIDTH){A[A_WIDTH-1]}}, A} : + {{(20 - A_WIDTH){1'b0}}, A}; + + assign b = (B_WIDTH == 18) ? B : + (B_SIGNED) ? {{(18 - B_WIDTH){B[B_WIDTH-1]}}, B} : + {{(18 - B_WIDTH){1'b0}}, B}; + + generate if (`USE_DSP_CFG_PARAMS == 0) begin + (* is_inferred=1 *) + dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .output_select_i (3'd0), + .saturate_enable_i (1'b0), + .shift_right_i (6'd0), + .round_i (1'b0), + .subtract_i (1'b0), + .register_inputs_i (1'b0) + ); + end else begin + (* is_inferred=1 *) + dsp_t1_20x18x64_cfg_params #( + .OUTPUT_SELECT (3'd0), + .SATURATE_ENABLE (1'b0), + .SHIFT_RIGHT (6'd0), + .ROUND (1'b0), + .REGISTER_INPUTS (1'b0) + ) TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .subtract_i (1'b0) + ); + end endgenerate + + assign Y = z; + +endmodule + +module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [ 9:0] a; + wire [ 8:0] b; + wire [18:0] z; + + assign a = (A_WIDTH == 10) ? A : + (A_SIGNED) ? {{(10 - A_WIDTH){A[A_WIDTH-1]}}, A} : + {{(10 - A_WIDTH){1'b0}}, A}; + + assign b = (B_WIDTH == 9) ? B : + (B_SIGNED) ? {{( 9 - B_WIDTH){B[B_WIDTH-1]}}, B} : + {{( 9 - B_WIDTH){1'b0}}, B}; + + generate if (`USE_DSP_CFG_PARAMS == 0) begin + (* is_inferred=1 *) + dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .output_select_i (3'd0), + .saturate_enable_i (1'b0), + .shift_right_i (6'd0), + .round_i (1'b0), + .subtract_i (1'b0), + .register_inputs_i (1'b0) + ); + end else begin + (* is_inferred=1 *) + dsp_t1_10x9x32_cfg_params #( + .OUTPUT_SELECT (3'd0), + .SATURATE_ENABLE (1'b0), + .SHIFT_RIGHT (6'd0), + .ROUND (1'b0), + .REGISTER_INPUTS (1'b0) + ) TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .subtract_i (1'b0) + ); + end endgenerate + + assign Y = z; + +endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v b/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v new file mode 100644 index 00000000000..05a4835e868 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v @@ -0,0 +1,5753 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`timescale 1ps/1ps + +`default_nettype none + +(* blackbox *) +module QL_DSP1 ( + input wire [19:0] a, + input wire [17:0] b, + (* clkbuf_sink *) + input wire clk0, + (* clkbuf_sink *) + input wire clk1, + input wire [ 1:0] feedback0, + input wire [ 1:0] feedback1, + input wire load_acc0, + input wire load_acc1, + input wire reset0, + input wire reset1, + output reg [37:0] z +); + parameter MODE_BITS = 27'b00000000000000000000000000; +endmodule /* QL_DSP1 */ + + + +// ---------------------------------------- // +// ----- DSP cells simulation modules ----- // +// --------- Control bits in ports -------- // +// ---------------------------------------- // + +module QL_DSP2 ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + input wire [ 5:0] acc_fir, + output wire [37:0] z, + output wire [17:0] dly_b, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [2:0] output_select, + input wire saturate_enable, + input wire [5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam NBITS_ACC = 64; + localparam NBITS_A = 20; + localparam NBITS_B = 18; + localparam NBITS_Z = 38; + + wire [NBITS_Z-1:0] dsp_full_z; + wire [(NBITS_Z/2)-1:0] dsp_frac0_z; + wire [(NBITS_Z/2)-1:0] dsp_frac1_z; + + wire [NBITS_B-1:0] dsp_full_dly_b; + wire [(NBITS_B/2)-1:0] dsp_frac0_dly_b; + wire [(NBITS_B/2)-1:0] dsp_frac1_dly_b; + + assign z = f_mode ? {dsp_frac1_z, dsp_frac0_z} : dsp_full_z; + assign dly_b = f_mode ? {dsp_frac1_dly_b, dsp_frac0_dly_b} : dsp_full_dly_b; + + // Output used when fmode == 1 + dsp_t1_sim_cfg_ports #( + .NBITS_A(NBITS_A/2), + .NBITS_B(NBITS_B/2), + .NBITS_ACC(NBITS_ACC/2), + .NBITS_Z(NBITS_Z/2) + ) dsp_frac0 ( + .a_i(a[(NBITS_A/2)-1:0]), + .b_i(b[(NBITS_B/2)-1:0]), + .z_o(dsp_frac0_z), + .dly_b_o(dsp_frac0_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .saturate_enable_i(saturate_enable), + .output_select_i(output_select), + .round_i(round), + .shift_right_i(shift_right), + .subtract_i(subtract), + .register_inputs_i(register_inputs), + .coef_0_i(COEFF_0[(NBITS_A/2)-1:0]), + .coef_1_i(COEFF_1[(NBITS_A/2)-1:0]), + .coef_2_i(COEFF_2[(NBITS_A/2)-1:0]), + .coef_3_i(COEFF_3[(NBITS_A/2)-1:0]) + ); + + // Output used when fmode == 1 + dsp_t1_sim_cfg_ports #( + .NBITS_A(NBITS_A/2), + .NBITS_B(NBITS_B/2), + .NBITS_ACC(NBITS_ACC/2), + .NBITS_Z(NBITS_Z/2) + ) dsp_frac1 ( + .a_i(a[NBITS_A-1:NBITS_A/2]), + .b_i(b[NBITS_B-1:NBITS_B/2]), + .z_o(dsp_frac1_z), + .dly_b_o(dsp_frac1_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .saturate_enable_i(saturate_enable), + .output_select_i(output_select), + .round_i(round), + .shift_right_i(shift_right), + .subtract_i(subtract), + .register_inputs_i(register_inputs), + .coef_0_i(COEFF_0[NBITS_A-1:NBITS_A/2]), + .coef_1_i(COEFF_1[NBITS_A-1:NBITS_A/2]), + .coef_2_i(COEFF_2[NBITS_A-1:NBITS_A/2]), + .coef_3_i(COEFF_3[NBITS_A-1:NBITS_A/2]) + ); + + // Output used when fmode == 0 + dsp_t1_sim_cfg_ports #( + .NBITS_A(NBITS_A), + .NBITS_B(NBITS_B), + .NBITS_ACC(NBITS_ACC), + .NBITS_Z(NBITS_Z) + ) dsp_full ( + .a_i(a), + .b_i(b), + .z_o(dsp_full_z), + .dly_b_o(dsp_full_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .saturate_enable_i(saturate_enable), + .output_select_i(output_select), + .round_i(round), + .shift_right_i(shift_right), + .subtract_i(subtract), + .register_inputs_i(register_inputs), + .coef_0_i(COEFF_0), + .coef_1_i(COEFF_1), + .coef_2_i(COEFF_2), + .coef_3_i(COEFF_3) + ); +endmodule + +module QL_DSP2_MULT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .clk(1'b0), + .reset(reset), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .output_select(output_select), // unregistered output: a * b (0) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (a[0] => z[0]) = 0; + (a[1] => z[0]) = 0; + (a[2] => z[0]) = 0; + (a[3] => z[0]) = 0; + (a[4] => z[0]) = 0; + (a[5] => z[0]) = 0; + (a[6] => z[0]) = 0; + (a[7] => z[0]) = 0; + (a[8] => z[0]) = 0; + (a[9] => z[0]) = 0; + (a[10] => z[0]) = 0; + (a[11] => z[0]) = 0; + (a[12] => z[0]) = 0; + (a[13] => z[0]) = 0; + (a[14] => z[0]) = 0; + (a[15] => z[0]) = 0; + (a[16] => z[0]) = 0; + (a[17] => z[0]) = 0; + (a[18] => z[0]) = 0; + (a[19] => z[0]) = 0; + (b[0] => z[0]) = 0; + (b[1] => z[0]) = 0; + (b[2] => z[0]) = 0; + (b[3] => z[0]) = 0; + (b[4] => z[0]) = 0; + (b[5] => z[0]) = 0; + (b[6] => z[0]) = 0; + (b[7] => z[0]) = 0; + (b[8] => z[0]) = 0; + (b[9] => z[0]) = 0; + (b[10] => z[0]) = 0; + (b[11] => z[0]) = 0; + (b[12] => z[0]) = 0; + (b[13] => z[0]) = 0; + (b[14] => z[0]) = 0; + (b[15] => z[0]) = 0; + (b[16] => z[0]) = 0; + (b[17] => z[0]) = 0; + (a[0] => z[1]) = 0; + (a[1] => z[1]) = 0; + (a[2] => z[1]) = 0; + (a[3] => z[1]) = 0; + (a[4] => z[1]) = 0; + (a[5] => z[1]) = 0; + (a[6] => z[1]) = 0; + (a[7] => z[1]) = 0; + (a[8] => z[1]) = 0; + (a[9] => z[1]) = 0; + (a[10] => z[1]) = 0; + (a[11] => z[1]) = 0; + (a[12] => z[1]) = 0; + (a[13] => z[1]) = 0; + (a[14] => z[1]) = 0; + (a[15] => z[1]) = 0; + (a[16] => z[1]) = 0; + (a[17] => z[1]) = 0; + (a[18] => z[1]) = 0; + (a[19] => z[1]) = 0; + (b[0] => z[1]) = 0; + (b[1] => z[1]) = 0; + (b[2] => z[1]) = 0; + (b[3] => z[1]) = 0; + (b[4] => z[1]) = 0; + (b[5] => z[1]) = 0; + (b[6] => z[1]) = 0; + (b[7] => z[1]) = 0; + (b[8] => z[1]) = 0; + (b[9] => z[1]) = 0; + (b[10] => z[1]) = 0; + (b[11] => z[1]) = 0; + (b[12] => z[1]) = 0; + (b[13] => z[1]) = 0; + (b[14] => z[1]) = 0; + (b[15] => z[1]) = 0; + (b[16] => z[1]) = 0; + (b[17] => z[1]) = 0; + (a[0] => z[2]) = 0; + (a[1] => z[2]) = 0; + (a[2] => z[2]) = 0; + (a[3] => z[2]) = 0; + (a[4] => z[2]) = 0; + (a[5] => z[2]) = 0; + (a[6] => z[2]) = 0; + (a[7] => z[2]) = 0; + (a[8] => z[2]) = 0; + (a[9] => z[2]) = 0; + (a[10] => z[2]) = 0; + (a[11] => z[2]) = 0; + (a[12] => z[2]) = 0; + (a[13] => z[2]) = 0; + (a[14] => z[2]) = 0; + (a[15] => z[2]) = 0; + (a[16] => z[2]) = 0; + (a[17] => z[2]) = 0; + (a[18] => z[2]) = 0; + (a[19] => z[2]) = 0; + (b[0] => z[2]) = 0; + (b[1] => z[2]) = 0; + (b[2] => z[2]) = 0; + (b[3] => z[2]) = 0; + (b[4] => z[2]) = 0; + (b[5] => z[2]) = 0; + (b[6] => z[2]) = 0; + (b[7] => z[2]) = 0; + (b[8] => z[2]) = 0; + (b[9] => z[2]) = 0; + (b[10] => z[2]) = 0; + (b[11] => z[2]) = 0; + (b[12] => z[2]) = 0; + (b[13] => z[2]) = 0; + (b[14] => z[2]) = 0; + (b[15] => z[2]) = 0; + (b[16] => z[2]) = 0; + (b[17] => z[2]) = 0; + (a[0] => z[3]) = 0; + (a[1] => z[3]) = 0; + (a[2] => z[3]) = 0; + (a[3] => z[3]) = 0; + (a[4] => z[3]) = 0; + (a[5] => z[3]) = 0; + (a[6] => z[3]) = 0; + (a[7] => z[3]) = 0; + (a[8] => z[3]) = 0; + (a[9] => z[3]) = 0; + (a[10] => z[3]) = 0; + (a[11] => z[3]) = 0; + (a[12] => z[3]) = 0; + (a[13] => z[3]) = 0; + (a[14] => z[3]) = 0; + (a[15] => z[3]) = 0; + (a[16] => z[3]) = 0; + (a[17] => z[3]) = 0; + (a[18] => z[3]) = 0; + (a[19] => z[3]) = 0; + (b[0] => z[3]) = 0; + (b[1] => z[3]) = 0; + (b[2] => z[3]) = 0; + (b[3] => z[3]) = 0; + (b[4] => z[3]) = 0; + (b[5] => z[3]) = 0; + (b[6] => z[3]) = 0; + (b[7] => z[3]) = 0; + (b[8] => z[3]) = 0; + (b[9] => z[3]) = 0; + (b[10] => z[3]) = 0; + (b[11] => z[3]) = 0; + (b[12] => z[3]) = 0; + (b[13] => z[3]) = 0; + (b[14] => z[3]) = 0; + (b[15] => z[3]) = 0; + (b[16] => z[3]) = 0; + (b[17] => z[3]) = 0; + (a[0] => z[4]) = 0; + (a[1] => z[4]) = 0; + (a[2] => z[4]) = 0; + (a[3] => z[4]) = 0; + (a[4] => z[4]) = 0; + (a[5] => z[4]) = 0; + (a[6] => z[4]) = 0; + (a[7] => z[4]) = 0; + (a[8] => z[4]) = 0; + (a[9] => z[4]) = 0; + (a[10] => z[4]) = 0; + (a[11] => z[4]) = 0; + (a[12] => z[4]) = 0; + (a[13] => z[4]) = 0; + (a[14] => z[4]) = 0; + (a[15] => z[4]) = 0; + (a[16] => z[4]) = 0; + (a[17] => z[4]) = 0; + (a[18] => z[4]) = 0; + (a[19] => z[4]) = 0; + (b[0] => z[4]) = 0; + (b[1] => z[4]) = 0; + (b[2] => z[4]) = 0; + (b[3] => z[4]) = 0; + (b[4] => z[4]) = 0; + (b[5] => z[4]) = 0; + (b[6] => z[4]) = 0; + (b[7] => z[4]) = 0; + (b[8] => z[4]) = 0; + (b[9] => z[4]) = 0; + (b[10] => z[4]) = 0; + (b[11] => z[4]) = 0; + (b[12] => z[4]) = 0; + (b[13] => z[4]) = 0; + (b[14] => z[4]) = 0; + (b[15] => z[4]) = 0; + (b[16] => z[4]) = 0; + (b[17] => z[4]) = 0; + (a[0] => z[5]) = 0; + (a[1] => z[5]) = 0; + (a[2] => z[5]) = 0; + (a[3] => z[5]) = 0; + (a[4] => z[5]) = 0; + (a[5] => z[5]) = 0; + (a[6] => z[5]) = 0; + (a[7] => z[5]) = 0; + (a[8] => z[5]) = 0; + (a[9] => z[5]) = 0; + (a[10] => z[5]) = 0; + (a[11] => z[5]) = 0; + (a[12] => z[5]) = 0; + (a[13] => z[5]) = 0; + (a[14] => z[5]) = 0; + (a[15] => z[5]) = 0; + (a[16] => z[5]) = 0; + (a[17] => z[5]) = 0; + (a[18] => z[5]) = 0; + (a[19] => z[5]) = 0; + (b[0] => z[5]) = 0; + (b[1] => z[5]) = 0; + (b[2] => z[5]) = 0; + (b[3] => z[5]) = 0; + (b[4] => z[5]) = 0; + (b[5] => z[5]) = 0; + (b[6] => z[5]) = 0; + (b[7] => z[5]) = 0; + (b[8] => z[5]) = 0; + (b[9] => z[5]) = 0; + (b[10] => z[5]) = 0; + (b[11] => z[5]) = 0; + (b[12] => z[5]) = 0; + (b[13] => z[5]) = 0; + (b[14] => z[5]) = 0; + (b[15] => z[5]) = 0; + (b[16] => z[5]) = 0; + (b[17] => z[5]) = 0; + (a[0] => z[6]) = 0; + (a[1] => z[6]) = 0; + (a[2] => z[6]) = 0; + (a[3] => z[6]) = 0; + (a[4] => z[6]) = 0; + (a[5] => z[6]) = 0; + (a[6] => z[6]) = 0; + (a[7] => z[6]) = 0; + (a[8] => z[6]) = 0; + (a[9] => z[6]) = 0; + (a[10] => z[6]) = 0; + (a[11] => z[6]) = 0; + (a[12] => z[6]) = 0; + (a[13] => z[6]) = 0; + (a[14] => z[6]) = 0; + (a[15] => z[6]) = 0; + (a[16] => z[6]) = 0; + (a[17] => z[6]) = 0; + (a[18] => z[6]) = 0; + (a[19] => z[6]) = 0; + (b[0] => z[6]) = 0; + (b[1] => z[6]) = 0; + (b[2] => z[6]) = 0; + (b[3] => z[6]) = 0; + (b[4] => z[6]) = 0; + (b[5] => z[6]) = 0; + (b[6] => z[6]) = 0; + (b[7] => z[6]) = 0; + (b[8] => z[6]) = 0; + (b[9] => z[6]) = 0; + (b[10] => z[6]) = 0; + (b[11] => z[6]) = 0; + (b[12] => z[6]) = 0; + (b[13] => z[6]) = 0; + (b[14] => z[6]) = 0; + (b[15] => z[6]) = 0; + (b[16] => z[6]) = 0; + (b[17] => z[6]) = 0; + (a[0] => z[7]) = 0; + (a[1] => z[7]) = 0; + (a[2] => z[7]) = 0; + (a[3] => z[7]) = 0; + (a[4] => z[7]) = 0; + (a[5] => z[7]) = 0; + (a[6] => z[7]) = 0; + (a[7] => z[7]) = 0; + (a[8] => z[7]) = 0; + (a[9] => z[7]) = 0; + (a[10] => z[7]) = 0; + (a[11] => z[7]) = 0; + (a[12] => z[7]) = 0; + (a[13] => z[7]) = 0; + (a[14] => z[7]) = 0; + (a[15] => z[7]) = 0; + (a[16] => z[7]) = 0; + (a[17] => z[7]) = 0; + (a[18] => z[7]) = 0; + (a[19] => z[7]) = 0; + (b[0] => z[7]) = 0; + (b[1] => z[7]) = 0; + (b[2] => z[7]) = 0; + (b[3] => z[7]) = 0; + (b[4] => z[7]) = 0; + (b[5] => z[7]) = 0; + (b[6] => z[7]) = 0; + (b[7] => z[7]) = 0; + (b[8] => z[7]) = 0; + (b[9] => z[7]) = 0; + (b[10] => z[7]) = 0; + (b[11] => z[7]) = 0; + (b[12] => z[7]) = 0; + (b[13] => z[7]) = 0; + (b[14] => z[7]) = 0; + (b[15] => z[7]) = 0; + (b[16] => z[7]) = 0; + (b[17] => z[7]) = 0; + (a[0] => z[8]) = 0; + (a[1] => z[8]) = 0; + (a[2] => z[8]) = 0; + (a[3] => z[8]) = 0; + (a[4] => z[8]) = 0; + (a[5] => z[8]) = 0; + (a[6] => z[8]) = 0; + (a[7] => z[8]) = 0; + (a[8] => z[8]) = 0; + (a[9] => z[8]) = 0; + (a[10] => z[8]) = 0; + (a[11] => z[8]) = 0; + (a[12] => z[8]) = 0; + (a[13] => z[8]) = 0; + (a[14] => z[8]) = 0; + (a[15] => z[8]) = 0; + (a[16] => z[8]) = 0; + (a[17] => z[8]) = 0; + (a[18] => z[8]) = 0; + (a[19] => z[8]) = 0; + (b[0] => z[8]) = 0; + (b[1] => z[8]) = 0; + (b[2] => z[8]) = 0; + (b[3] => z[8]) = 0; + (b[4] => z[8]) = 0; + (b[5] => z[8]) = 0; + (b[6] => z[8]) = 0; + (b[7] => z[8]) = 0; + (b[8] => z[8]) = 0; + (b[9] => z[8]) = 0; + (b[10] => z[8]) = 0; + (b[11] => z[8]) = 0; + (b[12] => z[8]) = 0; + (b[13] => z[8]) = 0; + (b[14] => z[8]) = 0; + (b[15] => z[8]) = 0; + (b[16] => z[8]) = 0; + (b[17] => z[8]) = 0; + (a[0] => z[9]) = 0; + (a[1] => z[9]) = 0; + (a[2] => z[9]) = 0; + (a[3] => z[9]) = 0; + (a[4] => z[9]) = 0; + (a[5] => z[9]) = 0; + (a[6] => z[9]) = 0; + (a[7] => z[9]) = 0; + (a[8] => z[9]) = 0; + (a[9] => z[9]) = 0; + (a[10] => z[9]) = 0; + (a[11] => z[9]) = 0; + (a[12] => z[9]) = 0; + (a[13] => z[9]) = 0; + (a[14] => z[9]) = 0; + (a[15] => z[9]) = 0; + (a[16] => z[9]) = 0; + (a[17] => z[9]) = 0; + (a[18] => z[9]) = 0; + (a[19] => z[9]) = 0; + (b[0] => z[9]) = 0; + (b[1] => z[9]) = 0; + (b[2] => z[9]) = 0; + (b[3] => z[9]) = 0; + (b[4] => z[9]) = 0; + (b[5] => z[9]) = 0; + (b[6] => z[9]) = 0; + (b[7] => z[9]) = 0; + (b[8] => z[9]) = 0; + (b[9] => z[9]) = 0; + (b[10] => z[9]) = 0; + (b[11] => z[9]) = 0; + (b[12] => z[9]) = 0; + (b[13] => z[9]) = 0; + (b[14] => z[9]) = 0; + (b[15] => z[9]) = 0; + (b[16] => z[9]) = 0; + (b[17] => z[9]) = 0; + (a[0] => z[10]) = 0; + (a[1] => z[10]) = 0; + (a[2] => z[10]) = 0; + (a[3] => z[10]) = 0; + (a[4] => z[10]) = 0; + (a[5] => z[10]) = 0; + (a[6] => z[10]) = 0; + (a[7] => z[10]) = 0; + (a[8] => z[10]) = 0; + (a[9] => z[10]) = 0; + (a[10] => z[10]) = 0; + (a[11] => z[10]) = 0; + (a[12] => z[10]) = 0; + (a[13] => z[10]) = 0; + (a[14] => z[10]) = 0; + (a[15] => z[10]) = 0; + (a[16] => z[10]) = 0; + (a[17] => z[10]) = 0; + (a[18] => z[10]) = 0; + (a[19] => z[10]) = 0; + (b[0] => z[10]) = 0; + (b[1] => z[10]) = 0; + (b[2] => z[10]) = 0; + (b[3] => z[10]) = 0; + (b[4] => z[10]) = 0; + (b[5] => z[10]) = 0; + (b[6] => z[10]) = 0; + (b[7] => z[10]) = 0; + (b[8] => z[10]) = 0; + (b[9] => z[10]) = 0; + (b[10] => z[10]) = 0; + (b[11] => z[10]) = 0; + (b[12] => z[10]) = 0; + (b[13] => z[10]) = 0; + (b[14] => z[10]) = 0; + (b[15] => z[10]) = 0; + (b[16] => z[10]) = 0; + (b[17] => z[10]) = 0; + (a[0] => z[11]) = 0; + (a[1] => z[11]) = 0; + (a[2] => z[11]) = 0; + (a[3] => z[11]) = 0; + (a[4] => z[11]) = 0; + (a[5] => z[11]) = 0; + (a[6] => z[11]) = 0; + (a[7] => z[11]) = 0; + (a[8] => z[11]) = 0; + (a[9] => z[11]) = 0; + (a[10] => z[11]) = 0; + (a[11] => z[11]) = 0; + (a[12] => z[11]) = 0; + (a[13] => z[11]) = 0; + (a[14] => z[11]) = 0; + (a[15] => z[11]) = 0; + (a[16] => z[11]) = 0; + (a[17] => z[11]) = 0; + (a[18] => z[11]) = 0; + (a[19] => z[11]) = 0; + (b[0] => z[11]) = 0; + (b[1] => z[11]) = 0; + (b[2] => z[11]) = 0; + (b[3] => z[11]) = 0; + (b[4] => z[11]) = 0; + (b[5] => z[11]) = 0; + (b[6] => z[11]) = 0; + (b[7] => z[11]) = 0; + (b[8] => z[11]) = 0; + (b[9] => z[11]) = 0; + (b[10] => z[11]) = 0; + (b[11] => z[11]) = 0; + (b[12] => z[11]) = 0; + (b[13] => z[11]) = 0; + (b[14] => z[11]) = 0; + (b[15] => z[11]) = 0; + (b[16] => z[11]) = 0; + (b[17] => z[11]) = 0; + (a[0] => z[12]) = 0; + (a[1] => z[12]) = 0; + (a[2] => z[12]) = 0; + (a[3] => z[12]) = 0; + (a[4] => z[12]) = 0; + (a[5] => z[12]) = 0; + (a[6] => z[12]) = 0; + (a[7] => z[12]) = 0; + (a[8] => z[12]) = 0; + (a[9] => z[12]) = 0; + (a[10] => z[12]) = 0; + (a[11] => z[12]) = 0; + (a[12] => z[12]) = 0; + (a[13] => z[12]) = 0; + (a[14] => z[12]) = 0; + (a[15] => z[12]) = 0; + (a[16] => z[12]) = 0; + (a[17] => z[12]) = 0; + (a[18] => z[12]) = 0; + (a[19] => z[12]) = 0; + (b[0] => z[12]) = 0; + (b[1] => z[12]) = 0; + (b[2] => z[12]) = 0; + (b[3] => z[12]) = 0; + (b[4] => z[12]) = 0; + (b[5] => z[12]) = 0; + (b[6] => z[12]) = 0; + (b[7] => z[12]) = 0; + (b[8] => z[12]) = 0; + (b[9] => z[12]) = 0; + (b[10] => z[12]) = 0; + (b[11] => z[12]) = 0; + (b[12] => z[12]) = 0; + (b[13] => z[12]) = 0; + (b[14] => z[12]) = 0; + (b[15] => z[12]) = 0; + (b[16] => z[12]) = 0; + (b[17] => z[12]) = 0; + (a[0] => z[13]) = 0; + (a[1] => z[13]) = 0; + (a[2] => z[13]) = 0; + (a[3] => z[13]) = 0; + (a[4] => z[13]) = 0; + (a[5] => z[13]) = 0; + (a[6] => z[13]) = 0; + (a[7] => z[13]) = 0; + (a[8] => z[13]) = 0; + (a[9] => z[13]) = 0; + (a[10] => z[13]) = 0; + (a[11] => z[13]) = 0; + (a[12] => z[13]) = 0; + (a[13] => z[13]) = 0; + (a[14] => z[13]) = 0; + (a[15] => z[13]) = 0; + (a[16] => z[13]) = 0; + (a[17] => z[13]) = 0; + (a[18] => z[13]) = 0; + (a[19] => z[13]) = 0; + (b[0] => z[13]) = 0; + (b[1] => z[13]) = 0; + (b[2] => z[13]) = 0; + (b[3] => z[13]) = 0; + (b[4] => z[13]) = 0; + (b[5] => z[13]) = 0; + (b[6] => z[13]) = 0; + (b[7] => z[13]) = 0; + (b[8] => z[13]) = 0; + (b[9] => z[13]) = 0; + (b[10] => z[13]) = 0; + (b[11] => z[13]) = 0; + (b[12] => z[13]) = 0; + (b[13] => z[13]) = 0; + (b[14] => z[13]) = 0; + (b[15] => z[13]) = 0; + (b[16] => z[13]) = 0; + (b[17] => z[13]) = 0; + (a[0] => z[14]) = 0; + (a[1] => z[14]) = 0; + (a[2] => z[14]) = 0; + (a[3] => z[14]) = 0; + (a[4] => z[14]) = 0; + (a[5] => z[14]) = 0; + (a[6] => z[14]) = 0; + (a[7] => z[14]) = 0; + (a[8] => z[14]) = 0; + (a[9] => z[14]) = 0; + (a[10] => z[14]) = 0; + (a[11] => z[14]) = 0; + (a[12] => z[14]) = 0; + (a[13] => z[14]) = 0; + (a[14] => z[14]) = 0; + (a[15] => z[14]) = 0; + (a[16] => z[14]) = 0; + (a[17] => z[14]) = 0; + (a[18] => z[14]) = 0; + (a[19] => z[14]) = 0; + (b[0] => z[14]) = 0; + (b[1] => z[14]) = 0; + (b[2] => z[14]) = 0; + (b[3] => z[14]) = 0; + (b[4] => z[14]) = 0; + (b[5] => z[14]) = 0; + (b[6] => z[14]) = 0; + (b[7] => z[14]) = 0; + (b[8] => z[14]) = 0; + (b[9] => z[14]) = 0; + (b[10] => z[14]) = 0; + (b[11] => z[14]) = 0; + (b[12] => z[14]) = 0; + (b[13] => z[14]) = 0; + (b[14] => z[14]) = 0; + (b[15] => z[14]) = 0; + (b[16] => z[14]) = 0; + (b[17] => z[14]) = 0; + (a[0] => z[15]) = 0; + (a[1] => z[15]) = 0; + (a[2] => z[15]) = 0; + (a[3] => z[15]) = 0; + (a[4] => z[15]) = 0; + (a[5] => z[15]) = 0; + (a[6] => z[15]) = 0; + (a[7] => z[15]) = 0; + (a[8] => z[15]) = 0; + (a[9] => z[15]) = 0; + (a[10] => z[15]) = 0; + (a[11] => z[15]) = 0; + (a[12] => z[15]) = 0; + (a[13] => z[15]) = 0; + (a[14] => z[15]) = 0; + (a[15] => z[15]) = 0; + (a[16] => z[15]) = 0; + (a[17] => z[15]) = 0; + (a[18] => z[15]) = 0; + (a[19] => z[15]) = 0; + (b[0] => z[15]) = 0; + (b[1] => z[15]) = 0; + (b[2] => z[15]) = 0; + (b[3] => z[15]) = 0; + (b[4] => z[15]) = 0; + (b[5] => z[15]) = 0; + (b[6] => z[15]) = 0; + (b[7] => z[15]) = 0; + (b[8] => z[15]) = 0; + (b[9] => z[15]) = 0; + (b[10] => z[15]) = 0; + (b[11] => z[15]) = 0; + (b[12] => z[15]) = 0; + (b[13] => z[15]) = 0; + (b[14] => z[15]) = 0; + (b[15] => z[15]) = 0; + (b[16] => z[15]) = 0; + (b[17] => z[15]) = 0; + (a[0] => z[16]) = 0; + (a[1] => z[16]) = 0; + (a[2] => z[16]) = 0; + (a[3] => z[16]) = 0; + (a[4] => z[16]) = 0; + (a[5] => z[16]) = 0; + (a[6] => z[16]) = 0; + (a[7] => z[16]) = 0; + (a[8] => z[16]) = 0; + (a[9] => z[16]) = 0; + (a[10] => z[16]) = 0; + (a[11] => z[16]) = 0; + (a[12] => z[16]) = 0; + (a[13] => z[16]) = 0; + (a[14] => z[16]) = 0; + (a[15] => z[16]) = 0; + (a[16] => z[16]) = 0; + (a[17] => z[16]) = 0; + (a[18] => z[16]) = 0; + (a[19] => z[16]) = 0; + (b[0] => z[16]) = 0; + (b[1] => z[16]) = 0; + (b[2] => z[16]) = 0; + (b[3] => z[16]) = 0; + (b[4] => z[16]) = 0; + (b[5] => z[16]) = 0; + (b[6] => z[16]) = 0; + (b[7] => z[16]) = 0; + (b[8] => z[16]) = 0; + (b[9] => z[16]) = 0; + (b[10] => z[16]) = 0; + (b[11] => z[16]) = 0; + (b[12] => z[16]) = 0; + (b[13] => z[16]) = 0; + (b[14] => z[16]) = 0; + (b[15] => z[16]) = 0; + (b[16] => z[16]) = 0; + (b[17] => z[16]) = 0; + (a[0] => z[17]) = 0; + (a[1] => z[17]) = 0; + (a[2] => z[17]) = 0; + (a[3] => z[17]) = 0; + (a[4] => z[17]) = 0; + (a[5] => z[17]) = 0; + (a[6] => z[17]) = 0; + (a[7] => z[17]) = 0; + (a[8] => z[17]) = 0; + (a[9] => z[17]) = 0; + (a[10] => z[17]) = 0; + (a[11] => z[17]) = 0; + (a[12] => z[17]) = 0; + (a[13] => z[17]) = 0; + (a[14] => z[17]) = 0; + (a[15] => z[17]) = 0; + (a[16] => z[17]) = 0; + (a[17] => z[17]) = 0; + (a[18] => z[17]) = 0; + (a[19] => z[17]) = 0; + (b[0] => z[17]) = 0; + (b[1] => z[17]) = 0; + (b[2] => z[17]) = 0; + (b[3] => z[17]) = 0; + (b[4] => z[17]) = 0; + (b[5] => z[17]) = 0; + (b[6] => z[17]) = 0; + (b[7] => z[17]) = 0; + (b[8] => z[17]) = 0; + (b[9] => z[17]) = 0; + (b[10] => z[17]) = 0; + (b[11] => z[17]) = 0; + (b[12] => z[17]) = 0; + (b[13] => z[17]) = 0; + (b[14] => z[17]) = 0; + (b[15] => z[17]) = 0; + (b[16] => z[17]) = 0; + (b[17] => z[17]) = 0; + (a[0] => z[18]) = 0; + (a[1] => z[18]) = 0; + (a[2] => z[18]) = 0; + (a[3] => z[18]) = 0; + (a[4] => z[18]) = 0; + (a[5] => z[18]) = 0; + (a[6] => z[18]) = 0; + (a[7] => z[18]) = 0; + (a[8] => z[18]) = 0; + (a[9] => z[18]) = 0; + (a[10] => z[18]) = 0; + (a[11] => z[18]) = 0; + (a[12] => z[18]) = 0; + (a[13] => z[18]) = 0; + (a[14] => z[18]) = 0; + (a[15] => z[18]) = 0; + (a[16] => z[18]) = 0; + (a[17] => z[18]) = 0; + (a[18] => z[18]) = 0; + (a[19] => z[18]) = 0; + (b[0] => z[18]) = 0; + (b[1] => z[18]) = 0; + (b[2] => z[18]) = 0; + (b[3] => z[18]) = 0; + (b[4] => z[18]) = 0; + (b[5] => z[18]) = 0; + (b[6] => z[18]) = 0; + (b[7] => z[18]) = 0; + (b[8] => z[18]) = 0; + (b[9] => z[18]) = 0; + (b[10] => z[18]) = 0; + (b[11] => z[18]) = 0; + (b[12] => z[18]) = 0; + (b[13] => z[18]) = 0; + (b[14] => z[18]) = 0; + (b[15] => z[18]) = 0; + (b[16] => z[18]) = 0; + (b[17] => z[18]) = 0; + (a[0] => z[19]) = 0; + (a[1] => z[19]) = 0; + (a[2] => z[19]) = 0; + (a[3] => z[19]) = 0; + (a[4] => z[19]) = 0; + (a[5] => z[19]) = 0; + (a[6] => z[19]) = 0; + (a[7] => z[19]) = 0; + (a[8] => z[19]) = 0; + (a[9] => z[19]) = 0; + (a[10] => z[19]) = 0; + (a[11] => z[19]) = 0; + (a[12] => z[19]) = 0; + (a[13] => z[19]) = 0; + (a[14] => z[19]) = 0; + (a[15] => z[19]) = 0; + (a[16] => z[19]) = 0; + (a[17] => z[19]) = 0; + (a[18] => z[19]) = 0; + (a[19] => z[19]) = 0; + (b[0] => z[19]) = 0; + (b[1] => z[19]) = 0; + (b[2] => z[19]) = 0; + (b[3] => z[19]) = 0; + (b[4] => z[19]) = 0; + (b[5] => z[19]) = 0; + (b[6] => z[19]) = 0; + (b[7] => z[19]) = 0; + (b[8] => z[19]) = 0; + (b[9] => z[19]) = 0; + (b[10] => z[19]) = 0; + (b[11] => z[19]) = 0; + (b[12] => z[19]) = 0; + (b[13] => z[19]) = 0; + (b[14] => z[19]) = 0; + (b[15] => z[19]) = 0; + (b[16] => z[19]) = 0; + (b[17] => z[19]) = 0; + (a[0] => z[20]) = 0; + (a[1] => z[20]) = 0; + (a[2] => z[20]) = 0; + (a[3] => z[20]) = 0; + (a[4] => z[20]) = 0; + (a[5] => z[20]) = 0; + (a[6] => z[20]) = 0; + (a[7] => z[20]) = 0; + (a[8] => z[20]) = 0; + (a[9] => z[20]) = 0; + (a[10] => z[20]) = 0; + (a[11] => z[20]) = 0; + (a[12] => z[20]) = 0; + (a[13] => z[20]) = 0; + (a[14] => z[20]) = 0; + (a[15] => z[20]) = 0; + (a[16] => z[20]) = 0; + (a[17] => z[20]) = 0; + (a[18] => z[20]) = 0; + (a[19] => z[20]) = 0; + (b[0] => z[20]) = 0; + (b[1] => z[20]) = 0; + (b[2] => z[20]) = 0; + (b[3] => z[20]) = 0; + (b[4] => z[20]) = 0; + (b[5] => z[20]) = 0; + (b[6] => z[20]) = 0; + (b[7] => z[20]) = 0; + (b[8] => z[20]) = 0; + (b[9] => z[20]) = 0; + (b[10] => z[20]) = 0; + (b[11] => z[20]) = 0; + (b[12] => z[20]) = 0; + (b[13] => z[20]) = 0; + (b[14] => z[20]) = 0; + (b[15] => z[20]) = 0; + (b[16] => z[20]) = 0; + (b[17] => z[20]) = 0; + (a[0] => z[21]) = 0; + (a[1] => z[21]) = 0; + (a[2] => z[21]) = 0; + (a[3] => z[21]) = 0; + (a[4] => z[21]) = 0; + (a[5] => z[21]) = 0; + (a[6] => z[21]) = 0; + (a[7] => z[21]) = 0; + (a[8] => z[21]) = 0; + (a[9] => z[21]) = 0; + (a[10] => z[21]) = 0; + (a[11] => z[21]) = 0; + (a[12] => z[21]) = 0; + (a[13] => z[21]) = 0; + (a[14] => z[21]) = 0; + (a[15] => z[21]) = 0; + (a[16] => z[21]) = 0; + (a[17] => z[21]) = 0; + (a[18] => z[21]) = 0; + (a[19] => z[21]) = 0; + (b[0] => z[21]) = 0; + (b[1] => z[21]) = 0; + (b[2] => z[21]) = 0; + (b[3] => z[21]) = 0; + (b[4] => z[21]) = 0; + (b[5] => z[21]) = 0; + (b[6] => z[21]) = 0; + (b[7] => z[21]) = 0; + (b[8] => z[21]) = 0; + (b[9] => z[21]) = 0; + (b[10] => z[21]) = 0; + (b[11] => z[21]) = 0; + (b[12] => z[21]) = 0; + (b[13] => z[21]) = 0; + (b[14] => z[21]) = 0; + (b[15] => z[21]) = 0; + (b[16] => z[21]) = 0; + (b[17] => z[21]) = 0; + (a[0] => z[22]) = 0; + (a[1] => z[22]) = 0; + (a[2] => z[22]) = 0; + (a[3] => z[22]) = 0; + (a[4] => z[22]) = 0; + (a[5] => z[22]) = 0; + (a[6] => z[22]) = 0; + (a[7] => z[22]) = 0; + (a[8] => z[22]) = 0; + (a[9] => z[22]) = 0; + (a[10] => z[22]) = 0; + (a[11] => z[22]) = 0; + (a[12] => z[22]) = 0; + (a[13] => z[22]) = 0; + (a[14] => z[22]) = 0; + (a[15] => z[22]) = 0; + (a[16] => z[22]) = 0; + (a[17] => z[22]) = 0; + (a[18] => z[22]) = 0; + (a[19] => z[22]) = 0; + (b[0] => z[22]) = 0; + (b[1] => z[22]) = 0; + (b[2] => z[22]) = 0; + (b[3] => z[22]) = 0; + (b[4] => z[22]) = 0; + (b[5] => z[22]) = 0; + (b[6] => z[22]) = 0; + (b[7] => z[22]) = 0; + (b[8] => z[22]) = 0; + (b[9] => z[22]) = 0; + (b[10] => z[22]) = 0; + (b[11] => z[22]) = 0; + (b[12] => z[22]) = 0; + (b[13] => z[22]) = 0; + (b[14] => z[22]) = 0; + (b[15] => z[22]) = 0; + (b[16] => z[22]) = 0; + (b[17] => z[22]) = 0; + (a[0] => z[23]) = 0; + (a[1] => z[23]) = 0; + (a[2] => z[23]) = 0; + (a[3] => z[23]) = 0; + (a[4] => z[23]) = 0; + (a[5] => z[23]) = 0; + (a[6] => z[23]) = 0; + (a[7] => z[23]) = 0; + (a[8] => z[23]) = 0; + (a[9] => z[23]) = 0; + (a[10] => z[23]) = 0; + (a[11] => z[23]) = 0; + (a[12] => z[23]) = 0; + (a[13] => z[23]) = 0; + (a[14] => z[23]) = 0; + (a[15] => z[23]) = 0; + (a[16] => z[23]) = 0; + (a[17] => z[23]) = 0; + (a[18] => z[23]) = 0; + (a[19] => z[23]) = 0; + (b[0] => z[23]) = 0; + (b[1] => z[23]) = 0; + (b[2] => z[23]) = 0; + (b[3] => z[23]) = 0; + (b[4] => z[23]) = 0; + (b[5] => z[23]) = 0; + (b[6] => z[23]) = 0; + (b[7] => z[23]) = 0; + (b[8] => z[23]) = 0; + (b[9] => z[23]) = 0; + (b[10] => z[23]) = 0; + (b[11] => z[23]) = 0; + (b[12] => z[23]) = 0; + (b[13] => z[23]) = 0; + (b[14] => z[23]) = 0; + (b[15] => z[23]) = 0; + (b[16] => z[23]) = 0; + (b[17] => z[23]) = 0; + (a[0] => z[24]) = 0; + (a[1] => z[24]) = 0; + (a[2] => z[24]) = 0; + (a[3] => z[24]) = 0; + (a[4] => z[24]) = 0; + (a[5] => z[24]) = 0; + (a[6] => z[24]) = 0; + (a[7] => z[24]) = 0; + (a[8] => z[24]) = 0; + (a[9] => z[24]) = 0; + (a[10] => z[24]) = 0; + (a[11] => z[24]) = 0; + (a[12] => z[24]) = 0; + (a[13] => z[24]) = 0; + (a[14] => z[24]) = 0; + (a[15] => z[24]) = 0; + (a[16] => z[24]) = 0; + (a[17] => z[24]) = 0; + (a[18] => z[24]) = 0; + (a[19] => z[24]) = 0; + (b[0] => z[24]) = 0; + (b[1] => z[24]) = 0; + (b[2] => z[24]) = 0; + (b[3] => z[24]) = 0; + (b[4] => z[24]) = 0; + (b[5] => z[24]) = 0; + (b[6] => z[24]) = 0; + (b[7] => z[24]) = 0; + (b[8] => z[24]) = 0; + (b[9] => z[24]) = 0; + (b[10] => z[24]) = 0; + (b[11] => z[24]) = 0; + (b[12] => z[24]) = 0; + (b[13] => z[24]) = 0; + (b[14] => z[24]) = 0; + (b[15] => z[24]) = 0; + (b[16] => z[24]) = 0; + (b[17] => z[24]) = 0; + (a[0] => z[25]) = 0; + (a[1] => z[25]) = 0; + (a[2] => z[25]) = 0; + (a[3] => z[25]) = 0; + (a[4] => z[25]) = 0; + (a[5] => z[25]) = 0; + (a[6] => z[25]) = 0; + (a[7] => z[25]) = 0; + (a[8] => z[25]) = 0; + (a[9] => z[25]) = 0; + (a[10] => z[25]) = 0; + (a[11] => z[25]) = 0; + (a[12] => z[25]) = 0; + (a[13] => z[25]) = 0; + (a[14] => z[25]) = 0; + (a[15] => z[25]) = 0; + (a[16] => z[25]) = 0; + (a[17] => z[25]) = 0; + (a[18] => z[25]) = 0; + (a[19] => z[25]) = 0; + (b[0] => z[25]) = 0; + (b[1] => z[25]) = 0; + (b[2] => z[25]) = 0; + (b[3] => z[25]) = 0; + (b[4] => z[25]) = 0; + (b[5] => z[25]) = 0; + (b[6] => z[25]) = 0; + (b[7] => z[25]) = 0; + (b[8] => z[25]) = 0; + (b[9] => z[25]) = 0; + (b[10] => z[25]) = 0; + (b[11] => z[25]) = 0; + (b[12] => z[25]) = 0; + (b[13] => z[25]) = 0; + (b[14] => z[25]) = 0; + (b[15] => z[25]) = 0; + (b[16] => z[25]) = 0; + (b[17] => z[25]) = 0; + (a[0] => z[26]) = 0; + (a[1] => z[26]) = 0; + (a[2] => z[26]) = 0; + (a[3] => z[26]) = 0; + (a[4] => z[26]) = 0; + (a[5] => z[26]) = 0; + (a[6] => z[26]) = 0; + (a[7] => z[26]) = 0; + (a[8] => z[26]) = 0; + (a[9] => z[26]) = 0; + (a[10] => z[26]) = 0; + (a[11] => z[26]) = 0; + (a[12] => z[26]) = 0; + (a[13] => z[26]) = 0; + (a[14] => z[26]) = 0; + (a[15] => z[26]) = 0; + (a[16] => z[26]) = 0; + (a[17] => z[26]) = 0; + (a[18] => z[26]) = 0; + (a[19] => z[26]) = 0; + (b[0] => z[26]) = 0; + (b[1] => z[26]) = 0; + (b[2] => z[26]) = 0; + (b[3] => z[26]) = 0; + (b[4] => z[26]) = 0; + (b[5] => z[26]) = 0; + (b[6] => z[26]) = 0; + (b[7] => z[26]) = 0; + (b[8] => z[26]) = 0; + (b[9] => z[26]) = 0; + (b[10] => z[26]) = 0; + (b[11] => z[26]) = 0; + (b[12] => z[26]) = 0; + (b[13] => z[26]) = 0; + (b[14] => z[26]) = 0; + (b[15] => z[26]) = 0; + (b[16] => z[26]) = 0; + (b[17] => z[26]) = 0; + (a[0] => z[27]) = 0; + (a[1] => z[27]) = 0; + (a[2] => z[27]) = 0; + (a[3] => z[27]) = 0; + (a[4] => z[27]) = 0; + (a[5] => z[27]) = 0; + (a[6] => z[27]) = 0; + (a[7] => z[27]) = 0; + (a[8] => z[27]) = 0; + (a[9] => z[27]) = 0; + (a[10] => z[27]) = 0; + (a[11] => z[27]) = 0; + (a[12] => z[27]) = 0; + (a[13] => z[27]) = 0; + (a[14] => z[27]) = 0; + (a[15] => z[27]) = 0; + (a[16] => z[27]) = 0; + (a[17] => z[27]) = 0; + (a[18] => z[27]) = 0; + (a[19] => z[27]) = 0; + (b[0] => z[27]) = 0; + (b[1] => z[27]) = 0; + (b[2] => z[27]) = 0; + (b[3] => z[27]) = 0; + (b[4] => z[27]) = 0; + (b[5] => z[27]) = 0; + (b[6] => z[27]) = 0; + (b[7] => z[27]) = 0; + (b[8] => z[27]) = 0; + (b[9] => z[27]) = 0; + (b[10] => z[27]) = 0; + (b[11] => z[27]) = 0; + (b[12] => z[27]) = 0; + (b[13] => z[27]) = 0; + (b[14] => z[27]) = 0; + (b[15] => z[27]) = 0; + (b[16] => z[27]) = 0; + (b[17] => z[27]) = 0; + (a[0] => z[28]) = 0; + (a[1] => z[28]) = 0; + (a[2] => z[28]) = 0; + (a[3] => z[28]) = 0; + (a[4] => z[28]) = 0; + (a[5] => z[28]) = 0; + (a[6] => z[28]) = 0; + (a[7] => z[28]) = 0; + (a[8] => z[28]) = 0; + (a[9] => z[28]) = 0; + (a[10] => z[28]) = 0; + (a[11] => z[28]) = 0; + (a[12] => z[28]) = 0; + (a[13] => z[28]) = 0; + (a[14] => z[28]) = 0; + (a[15] => z[28]) = 0; + (a[16] => z[28]) = 0; + (a[17] => z[28]) = 0; + (a[18] => z[28]) = 0; + (a[19] => z[28]) = 0; + (b[0] => z[28]) = 0; + (b[1] => z[28]) = 0; + (b[2] => z[28]) = 0; + (b[3] => z[28]) = 0; + (b[4] => z[28]) = 0; + (b[5] => z[28]) = 0; + (b[6] => z[28]) = 0; + (b[7] => z[28]) = 0; + (b[8] => z[28]) = 0; + (b[9] => z[28]) = 0; + (b[10] => z[28]) = 0; + (b[11] => z[28]) = 0; + (b[12] => z[28]) = 0; + (b[13] => z[28]) = 0; + (b[14] => z[28]) = 0; + (b[15] => z[28]) = 0; + (b[16] => z[28]) = 0; + (b[17] => z[28]) = 0; + (a[0] => z[29]) = 0; + (a[1] => z[29]) = 0; + (a[2] => z[29]) = 0; + (a[3] => z[29]) = 0; + (a[4] => z[29]) = 0; + (a[5] => z[29]) = 0; + (a[6] => z[29]) = 0; + (a[7] => z[29]) = 0; + (a[8] => z[29]) = 0; + (a[9] => z[29]) = 0; + (a[10] => z[29]) = 0; + (a[11] => z[29]) = 0; + (a[12] => z[29]) = 0; + (a[13] => z[29]) = 0; + (a[14] => z[29]) = 0; + (a[15] => z[29]) = 0; + (a[16] => z[29]) = 0; + (a[17] => z[29]) = 0; + (a[18] => z[29]) = 0; + (a[19] => z[29]) = 0; + (b[0] => z[29]) = 0; + (b[1] => z[29]) = 0; + (b[2] => z[29]) = 0; + (b[3] => z[29]) = 0; + (b[4] => z[29]) = 0; + (b[5] => z[29]) = 0; + (b[6] => z[29]) = 0; + (b[7] => z[29]) = 0; + (b[8] => z[29]) = 0; + (b[9] => z[29]) = 0; + (b[10] => z[29]) = 0; + (b[11] => z[29]) = 0; + (b[12] => z[29]) = 0; + (b[13] => z[29]) = 0; + (b[14] => z[29]) = 0; + (b[15] => z[29]) = 0; + (b[16] => z[29]) = 0; + (b[17] => z[29]) = 0; + (a[0] => z[30]) = 0; + (a[1] => z[30]) = 0; + (a[2] => z[30]) = 0; + (a[3] => z[30]) = 0; + (a[4] => z[30]) = 0; + (a[5] => z[30]) = 0; + (a[6] => z[30]) = 0; + (a[7] => z[30]) = 0; + (a[8] => z[30]) = 0; + (a[9] => z[30]) = 0; + (a[10] => z[30]) = 0; + (a[11] => z[30]) = 0; + (a[12] => z[30]) = 0; + (a[13] => z[30]) = 0; + (a[14] => z[30]) = 0; + (a[15] => z[30]) = 0; + (a[16] => z[30]) = 0; + (a[17] => z[30]) = 0; + (a[18] => z[30]) = 0; + (a[19] => z[30]) = 0; + (b[0] => z[30]) = 0; + (b[1] => z[30]) = 0; + (b[2] => z[30]) = 0; + (b[3] => z[30]) = 0; + (b[4] => z[30]) = 0; + (b[5] => z[30]) = 0; + (b[6] => z[30]) = 0; + (b[7] => z[30]) = 0; + (b[8] => z[30]) = 0; + (b[9] => z[30]) = 0; + (b[10] => z[30]) = 0; + (b[11] => z[30]) = 0; + (b[12] => z[30]) = 0; + (b[13] => z[30]) = 0; + (b[14] => z[30]) = 0; + (b[15] => z[30]) = 0; + (b[16] => z[30]) = 0; + (b[17] => z[30]) = 0; + (a[0] => z[31]) = 0; + (a[1] => z[31]) = 0; + (a[2] => z[31]) = 0; + (a[3] => z[31]) = 0; + (a[4] => z[31]) = 0; + (a[5] => z[31]) = 0; + (a[6] => z[31]) = 0; + (a[7] => z[31]) = 0; + (a[8] => z[31]) = 0; + (a[9] => z[31]) = 0; + (a[10] => z[31]) = 0; + (a[11] => z[31]) = 0; + (a[12] => z[31]) = 0; + (a[13] => z[31]) = 0; + (a[14] => z[31]) = 0; + (a[15] => z[31]) = 0; + (a[16] => z[31]) = 0; + (a[17] => z[31]) = 0; + (a[18] => z[31]) = 0; + (a[19] => z[31]) = 0; + (b[0] => z[31]) = 0; + (b[1] => z[31]) = 0; + (b[2] => z[31]) = 0; + (b[3] => z[31]) = 0; + (b[4] => z[31]) = 0; + (b[5] => z[31]) = 0; + (b[6] => z[31]) = 0; + (b[7] => z[31]) = 0; + (b[8] => z[31]) = 0; + (b[9] => z[31]) = 0; + (b[10] => z[31]) = 0; + (b[11] => z[31]) = 0; + (b[12] => z[31]) = 0; + (b[13] => z[31]) = 0; + (b[14] => z[31]) = 0; + (b[15] => z[31]) = 0; + (b[16] => z[31]) = 0; + (b[17] => z[31]) = 0; + (a[0] => z[32]) = 0; + (a[1] => z[32]) = 0; + (a[2] => z[32]) = 0; + (a[3] => z[32]) = 0; + (a[4] => z[32]) = 0; + (a[5] => z[32]) = 0; + (a[6] => z[32]) = 0; + (a[7] => z[32]) = 0; + (a[8] => z[32]) = 0; + (a[9] => z[32]) = 0; + (a[10] => z[32]) = 0; + (a[11] => z[32]) = 0; + (a[12] => z[32]) = 0; + (a[13] => z[32]) = 0; + (a[14] => z[32]) = 0; + (a[15] => z[32]) = 0; + (a[16] => z[32]) = 0; + (a[17] => z[32]) = 0; + (a[18] => z[32]) = 0; + (a[19] => z[32]) = 0; + (b[0] => z[32]) = 0; + (b[1] => z[32]) = 0; + (b[2] => z[32]) = 0; + (b[3] => z[32]) = 0; + (b[4] => z[32]) = 0; + (b[5] => z[32]) = 0; + (b[6] => z[32]) = 0; + (b[7] => z[32]) = 0; + (b[8] => z[32]) = 0; + (b[9] => z[32]) = 0; + (b[10] => z[32]) = 0; + (b[11] => z[32]) = 0; + (b[12] => z[32]) = 0; + (b[13] => z[32]) = 0; + (b[14] => z[32]) = 0; + (b[15] => z[32]) = 0; + (b[16] => z[32]) = 0; + (b[17] => z[32]) = 0; + (a[0] => z[33]) = 0; + (a[1] => z[33]) = 0; + (a[2] => z[33]) = 0; + (a[3] => z[33]) = 0; + (a[4] => z[33]) = 0; + (a[5] => z[33]) = 0; + (a[6] => z[33]) = 0; + (a[7] => z[33]) = 0; + (a[8] => z[33]) = 0; + (a[9] => z[33]) = 0; + (a[10] => z[33]) = 0; + (a[11] => z[33]) = 0; + (a[12] => z[33]) = 0; + (a[13] => z[33]) = 0; + (a[14] => z[33]) = 0; + (a[15] => z[33]) = 0; + (a[16] => z[33]) = 0; + (a[17] => z[33]) = 0; + (a[18] => z[33]) = 0; + (a[19] => z[33]) = 0; + (b[0] => z[33]) = 0; + (b[1] => z[33]) = 0; + (b[2] => z[33]) = 0; + (b[3] => z[33]) = 0; + (b[4] => z[33]) = 0; + (b[5] => z[33]) = 0; + (b[6] => z[33]) = 0; + (b[7] => z[33]) = 0; + (b[8] => z[33]) = 0; + (b[9] => z[33]) = 0; + (b[10] => z[33]) = 0; + (b[11] => z[33]) = 0; + (b[12] => z[33]) = 0; + (b[13] => z[33]) = 0; + (b[14] => z[33]) = 0; + (b[15] => z[33]) = 0; + (b[16] => z[33]) = 0; + (b[17] => z[33]) = 0; + (a[0] => z[34]) = 0; + (a[1] => z[34]) = 0; + (a[2] => z[34]) = 0; + (a[3] => z[34]) = 0; + (a[4] => z[34]) = 0; + (a[5] => z[34]) = 0; + (a[6] => z[34]) = 0; + (a[7] => z[34]) = 0; + (a[8] => z[34]) = 0; + (a[9] => z[34]) = 0; + (a[10] => z[34]) = 0; + (a[11] => z[34]) = 0; + (a[12] => z[34]) = 0; + (a[13] => z[34]) = 0; + (a[14] => z[34]) = 0; + (a[15] => z[34]) = 0; + (a[16] => z[34]) = 0; + (a[17] => z[34]) = 0; + (a[18] => z[34]) = 0; + (a[19] => z[34]) = 0; + (b[0] => z[34]) = 0; + (b[1] => z[34]) = 0; + (b[2] => z[34]) = 0; + (b[3] => z[34]) = 0; + (b[4] => z[34]) = 0; + (b[5] => z[34]) = 0; + (b[6] => z[34]) = 0; + (b[7] => z[34]) = 0; + (b[8] => z[34]) = 0; + (b[9] => z[34]) = 0; + (b[10] => z[34]) = 0; + (b[11] => z[34]) = 0; + (b[12] => z[34]) = 0; + (b[13] => z[34]) = 0; + (b[14] => z[34]) = 0; + (b[15] => z[34]) = 0; + (b[16] => z[34]) = 0; + (b[17] => z[34]) = 0; + (a[0] => z[35]) = 0; + (a[1] => z[35]) = 0; + (a[2] => z[35]) = 0; + (a[3] => z[35]) = 0; + (a[4] => z[35]) = 0; + (a[5] => z[35]) = 0; + (a[6] => z[35]) = 0; + (a[7] => z[35]) = 0; + (a[8] => z[35]) = 0; + (a[9] => z[35]) = 0; + (a[10] => z[35]) = 0; + (a[11] => z[35]) = 0; + (a[12] => z[35]) = 0; + (a[13] => z[35]) = 0; + (a[14] => z[35]) = 0; + (a[15] => z[35]) = 0; + (a[16] => z[35]) = 0; + (a[17] => z[35]) = 0; + (a[18] => z[35]) = 0; + (a[19] => z[35]) = 0; + (b[0] => z[35]) = 0; + (b[1] => z[35]) = 0; + (b[2] => z[35]) = 0; + (b[3] => z[35]) = 0; + (b[4] => z[35]) = 0; + (b[5] => z[35]) = 0; + (b[6] => z[35]) = 0; + (b[7] => z[35]) = 0; + (b[8] => z[35]) = 0; + (b[9] => z[35]) = 0; + (b[10] => z[35]) = 0; + (b[11] => z[35]) = 0; + (b[12] => z[35]) = 0; + (b[13] => z[35]) = 0; + (b[14] => z[35]) = 0; + (b[15] => z[35]) = 0; + (b[16] => z[35]) = 0; + (b[17] => z[35]) = 0; + (a[0] => z[36]) = 0; + (a[1] => z[36]) = 0; + (a[2] => z[36]) = 0; + (a[3] => z[36]) = 0; + (a[4] => z[36]) = 0; + (a[5] => z[36]) = 0; + (a[6] => z[36]) = 0; + (a[7] => z[36]) = 0; + (a[8] => z[36]) = 0; + (a[9] => z[36]) = 0; + (a[10] => z[36]) = 0; + (a[11] => z[36]) = 0; + (a[12] => z[36]) = 0; + (a[13] => z[36]) = 0; + (a[14] => z[36]) = 0; + (a[15] => z[36]) = 0; + (a[16] => z[36]) = 0; + (a[17] => z[36]) = 0; + (a[18] => z[36]) = 0; + (a[19] => z[36]) = 0; + (b[0] => z[36]) = 0; + (b[1] => z[36]) = 0; + (b[2] => z[36]) = 0; + (b[3] => z[36]) = 0; + (b[4] => z[36]) = 0; + (b[5] => z[36]) = 0; + (b[6] => z[36]) = 0; + (b[7] => z[36]) = 0; + (b[8] => z[36]) = 0; + (b[9] => z[36]) = 0; + (b[10] => z[36]) = 0; + (b[11] => z[36]) = 0; + (b[12] => z[36]) = 0; + (b[13] => z[36]) = 0; + (b[14] => z[36]) = 0; + (b[15] => z[36]) = 0; + (b[16] => z[36]) = 0; + (b[17] => z[36]) = 0; + (a[0] => z[37]) = 0; + (a[1] => z[37]) = 0; + (a[2] => z[37]) = 0; + (a[3] => z[37]) = 0; + (a[4] => z[37]) = 0; + (a[5] => z[37]) = 0; + (a[6] => z[37]) = 0; + (a[7] => z[37]) = 0; + (a[8] => z[37]) = 0; + (a[9] => z[37]) = 0; + (a[10] => z[37]) = 0; + (a[11] => z[37]) = 0; + (a[12] => z[37]) = 0; + (a[13] => z[37]) = 0; + (a[14] => z[37]) = 0; + (a[15] => z[37]) = 0; + (a[16] => z[37]) = 0; + (a[17] => z[37]) = 0; + (a[18] => z[37]) = 0; + (a[19] => z[37]) = 0; + (b[0] => z[37]) = 0; + (b[1] => z[37]) = 0; + (b[2] => z[37]) = 0; + (b[3] => z[37]) = 0; + (b[4] => z[37]) = 0; + (b[5] => z[37]) = 0; + (b[6] => z[37]) = 0; + (b[7] => z[37]) = 0; + (b[8] => z[37]) = 0; + (b[9] => z[37]) = 0; + (b[10] => z[37]) = 0; + (b[11] => z[37]) = 0; + (b[12] => z[37]) = 0; + (b[13] => z[37]) = 0; + (b[14] => z[37]) = 0; + (b[15] => z[37]) = 0; + (b[16] => z[37]) = 0; + (b[17] => z[37]) = 0; + endspecify +`endif + +endmodule + +module QL_DSP2_MULT_REGIN ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: a * b (0) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULT_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: a * b (4) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULT_REGIN_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: a * b (4) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + //.clk(1'b0), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCin (2, 3) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (a[0] => z[0]) = 0; + (a[1] => z[0]) = 0; + (a[2] => z[0]) = 0; + (a[3] => z[0]) = 0; + (a[4] => z[0]) = 0; + (a[5] => z[0]) = 0; + (a[6] => z[0]) = 0; + (a[7] => z[0]) = 0; + (a[8] => z[0]) = 0; + (a[9] => z[0]) = 0; + (a[10] => z[0]) = 0; + (a[11] => z[0]) = 0; + (a[12] => z[0]) = 0; + (a[13] => z[0]) = 0; + (a[14] => z[0]) = 0; + (a[15] => z[0]) = 0; + (a[16] => z[0]) = 0; + (a[17] => z[0]) = 0; + (a[18] => z[0]) = 0; + (a[19] => z[0]) = 0; + (b[0] => z[0]) = 0; + (b[1] => z[0]) = 0; + (b[2] => z[0]) = 0; + (b[3] => z[0]) = 0; + (b[4] => z[0]) = 0; + (b[5] => z[0]) = 0; + (b[6] => z[0]) = 0; + (b[7] => z[0]) = 0; + (b[8] => z[0]) = 0; + (b[9] => z[0]) = 0; + (b[10] => z[0]) = 0; + (b[11] => z[0]) = 0; + (b[12] => z[0]) = 0; + (b[13] => z[0]) = 0; + (b[14] => z[0]) = 0; + (b[15] => z[0]) = 0; + (b[16] => z[0]) = 0; + (b[17] => z[0]) = 0; + (a[0] => z[1]) = 0; + (a[1] => z[1]) = 0; + (a[2] => z[1]) = 0; + (a[3] => z[1]) = 0; + (a[4] => z[1]) = 0; + (a[5] => z[1]) = 0; + (a[6] => z[1]) = 0; + (a[7] => z[1]) = 0; + (a[8] => z[1]) = 0; + (a[9] => z[1]) = 0; + (a[10] => z[1]) = 0; + (a[11] => z[1]) = 0; + (a[12] => z[1]) = 0; + (a[13] => z[1]) = 0; + (a[14] => z[1]) = 0; + (a[15] => z[1]) = 0; + (a[16] => z[1]) = 0; + (a[17] => z[1]) = 0; + (a[18] => z[1]) = 0; + (a[19] => z[1]) = 0; + (b[0] => z[1]) = 0; + (b[1] => z[1]) = 0; + (b[2] => z[1]) = 0; + (b[3] => z[1]) = 0; + (b[4] => z[1]) = 0; + (b[5] => z[1]) = 0; + (b[6] => z[1]) = 0; + (b[7] => z[1]) = 0; + (b[8] => z[1]) = 0; + (b[9] => z[1]) = 0; + (b[10] => z[1]) = 0; + (b[11] => z[1]) = 0; + (b[12] => z[1]) = 0; + (b[13] => z[1]) = 0; + (b[14] => z[1]) = 0; + (b[15] => z[1]) = 0; + (b[16] => z[1]) = 0; + (b[17] => z[1]) = 0; + (a[0] => z[2]) = 0; + (a[1] => z[2]) = 0; + (a[2] => z[2]) = 0; + (a[3] => z[2]) = 0; + (a[4] => z[2]) = 0; + (a[5] => z[2]) = 0; + (a[6] => z[2]) = 0; + (a[7] => z[2]) = 0; + (a[8] => z[2]) = 0; + (a[9] => z[2]) = 0; + (a[10] => z[2]) = 0; + (a[11] => z[2]) = 0; + (a[12] => z[2]) = 0; + (a[13] => z[2]) = 0; + (a[14] => z[2]) = 0; + (a[15] => z[2]) = 0; + (a[16] => z[2]) = 0; + (a[17] => z[2]) = 0; + (a[18] => z[2]) = 0; + (a[19] => z[2]) = 0; + (b[0] => z[2]) = 0; + (b[1] => z[2]) = 0; + (b[2] => z[2]) = 0; + (b[3] => z[2]) = 0; + (b[4] => z[2]) = 0; + (b[5] => z[2]) = 0; + (b[6] => z[2]) = 0; + (b[7] => z[2]) = 0; + (b[8] => z[2]) = 0; + (b[9] => z[2]) = 0; + (b[10] => z[2]) = 0; + (b[11] => z[2]) = 0; + (b[12] => z[2]) = 0; + (b[13] => z[2]) = 0; + (b[14] => z[2]) = 0; + (b[15] => z[2]) = 0; + (b[16] => z[2]) = 0; + (b[17] => z[2]) = 0; + (a[0] => z[3]) = 0; + (a[1] => z[3]) = 0; + (a[2] => z[3]) = 0; + (a[3] => z[3]) = 0; + (a[4] => z[3]) = 0; + (a[5] => z[3]) = 0; + (a[6] => z[3]) = 0; + (a[7] => z[3]) = 0; + (a[8] => z[3]) = 0; + (a[9] => z[3]) = 0; + (a[10] => z[3]) = 0; + (a[11] => z[3]) = 0; + (a[12] => z[3]) = 0; + (a[13] => z[3]) = 0; + (a[14] => z[3]) = 0; + (a[15] => z[3]) = 0; + (a[16] => z[3]) = 0; + (a[17] => z[3]) = 0; + (a[18] => z[3]) = 0; + (a[19] => z[3]) = 0; + (b[0] => z[3]) = 0; + (b[1] => z[3]) = 0; + (b[2] => z[3]) = 0; + (b[3] => z[3]) = 0; + (b[4] => z[3]) = 0; + (b[5] => z[3]) = 0; + (b[6] => z[3]) = 0; + (b[7] => z[3]) = 0; + (b[8] => z[3]) = 0; + (b[9] => z[3]) = 0; + (b[10] => z[3]) = 0; + (b[11] => z[3]) = 0; + (b[12] => z[3]) = 0; + (b[13] => z[3]) = 0; + (b[14] => z[3]) = 0; + (b[15] => z[3]) = 0; + (b[16] => z[3]) = 0; + (b[17] => z[3]) = 0; + (a[0] => z[4]) = 0; + (a[1] => z[4]) = 0; + (a[2] => z[4]) = 0; + (a[3] => z[4]) = 0; + (a[4] => z[4]) = 0; + (a[5] => z[4]) = 0; + (a[6] => z[4]) = 0; + (a[7] => z[4]) = 0; + (a[8] => z[4]) = 0; + (a[9] => z[4]) = 0; + (a[10] => z[4]) = 0; + (a[11] => z[4]) = 0; + (a[12] => z[4]) = 0; + (a[13] => z[4]) = 0; + (a[14] => z[4]) = 0; + (a[15] => z[4]) = 0; + (a[16] => z[4]) = 0; + (a[17] => z[4]) = 0; + (a[18] => z[4]) = 0; + (a[19] => z[4]) = 0; + (b[0] => z[4]) = 0; + (b[1] => z[4]) = 0; + (b[2] => z[4]) = 0; + (b[3] => z[4]) = 0; + (b[4] => z[4]) = 0; + (b[5] => z[4]) = 0; + (b[6] => z[4]) = 0; + (b[7] => z[4]) = 0; + (b[8] => z[4]) = 0; + (b[9] => z[4]) = 0; + (b[10] => z[4]) = 0; + (b[11] => z[4]) = 0; + (b[12] => z[4]) = 0; + (b[13] => z[4]) = 0; + (b[14] => z[4]) = 0; + (b[15] => z[4]) = 0; + (b[16] => z[4]) = 0; + (b[17] => z[4]) = 0; + (a[0] => z[5]) = 0; + (a[1] => z[5]) = 0; + (a[2] => z[5]) = 0; + (a[3] => z[5]) = 0; + (a[4] => z[5]) = 0; + (a[5] => z[5]) = 0; + (a[6] => z[5]) = 0; + (a[7] => z[5]) = 0; + (a[8] => z[5]) = 0; + (a[9] => z[5]) = 0; + (a[10] => z[5]) = 0; + (a[11] => z[5]) = 0; + (a[12] => z[5]) = 0; + (a[13] => z[5]) = 0; + (a[14] => z[5]) = 0; + (a[15] => z[5]) = 0; + (a[16] => z[5]) = 0; + (a[17] => z[5]) = 0; + (a[18] => z[5]) = 0; + (a[19] => z[5]) = 0; + (b[0] => z[5]) = 0; + (b[1] => z[5]) = 0; + (b[2] => z[5]) = 0; + (b[3] => z[5]) = 0; + (b[4] => z[5]) = 0; + (b[5] => z[5]) = 0; + (b[6] => z[5]) = 0; + (b[7] => z[5]) = 0; + (b[8] => z[5]) = 0; + (b[9] => z[5]) = 0; + (b[10] => z[5]) = 0; + (b[11] => z[5]) = 0; + (b[12] => z[5]) = 0; + (b[13] => z[5]) = 0; + (b[14] => z[5]) = 0; + (b[15] => z[5]) = 0; + (b[16] => z[5]) = 0; + (b[17] => z[5]) = 0; + (a[0] => z[6]) = 0; + (a[1] => z[6]) = 0; + (a[2] => z[6]) = 0; + (a[3] => z[6]) = 0; + (a[4] => z[6]) = 0; + (a[5] => z[6]) = 0; + (a[6] => z[6]) = 0; + (a[7] => z[6]) = 0; + (a[8] => z[6]) = 0; + (a[9] => z[6]) = 0; + (a[10] => z[6]) = 0; + (a[11] => z[6]) = 0; + (a[12] => z[6]) = 0; + (a[13] => z[6]) = 0; + (a[14] => z[6]) = 0; + (a[15] => z[6]) = 0; + (a[16] => z[6]) = 0; + (a[17] => z[6]) = 0; + (a[18] => z[6]) = 0; + (a[19] => z[6]) = 0; + (b[0] => z[6]) = 0; + (b[1] => z[6]) = 0; + (b[2] => z[6]) = 0; + (b[3] => z[6]) = 0; + (b[4] => z[6]) = 0; + (b[5] => z[6]) = 0; + (b[6] => z[6]) = 0; + (b[7] => z[6]) = 0; + (b[8] => z[6]) = 0; + (b[9] => z[6]) = 0; + (b[10] => z[6]) = 0; + (b[11] => z[6]) = 0; + (b[12] => z[6]) = 0; + (b[13] => z[6]) = 0; + (b[14] => z[6]) = 0; + (b[15] => z[6]) = 0; + (b[16] => z[6]) = 0; + (b[17] => z[6]) = 0; + (a[0] => z[7]) = 0; + (a[1] => z[7]) = 0; + (a[2] => z[7]) = 0; + (a[3] => z[7]) = 0; + (a[4] => z[7]) = 0; + (a[5] => z[7]) = 0; + (a[6] => z[7]) = 0; + (a[7] => z[7]) = 0; + (a[8] => z[7]) = 0; + (a[9] => z[7]) = 0; + (a[10] => z[7]) = 0; + (a[11] => z[7]) = 0; + (a[12] => z[7]) = 0; + (a[13] => z[7]) = 0; + (a[14] => z[7]) = 0; + (a[15] => z[7]) = 0; + (a[16] => z[7]) = 0; + (a[17] => z[7]) = 0; + (a[18] => z[7]) = 0; + (a[19] => z[7]) = 0; + (b[0] => z[7]) = 0; + (b[1] => z[7]) = 0; + (b[2] => z[7]) = 0; + (b[3] => z[7]) = 0; + (b[4] => z[7]) = 0; + (b[5] => z[7]) = 0; + (b[6] => z[7]) = 0; + (b[7] => z[7]) = 0; + (b[8] => z[7]) = 0; + (b[9] => z[7]) = 0; + (b[10] => z[7]) = 0; + (b[11] => z[7]) = 0; + (b[12] => z[7]) = 0; + (b[13] => z[7]) = 0; + (b[14] => z[7]) = 0; + (b[15] => z[7]) = 0; + (b[16] => z[7]) = 0; + (b[17] => z[7]) = 0; + (a[0] => z[8]) = 0; + (a[1] => z[8]) = 0; + (a[2] => z[8]) = 0; + (a[3] => z[8]) = 0; + (a[4] => z[8]) = 0; + (a[5] => z[8]) = 0; + (a[6] => z[8]) = 0; + (a[7] => z[8]) = 0; + (a[8] => z[8]) = 0; + (a[9] => z[8]) = 0; + (a[10] => z[8]) = 0; + (a[11] => z[8]) = 0; + (a[12] => z[8]) = 0; + (a[13] => z[8]) = 0; + (a[14] => z[8]) = 0; + (a[15] => z[8]) = 0; + (a[16] => z[8]) = 0; + (a[17] => z[8]) = 0; + (a[18] => z[8]) = 0; + (a[19] => z[8]) = 0; + (b[0] => z[8]) = 0; + (b[1] => z[8]) = 0; + (b[2] => z[8]) = 0; + (b[3] => z[8]) = 0; + (b[4] => z[8]) = 0; + (b[5] => z[8]) = 0; + (b[6] => z[8]) = 0; + (b[7] => z[8]) = 0; + (b[8] => z[8]) = 0; + (b[9] => z[8]) = 0; + (b[10] => z[8]) = 0; + (b[11] => z[8]) = 0; + (b[12] => z[8]) = 0; + (b[13] => z[8]) = 0; + (b[14] => z[8]) = 0; + (b[15] => z[8]) = 0; + (b[16] => z[8]) = 0; + (b[17] => z[8]) = 0; + (a[0] => z[9]) = 0; + (a[1] => z[9]) = 0; + (a[2] => z[9]) = 0; + (a[3] => z[9]) = 0; + (a[4] => z[9]) = 0; + (a[5] => z[9]) = 0; + (a[6] => z[9]) = 0; + (a[7] => z[9]) = 0; + (a[8] => z[9]) = 0; + (a[9] => z[9]) = 0; + (a[10] => z[9]) = 0; + (a[11] => z[9]) = 0; + (a[12] => z[9]) = 0; + (a[13] => z[9]) = 0; + (a[14] => z[9]) = 0; + (a[15] => z[9]) = 0; + (a[16] => z[9]) = 0; + (a[17] => z[9]) = 0; + (a[18] => z[9]) = 0; + (a[19] => z[9]) = 0; + (b[0] => z[9]) = 0; + (b[1] => z[9]) = 0; + (b[2] => z[9]) = 0; + (b[3] => z[9]) = 0; + (b[4] => z[9]) = 0; + (b[5] => z[9]) = 0; + (b[6] => z[9]) = 0; + (b[7] => z[9]) = 0; + (b[8] => z[9]) = 0; + (b[9] => z[9]) = 0; + (b[10] => z[9]) = 0; + (b[11] => z[9]) = 0; + (b[12] => z[9]) = 0; + (b[13] => z[9]) = 0; + (b[14] => z[9]) = 0; + (b[15] => z[9]) = 0; + (b[16] => z[9]) = 0; + (b[17] => z[9]) = 0; + (a[0] => z[10]) = 0; + (a[1] => z[10]) = 0; + (a[2] => z[10]) = 0; + (a[3] => z[10]) = 0; + (a[4] => z[10]) = 0; + (a[5] => z[10]) = 0; + (a[6] => z[10]) = 0; + (a[7] => z[10]) = 0; + (a[8] => z[10]) = 0; + (a[9] => z[10]) = 0; + (a[10] => z[10]) = 0; + (a[11] => z[10]) = 0; + (a[12] => z[10]) = 0; + (a[13] => z[10]) = 0; + (a[14] => z[10]) = 0; + (a[15] => z[10]) = 0; + (a[16] => z[10]) = 0; + (a[17] => z[10]) = 0; + (a[18] => z[10]) = 0; + (a[19] => z[10]) = 0; + (b[0] => z[10]) = 0; + (b[1] => z[10]) = 0; + (b[2] => z[10]) = 0; + (b[3] => z[10]) = 0; + (b[4] => z[10]) = 0; + (b[5] => z[10]) = 0; + (b[6] => z[10]) = 0; + (b[7] => z[10]) = 0; + (b[8] => z[10]) = 0; + (b[9] => z[10]) = 0; + (b[10] => z[10]) = 0; + (b[11] => z[10]) = 0; + (b[12] => z[10]) = 0; + (b[13] => z[10]) = 0; + (b[14] => z[10]) = 0; + (b[15] => z[10]) = 0; + (b[16] => z[10]) = 0; + (b[17] => z[10]) = 0; + (a[0] => z[11]) = 0; + (a[1] => z[11]) = 0; + (a[2] => z[11]) = 0; + (a[3] => z[11]) = 0; + (a[4] => z[11]) = 0; + (a[5] => z[11]) = 0; + (a[6] => z[11]) = 0; + (a[7] => z[11]) = 0; + (a[8] => z[11]) = 0; + (a[9] => z[11]) = 0; + (a[10] => z[11]) = 0; + (a[11] => z[11]) = 0; + (a[12] => z[11]) = 0; + (a[13] => z[11]) = 0; + (a[14] => z[11]) = 0; + (a[15] => z[11]) = 0; + (a[16] => z[11]) = 0; + (a[17] => z[11]) = 0; + (a[18] => z[11]) = 0; + (a[19] => z[11]) = 0; + (b[0] => z[11]) = 0; + (b[1] => z[11]) = 0; + (b[2] => z[11]) = 0; + (b[3] => z[11]) = 0; + (b[4] => z[11]) = 0; + (b[5] => z[11]) = 0; + (b[6] => z[11]) = 0; + (b[7] => z[11]) = 0; + (b[8] => z[11]) = 0; + (b[9] => z[11]) = 0; + (b[10] => z[11]) = 0; + (b[11] => z[11]) = 0; + (b[12] => z[11]) = 0; + (b[13] => z[11]) = 0; + (b[14] => z[11]) = 0; + (b[15] => z[11]) = 0; + (b[16] => z[11]) = 0; + (b[17] => z[11]) = 0; + (a[0] => z[12]) = 0; + (a[1] => z[12]) = 0; + (a[2] => z[12]) = 0; + (a[3] => z[12]) = 0; + (a[4] => z[12]) = 0; + (a[5] => z[12]) = 0; + (a[6] => z[12]) = 0; + (a[7] => z[12]) = 0; + (a[8] => z[12]) = 0; + (a[9] => z[12]) = 0; + (a[10] => z[12]) = 0; + (a[11] => z[12]) = 0; + (a[12] => z[12]) = 0; + (a[13] => z[12]) = 0; + (a[14] => z[12]) = 0; + (a[15] => z[12]) = 0; + (a[16] => z[12]) = 0; + (a[17] => z[12]) = 0; + (a[18] => z[12]) = 0; + (a[19] => z[12]) = 0; + (b[0] => z[12]) = 0; + (b[1] => z[12]) = 0; + (b[2] => z[12]) = 0; + (b[3] => z[12]) = 0; + (b[4] => z[12]) = 0; + (b[5] => z[12]) = 0; + (b[6] => z[12]) = 0; + (b[7] => z[12]) = 0; + (b[8] => z[12]) = 0; + (b[9] => z[12]) = 0; + (b[10] => z[12]) = 0; + (b[11] => z[12]) = 0; + (b[12] => z[12]) = 0; + (b[13] => z[12]) = 0; + (b[14] => z[12]) = 0; + (b[15] => z[12]) = 0; + (b[16] => z[12]) = 0; + (b[17] => z[12]) = 0; + (a[0] => z[13]) = 0; + (a[1] => z[13]) = 0; + (a[2] => z[13]) = 0; + (a[3] => z[13]) = 0; + (a[4] => z[13]) = 0; + (a[5] => z[13]) = 0; + (a[6] => z[13]) = 0; + (a[7] => z[13]) = 0; + (a[8] => z[13]) = 0; + (a[9] => z[13]) = 0; + (a[10] => z[13]) = 0; + (a[11] => z[13]) = 0; + (a[12] => z[13]) = 0; + (a[13] => z[13]) = 0; + (a[14] => z[13]) = 0; + (a[15] => z[13]) = 0; + (a[16] => z[13]) = 0; + (a[17] => z[13]) = 0; + (a[18] => z[13]) = 0; + (a[19] => z[13]) = 0; + (b[0] => z[13]) = 0; + (b[1] => z[13]) = 0; + (b[2] => z[13]) = 0; + (b[3] => z[13]) = 0; + (b[4] => z[13]) = 0; + (b[5] => z[13]) = 0; + (b[6] => z[13]) = 0; + (b[7] => z[13]) = 0; + (b[8] => z[13]) = 0; + (b[9] => z[13]) = 0; + (b[10] => z[13]) = 0; + (b[11] => z[13]) = 0; + (b[12] => z[13]) = 0; + (b[13] => z[13]) = 0; + (b[14] => z[13]) = 0; + (b[15] => z[13]) = 0; + (b[16] => z[13]) = 0; + (b[17] => z[13]) = 0; + (a[0] => z[14]) = 0; + (a[1] => z[14]) = 0; + (a[2] => z[14]) = 0; + (a[3] => z[14]) = 0; + (a[4] => z[14]) = 0; + (a[5] => z[14]) = 0; + (a[6] => z[14]) = 0; + (a[7] => z[14]) = 0; + (a[8] => z[14]) = 0; + (a[9] => z[14]) = 0; + (a[10] => z[14]) = 0; + (a[11] => z[14]) = 0; + (a[12] => z[14]) = 0; + (a[13] => z[14]) = 0; + (a[14] => z[14]) = 0; + (a[15] => z[14]) = 0; + (a[16] => z[14]) = 0; + (a[17] => z[14]) = 0; + (a[18] => z[14]) = 0; + (a[19] => z[14]) = 0; + (b[0] => z[14]) = 0; + (b[1] => z[14]) = 0; + (b[2] => z[14]) = 0; + (b[3] => z[14]) = 0; + (b[4] => z[14]) = 0; + (b[5] => z[14]) = 0; + (b[6] => z[14]) = 0; + (b[7] => z[14]) = 0; + (b[8] => z[14]) = 0; + (b[9] => z[14]) = 0; + (b[10] => z[14]) = 0; + (b[11] => z[14]) = 0; + (b[12] => z[14]) = 0; + (b[13] => z[14]) = 0; + (b[14] => z[14]) = 0; + (b[15] => z[14]) = 0; + (b[16] => z[14]) = 0; + (b[17] => z[14]) = 0; + (a[0] => z[15]) = 0; + (a[1] => z[15]) = 0; + (a[2] => z[15]) = 0; + (a[3] => z[15]) = 0; + (a[4] => z[15]) = 0; + (a[5] => z[15]) = 0; + (a[6] => z[15]) = 0; + (a[7] => z[15]) = 0; + (a[8] => z[15]) = 0; + (a[9] => z[15]) = 0; + (a[10] => z[15]) = 0; + (a[11] => z[15]) = 0; + (a[12] => z[15]) = 0; + (a[13] => z[15]) = 0; + (a[14] => z[15]) = 0; + (a[15] => z[15]) = 0; + (a[16] => z[15]) = 0; + (a[17] => z[15]) = 0; + (a[18] => z[15]) = 0; + (a[19] => z[15]) = 0; + (b[0] => z[15]) = 0; + (b[1] => z[15]) = 0; + (b[2] => z[15]) = 0; + (b[3] => z[15]) = 0; + (b[4] => z[15]) = 0; + (b[5] => z[15]) = 0; + (b[6] => z[15]) = 0; + (b[7] => z[15]) = 0; + (b[8] => z[15]) = 0; + (b[9] => z[15]) = 0; + (b[10] => z[15]) = 0; + (b[11] => z[15]) = 0; + (b[12] => z[15]) = 0; + (b[13] => z[15]) = 0; + (b[14] => z[15]) = 0; + (b[15] => z[15]) = 0; + (b[16] => z[15]) = 0; + (b[17] => z[15]) = 0; + (a[0] => z[16]) = 0; + (a[1] => z[16]) = 0; + (a[2] => z[16]) = 0; + (a[3] => z[16]) = 0; + (a[4] => z[16]) = 0; + (a[5] => z[16]) = 0; + (a[6] => z[16]) = 0; + (a[7] => z[16]) = 0; + (a[8] => z[16]) = 0; + (a[9] => z[16]) = 0; + (a[10] => z[16]) = 0; + (a[11] => z[16]) = 0; + (a[12] => z[16]) = 0; + (a[13] => z[16]) = 0; + (a[14] => z[16]) = 0; + (a[15] => z[16]) = 0; + (a[16] => z[16]) = 0; + (a[17] => z[16]) = 0; + (a[18] => z[16]) = 0; + (a[19] => z[16]) = 0; + (b[0] => z[16]) = 0; + (b[1] => z[16]) = 0; + (b[2] => z[16]) = 0; + (b[3] => z[16]) = 0; + (b[4] => z[16]) = 0; + (b[5] => z[16]) = 0; + (b[6] => z[16]) = 0; + (b[7] => z[16]) = 0; + (b[8] => z[16]) = 0; + (b[9] => z[16]) = 0; + (b[10] => z[16]) = 0; + (b[11] => z[16]) = 0; + (b[12] => z[16]) = 0; + (b[13] => z[16]) = 0; + (b[14] => z[16]) = 0; + (b[15] => z[16]) = 0; + (b[16] => z[16]) = 0; + (b[17] => z[16]) = 0; + (a[0] => z[17]) = 0; + (a[1] => z[17]) = 0; + (a[2] => z[17]) = 0; + (a[3] => z[17]) = 0; + (a[4] => z[17]) = 0; + (a[5] => z[17]) = 0; + (a[6] => z[17]) = 0; + (a[7] => z[17]) = 0; + (a[8] => z[17]) = 0; + (a[9] => z[17]) = 0; + (a[10] => z[17]) = 0; + (a[11] => z[17]) = 0; + (a[12] => z[17]) = 0; + (a[13] => z[17]) = 0; + (a[14] => z[17]) = 0; + (a[15] => z[17]) = 0; + (a[16] => z[17]) = 0; + (a[17] => z[17]) = 0; + (a[18] => z[17]) = 0; + (a[19] => z[17]) = 0; + (b[0] => z[17]) = 0; + (b[1] => z[17]) = 0; + (b[2] => z[17]) = 0; + (b[3] => z[17]) = 0; + (b[4] => z[17]) = 0; + (b[5] => z[17]) = 0; + (b[6] => z[17]) = 0; + (b[7] => z[17]) = 0; + (b[8] => z[17]) = 0; + (b[9] => z[17]) = 0; + (b[10] => z[17]) = 0; + (b[11] => z[17]) = 0; + (b[12] => z[17]) = 0; + (b[13] => z[17]) = 0; + (b[14] => z[17]) = 0; + (b[15] => z[17]) = 0; + (b[16] => z[17]) = 0; + (b[17] => z[17]) = 0; + (a[0] => z[18]) = 0; + (a[1] => z[18]) = 0; + (a[2] => z[18]) = 0; + (a[3] => z[18]) = 0; + (a[4] => z[18]) = 0; + (a[5] => z[18]) = 0; + (a[6] => z[18]) = 0; + (a[7] => z[18]) = 0; + (a[8] => z[18]) = 0; + (a[9] => z[18]) = 0; + (a[10] => z[18]) = 0; + (a[11] => z[18]) = 0; + (a[12] => z[18]) = 0; + (a[13] => z[18]) = 0; + (a[14] => z[18]) = 0; + (a[15] => z[18]) = 0; + (a[16] => z[18]) = 0; + (a[17] => z[18]) = 0; + (a[18] => z[18]) = 0; + (a[19] => z[18]) = 0; + (b[0] => z[18]) = 0; + (b[1] => z[18]) = 0; + (b[2] => z[18]) = 0; + (b[3] => z[18]) = 0; + (b[4] => z[18]) = 0; + (b[5] => z[18]) = 0; + (b[6] => z[18]) = 0; + (b[7] => z[18]) = 0; + (b[8] => z[18]) = 0; + (b[9] => z[18]) = 0; + (b[10] => z[18]) = 0; + (b[11] => z[18]) = 0; + (b[12] => z[18]) = 0; + (b[13] => z[18]) = 0; + (b[14] => z[18]) = 0; + (b[15] => z[18]) = 0; + (b[16] => z[18]) = 0; + (b[17] => z[18]) = 0; + (a[0] => z[19]) = 0; + (a[1] => z[19]) = 0; + (a[2] => z[19]) = 0; + (a[3] => z[19]) = 0; + (a[4] => z[19]) = 0; + (a[5] => z[19]) = 0; + (a[6] => z[19]) = 0; + (a[7] => z[19]) = 0; + (a[8] => z[19]) = 0; + (a[9] => z[19]) = 0; + (a[10] => z[19]) = 0; + (a[11] => z[19]) = 0; + (a[12] => z[19]) = 0; + (a[13] => z[19]) = 0; + (a[14] => z[19]) = 0; + (a[15] => z[19]) = 0; + (a[16] => z[19]) = 0; + (a[17] => z[19]) = 0; + (a[18] => z[19]) = 0; + (a[19] => z[19]) = 0; + (b[0] => z[19]) = 0; + (b[1] => z[19]) = 0; + (b[2] => z[19]) = 0; + (b[3] => z[19]) = 0; + (b[4] => z[19]) = 0; + (b[5] => z[19]) = 0; + (b[6] => z[19]) = 0; + (b[7] => z[19]) = 0; + (b[8] => z[19]) = 0; + (b[9] => z[19]) = 0; + (b[10] => z[19]) = 0; + (b[11] => z[19]) = 0; + (b[12] => z[19]) = 0; + (b[13] => z[19]) = 0; + (b[14] => z[19]) = 0; + (b[15] => z[19]) = 0; + (b[16] => z[19]) = 0; + (b[17] => z[19]) = 0; + (a[0] => z[20]) = 0; + (a[1] => z[20]) = 0; + (a[2] => z[20]) = 0; + (a[3] => z[20]) = 0; + (a[4] => z[20]) = 0; + (a[5] => z[20]) = 0; + (a[6] => z[20]) = 0; + (a[7] => z[20]) = 0; + (a[8] => z[20]) = 0; + (a[9] => z[20]) = 0; + (a[10] => z[20]) = 0; + (a[11] => z[20]) = 0; + (a[12] => z[20]) = 0; + (a[13] => z[20]) = 0; + (a[14] => z[20]) = 0; + (a[15] => z[20]) = 0; + (a[16] => z[20]) = 0; + (a[17] => z[20]) = 0; + (a[18] => z[20]) = 0; + (a[19] => z[20]) = 0; + (b[0] => z[20]) = 0; + (b[1] => z[20]) = 0; + (b[2] => z[20]) = 0; + (b[3] => z[20]) = 0; + (b[4] => z[20]) = 0; + (b[5] => z[20]) = 0; + (b[6] => z[20]) = 0; + (b[7] => z[20]) = 0; + (b[8] => z[20]) = 0; + (b[9] => z[20]) = 0; + (b[10] => z[20]) = 0; + (b[11] => z[20]) = 0; + (b[12] => z[20]) = 0; + (b[13] => z[20]) = 0; + (b[14] => z[20]) = 0; + (b[15] => z[20]) = 0; + (b[16] => z[20]) = 0; + (b[17] => z[20]) = 0; + (a[0] => z[21]) = 0; + (a[1] => z[21]) = 0; + (a[2] => z[21]) = 0; + (a[3] => z[21]) = 0; + (a[4] => z[21]) = 0; + (a[5] => z[21]) = 0; + (a[6] => z[21]) = 0; + (a[7] => z[21]) = 0; + (a[8] => z[21]) = 0; + (a[9] => z[21]) = 0; + (a[10] => z[21]) = 0; + (a[11] => z[21]) = 0; + (a[12] => z[21]) = 0; + (a[13] => z[21]) = 0; + (a[14] => z[21]) = 0; + (a[15] => z[21]) = 0; + (a[16] => z[21]) = 0; + (a[17] => z[21]) = 0; + (a[18] => z[21]) = 0; + (a[19] => z[21]) = 0; + (b[0] => z[21]) = 0; + (b[1] => z[21]) = 0; + (b[2] => z[21]) = 0; + (b[3] => z[21]) = 0; + (b[4] => z[21]) = 0; + (b[5] => z[21]) = 0; + (b[6] => z[21]) = 0; + (b[7] => z[21]) = 0; + (b[8] => z[21]) = 0; + (b[9] => z[21]) = 0; + (b[10] => z[21]) = 0; + (b[11] => z[21]) = 0; + (b[12] => z[21]) = 0; + (b[13] => z[21]) = 0; + (b[14] => z[21]) = 0; + (b[15] => z[21]) = 0; + (b[16] => z[21]) = 0; + (b[17] => z[21]) = 0; + (a[0] => z[22]) = 0; + (a[1] => z[22]) = 0; + (a[2] => z[22]) = 0; + (a[3] => z[22]) = 0; + (a[4] => z[22]) = 0; + (a[5] => z[22]) = 0; + (a[6] => z[22]) = 0; + (a[7] => z[22]) = 0; + (a[8] => z[22]) = 0; + (a[9] => z[22]) = 0; + (a[10] => z[22]) = 0; + (a[11] => z[22]) = 0; + (a[12] => z[22]) = 0; + (a[13] => z[22]) = 0; + (a[14] => z[22]) = 0; + (a[15] => z[22]) = 0; + (a[16] => z[22]) = 0; + (a[17] => z[22]) = 0; + (a[18] => z[22]) = 0; + (a[19] => z[22]) = 0; + (b[0] => z[22]) = 0; + (b[1] => z[22]) = 0; + (b[2] => z[22]) = 0; + (b[3] => z[22]) = 0; + (b[4] => z[22]) = 0; + (b[5] => z[22]) = 0; + (b[6] => z[22]) = 0; + (b[7] => z[22]) = 0; + (b[8] => z[22]) = 0; + (b[9] => z[22]) = 0; + (b[10] => z[22]) = 0; + (b[11] => z[22]) = 0; + (b[12] => z[22]) = 0; + (b[13] => z[22]) = 0; + (b[14] => z[22]) = 0; + (b[15] => z[22]) = 0; + (b[16] => z[22]) = 0; + (b[17] => z[22]) = 0; + (a[0] => z[23]) = 0; + (a[1] => z[23]) = 0; + (a[2] => z[23]) = 0; + (a[3] => z[23]) = 0; + (a[4] => z[23]) = 0; + (a[5] => z[23]) = 0; + (a[6] => z[23]) = 0; + (a[7] => z[23]) = 0; + (a[8] => z[23]) = 0; + (a[9] => z[23]) = 0; + (a[10] => z[23]) = 0; + (a[11] => z[23]) = 0; + (a[12] => z[23]) = 0; + (a[13] => z[23]) = 0; + (a[14] => z[23]) = 0; + (a[15] => z[23]) = 0; + (a[16] => z[23]) = 0; + (a[17] => z[23]) = 0; + (a[18] => z[23]) = 0; + (a[19] => z[23]) = 0; + (b[0] => z[23]) = 0; + (b[1] => z[23]) = 0; + (b[2] => z[23]) = 0; + (b[3] => z[23]) = 0; + (b[4] => z[23]) = 0; + (b[5] => z[23]) = 0; + (b[6] => z[23]) = 0; + (b[7] => z[23]) = 0; + (b[8] => z[23]) = 0; + (b[9] => z[23]) = 0; + (b[10] => z[23]) = 0; + (b[11] => z[23]) = 0; + (b[12] => z[23]) = 0; + (b[13] => z[23]) = 0; + (b[14] => z[23]) = 0; + (b[15] => z[23]) = 0; + (b[16] => z[23]) = 0; + (b[17] => z[23]) = 0; + (a[0] => z[24]) = 0; + (a[1] => z[24]) = 0; + (a[2] => z[24]) = 0; + (a[3] => z[24]) = 0; + (a[4] => z[24]) = 0; + (a[5] => z[24]) = 0; + (a[6] => z[24]) = 0; + (a[7] => z[24]) = 0; + (a[8] => z[24]) = 0; + (a[9] => z[24]) = 0; + (a[10] => z[24]) = 0; + (a[11] => z[24]) = 0; + (a[12] => z[24]) = 0; + (a[13] => z[24]) = 0; + (a[14] => z[24]) = 0; + (a[15] => z[24]) = 0; + (a[16] => z[24]) = 0; + (a[17] => z[24]) = 0; + (a[18] => z[24]) = 0; + (a[19] => z[24]) = 0; + (b[0] => z[24]) = 0; + (b[1] => z[24]) = 0; + (b[2] => z[24]) = 0; + (b[3] => z[24]) = 0; + (b[4] => z[24]) = 0; + (b[5] => z[24]) = 0; + (b[6] => z[24]) = 0; + (b[7] => z[24]) = 0; + (b[8] => z[24]) = 0; + (b[9] => z[24]) = 0; + (b[10] => z[24]) = 0; + (b[11] => z[24]) = 0; + (b[12] => z[24]) = 0; + (b[13] => z[24]) = 0; + (b[14] => z[24]) = 0; + (b[15] => z[24]) = 0; + (b[16] => z[24]) = 0; + (b[17] => z[24]) = 0; + (a[0] => z[25]) = 0; + (a[1] => z[25]) = 0; + (a[2] => z[25]) = 0; + (a[3] => z[25]) = 0; + (a[4] => z[25]) = 0; + (a[5] => z[25]) = 0; + (a[6] => z[25]) = 0; + (a[7] => z[25]) = 0; + (a[8] => z[25]) = 0; + (a[9] => z[25]) = 0; + (a[10] => z[25]) = 0; + (a[11] => z[25]) = 0; + (a[12] => z[25]) = 0; + (a[13] => z[25]) = 0; + (a[14] => z[25]) = 0; + (a[15] => z[25]) = 0; + (a[16] => z[25]) = 0; + (a[17] => z[25]) = 0; + (a[18] => z[25]) = 0; + (a[19] => z[25]) = 0; + (b[0] => z[25]) = 0; + (b[1] => z[25]) = 0; + (b[2] => z[25]) = 0; + (b[3] => z[25]) = 0; + (b[4] => z[25]) = 0; + (b[5] => z[25]) = 0; + (b[6] => z[25]) = 0; + (b[7] => z[25]) = 0; + (b[8] => z[25]) = 0; + (b[9] => z[25]) = 0; + (b[10] => z[25]) = 0; + (b[11] => z[25]) = 0; + (b[12] => z[25]) = 0; + (b[13] => z[25]) = 0; + (b[14] => z[25]) = 0; + (b[15] => z[25]) = 0; + (b[16] => z[25]) = 0; + (b[17] => z[25]) = 0; + (a[0] => z[26]) = 0; + (a[1] => z[26]) = 0; + (a[2] => z[26]) = 0; + (a[3] => z[26]) = 0; + (a[4] => z[26]) = 0; + (a[5] => z[26]) = 0; + (a[6] => z[26]) = 0; + (a[7] => z[26]) = 0; + (a[8] => z[26]) = 0; + (a[9] => z[26]) = 0; + (a[10] => z[26]) = 0; + (a[11] => z[26]) = 0; + (a[12] => z[26]) = 0; + (a[13] => z[26]) = 0; + (a[14] => z[26]) = 0; + (a[15] => z[26]) = 0; + (a[16] => z[26]) = 0; + (a[17] => z[26]) = 0; + (a[18] => z[26]) = 0; + (a[19] => z[26]) = 0; + (b[0] => z[26]) = 0; + (b[1] => z[26]) = 0; + (b[2] => z[26]) = 0; + (b[3] => z[26]) = 0; + (b[4] => z[26]) = 0; + (b[5] => z[26]) = 0; + (b[6] => z[26]) = 0; + (b[7] => z[26]) = 0; + (b[8] => z[26]) = 0; + (b[9] => z[26]) = 0; + (b[10] => z[26]) = 0; + (b[11] => z[26]) = 0; + (b[12] => z[26]) = 0; + (b[13] => z[26]) = 0; + (b[14] => z[26]) = 0; + (b[15] => z[26]) = 0; + (b[16] => z[26]) = 0; + (b[17] => z[26]) = 0; + (a[0] => z[27]) = 0; + (a[1] => z[27]) = 0; + (a[2] => z[27]) = 0; + (a[3] => z[27]) = 0; + (a[4] => z[27]) = 0; + (a[5] => z[27]) = 0; + (a[6] => z[27]) = 0; + (a[7] => z[27]) = 0; + (a[8] => z[27]) = 0; + (a[9] => z[27]) = 0; + (a[10] => z[27]) = 0; + (a[11] => z[27]) = 0; + (a[12] => z[27]) = 0; + (a[13] => z[27]) = 0; + (a[14] => z[27]) = 0; + (a[15] => z[27]) = 0; + (a[16] => z[27]) = 0; + (a[17] => z[27]) = 0; + (a[18] => z[27]) = 0; + (a[19] => z[27]) = 0; + (b[0] => z[27]) = 0; + (b[1] => z[27]) = 0; + (b[2] => z[27]) = 0; + (b[3] => z[27]) = 0; + (b[4] => z[27]) = 0; + (b[5] => z[27]) = 0; + (b[6] => z[27]) = 0; + (b[7] => z[27]) = 0; + (b[8] => z[27]) = 0; + (b[9] => z[27]) = 0; + (b[10] => z[27]) = 0; + (b[11] => z[27]) = 0; + (b[12] => z[27]) = 0; + (b[13] => z[27]) = 0; + (b[14] => z[27]) = 0; + (b[15] => z[27]) = 0; + (b[16] => z[27]) = 0; + (b[17] => z[27]) = 0; + (a[0] => z[28]) = 0; + (a[1] => z[28]) = 0; + (a[2] => z[28]) = 0; + (a[3] => z[28]) = 0; + (a[4] => z[28]) = 0; + (a[5] => z[28]) = 0; + (a[6] => z[28]) = 0; + (a[7] => z[28]) = 0; + (a[8] => z[28]) = 0; + (a[9] => z[28]) = 0; + (a[10] => z[28]) = 0; + (a[11] => z[28]) = 0; + (a[12] => z[28]) = 0; + (a[13] => z[28]) = 0; + (a[14] => z[28]) = 0; + (a[15] => z[28]) = 0; + (a[16] => z[28]) = 0; + (a[17] => z[28]) = 0; + (a[18] => z[28]) = 0; + (a[19] => z[28]) = 0; + (b[0] => z[28]) = 0; + (b[1] => z[28]) = 0; + (b[2] => z[28]) = 0; + (b[3] => z[28]) = 0; + (b[4] => z[28]) = 0; + (b[5] => z[28]) = 0; + (b[6] => z[28]) = 0; + (b[7] => z[28]) = 0; + (b[8] => z[28]) = 0; + (b[9] => z[28]) = 0; + (b[10] => z[28]) = 0; + (b[11] => z[28]) = 0; + (b[12] => z[28]) = 0; + (b[13] => z[28]) = 0; + (b[14] => z[28]) = 0; + (b[15] => z[28]) = 0; + (b[16] => z[28]) = 0; + (b[17] => z[28]) = 0; + (a[0] => z[29]) = 0; + (a[1] => z[29]) = 0; + (a[2] => z[29]) = 0; + (a[3] => z[29]) = 0; + (a[4] => z[29]) = 0; + (a[5] => z[29]) = 0; + (a[6] => z[29]) = 0; + (a[7] => z[29]) = 0; + (a[8] => z[29]) = 0; + (a[9] => z[29]) = 0; + (a[10] => z[29]) = 0; + (a[11] => z[29]) = 0; + (a[12] => z[29]) = 0; + (a[13] => z[29]) = 0; + (a[14] => z[29]) = 0; + (a[15] => z[29]) = 0; + (a[16] => z[29]) = 0; + (a[17] => z[29]) = 0; + (a[18] => z[29]) = 0; + (a[19] => z[29]) = 0; + (b[0] => z[29]) = 0; + (b[1] => z[29]) = 0; + (b[2] => z[29]) = 0; + (b[3] => z[29]) = 0; + (b[4] => z[29]) = 0; + (b[5] => z[29]) = 0; + (b[6] => z[29]) = 0; + (b[7] => z[29]) = 0; + (b[8] => z[29]) = 0; + (b[9] => z[29]) = 0; + (b[10] => z[29]) = 0; + (b[11] => z[29]) = 0; + (b[12] => z[29]) = 0; + (b[13] => z[29]) = 0; + (b[14] => z[29]) = 0; + (b[15] => z[29]) = 0; + (b[16] => z[29]) = 0; + (b[17] => z[29]) = 0; + (a[0] => z[30]) = 0; + (a[1] => z[30]) = 0; + (a[2] => z[30]) = 0; + (a[3] => z[30]) = 0; + (a[4] => z[30]) = 0; + (a[5] => z[30]) = 0; + (a[6] => z[30]) = 0; + (a[7] => z[30]) = 0; + (a[8] => z[30]) = 0; + (a[9] => z[30]) = 0; + (a[10] => z[30]) = 0; + (a[11] => z[30]) = 0; + (a[12] => z[30]) = 0; + (a[13] => z[30]) = 0; + (a[14] => z[30]) = 0; + (a[15] => z[30]) = 0; + (a[16] => z[30]) = 0; + (a[17] => z[30]) = 0; + (a[18] => z[30]) = 0; + (a[19] => z[30]) = 0; + (b[0] => z[30]) = 0; + (b[1] => z[30]) = 0; + (b[2] => z[30]) = 0; + (b[3] => z[30]) = 0; + (b[4] => z[30]) = 0; + (b[5] => z[30]) = 0; + (b[6] => z[30]) = 0; + (b[7] => z[30]) = 0; + (b[8] => z[30]) = 0; + (b[9] => z[30]) = 0; + (b[10] => z[30]) = 0; + (b[11] => z[30]) = 0; + (b[12] => z[30]) = 0; + (b[13] => z[30]) = 0; + (b[14] => z[30]) = 0; + (b[15] => z[30]) = 0; + (b[16] => z[30]) = 0; + (b[17] => z[30]) = 0; + (a[0] => z[31]) = 0; + (a[1] => z[31]) = 0; + (a[2] => z[31]) = 0; + (a[3] => z[31]) = 0; + (a[4] => z[31]) = 0; + (a[5] => z[31]) = 0; + (a[6] => z[31]) = 0; + (a[7] => z[31]) = 0; + (a[8] => z[31]) = 0; + (a[9] => z[31]) = 0; + (a[10] => z[31]) = 0; + (a[11] => z[31]) = 0; + (a[12] => z[31]) = 0; + (a[13] => z[31]) = 0; + (a[14] => z[31]) = 0; + (a[15] => z[31]) = 0; + (a[16] => z[31]) = 0; + (a[17] => z[31]) = 0; + (a[18] => z[31]) = 0; + (a[19] => z[31]) = 0; + (b[0] => z[31]) = 0; + (b[1] => z[31]) = 0; + (b[2] => z[31]) = 0; + (b[3] => z[31]) = 0; + (b[4] => z[31]) = 0; + (b[5] => z[31]) = 0; + (b[6] => z[31]) = 0; + (b[7] => z[31]) = 0; + (b[8] => z[31]) = 0; + (b[9] => z[31]) = 0; + (b[10] => z[31]) = 0; + (b[11] => z[31]) = 0; + (b[12] => z[31]) = 0; + (b[13] => z[31]) = 0; + (b[14] => z[31]) = 0; + (b[15] => z[31]) = 0; + (b[16] => z[31]) = 0; + (b[17] => z[31]) = 0; + (a[0] => z[32]) = 0; + (a[1] => z[32]) = 0; + (a[2] => z[32]) = 0; + (a[3] => z[32]) = 0; + (a[4] => z[32]) = 0; + (a[5] => z[32]) = 0; + (a[6] => z[32]) = 0; + (a[7] => z[32]) = 0; + (a[8] => z[32]) = 0; + (a[9] => z[32]) = 0; + (a[10] => z[32]) = 0; + (a[11] => z[32]) = 0; + (a[12] => z[32]) = 0; + (a[13] => z[32]) = 0; + (a[14] => z[32]) = 0; + (a[15] => z[32]) = 0; + (a[16] => z[32]) = 0; + (a[17] => z[32]) = 0; + (a[18] => z[32]) = 0; + (a[19] => z[32]) = 0; + (b[0] => z[32]) = 0; + (b[1] => z[32]) = 0; + (b[2] => z[32]) = 0; + (b[3] => z[32]) = 0; + (b[4] => z[32]) = 0; + (b[5] => z[32]) = 0; + (b[6] => z[32]) = 0; + (b[7] => z[32]) = 0; + (b[8] => z[32]) = 0; + (b[9] => z[32]) = 0; + (b[10] => z[32]) = 0; + (b[11] => z[32]) = 0; + (b[12] => z[32]) = 0; + (b[13] => z[32]) = 0; + (b[14] => z[32]) = 0; + (b[15] => z[32]) = 0; + (b[16] => z[32]) = 0; + (b[17] => z[32]) = 0; + (a[0] => z[33]) = 0; + (a[1] => z[33]) = 0; + (a[2] => z[33]) = 0; + (a[3] => z[33]) = 0; + (a[4] => z[33]) = 0; + (a[5] => z[33]) = 0; + (a[6] => z[33]) = 0; + (a[7] => z[33]) = 0; + (a[8] => z[33]) = 0; + (a[9] => z[33]) = 0; + (a[10] => z[33]) = 0; + (a[11] => z[33]) = 0; + (a[12] => z[33]) = 0; + (a[13] => z[33]) = 0; + (a[14] => z[33]) = 0; + (a[15] => z[33]) = 0; + (a[16] => z[33]) = 0; + (a[17] => z[33]) = 0; + (a[18] => z[33]) = 0; + (a[19] => z[33]) = 0; + (b[0] => z[33]) = 0; + (b[1] => z[33]) = 0; + (b[2] => z[33]) = 0; + (b[3] => z[33]) = 0; + (b[4] => z[33]) = 0; + (b[5] => z[33]) = 0; + (b[6] => z[33]) = 0; + (b[7] => z[33]) = 0; + (b[8] => z[33]) = 0; + (b[9] => z[33]) = 0; + (b[10] => z[33]) = 0; + (b[11] => z[33]) = 0; + (b[12] => z[33]) = 0; + (b[13] => z[33]) = 0; + (b[14] => z[33]) = 0; + (b[15] => z[33]) = 0; + (b[16] => z[33]) = 0; + (b[17] => z[33]) = 0; + (a[0] => z[34]) = 0; + (a[1] => z[34]) = 0; + (a[2] => z[34]) = 0; + (a[3] => z[34]) = 0; + (a[4] => z[34]) = 0; + (a[5] => z[34]) = 0; + (a[6] => z[34]) = 0; + (a[7] => z[34]) = 0; + (a[8] => z[34]) = 0; + (a[9] => z[34]) = 0; + (a[10] => z[34]) = 0; + (a[11] => z[34]) = 0; + (a[12] => z[34]) = 0; + (a[13] => z[34]) = 0; + (a[14] => z[34]) = 0; + (a[15] => z[34]) = 0; + (a[16] => z[34]) = 0; + (a[17] => z[34]) = 0; + (a[18] => z[34]) = 0; + (a[19] => z[34]) = 0; + (b[0] => z[34]) = 0; + (b[1] => z[34]) = 0; + (b[2] => z[34]) = 0; + (b[3] => z[34]) = 0; + (b[4] => z[34]) = 0; + (b[5] => z[34]) = 0; + (b[6] => z[34]) = 0; + (b[7] => z[34]) = 0; + (b[8] => z[34]) = 0; + (b[9] => z[34]) = 0; + (b[10] => z[34]) = 0; + (b[11] => z[34]) = 0; + (b[12] => z[34]) = 0; + (b[13] => z[34]) = 0; + (b[14] => z[34]) = 0; + (b[15] => z[34]) = 0; + (b[16] => z[34]) = 0; + (b[17] => z[34]) = 0; + (a[0] => z[35]) = 0; + (a[1] => z[35]) = 0; + (a[2] => z[35]) = 0; + (a[3] => z[35]) = 0; + (a[4] => z[35]) = 0; + (a[5] => z[35]) = 0; + (a[6] => z[35]) = 0; + (a[7] => z[35]) = 0; + (a[8] => z[35]) = 0; + (a[9] => z[35]) = 0; + (a[10] => z[35]) = 0; + (a[11] => z[35]) = 0; + (a[12] => z[35]) = 0; + (a[13] => z[35]) = 0; + (a[14] => z[35]) = 0; + (a[15] => z[35]) = 0; + (a[16] => z[35]) = 0; + (a[17] => z[35]) = 0; + (a[18] => z[35]) = 0; + (a[19] => z[35]) = 0; + (b[0] => z[35]) = 0; + (b[1] => z[35]) = 0; + (b[2] => z[35]) = 0; + (b[3] => z[35]) = 0; + (b[4] => z[35]) = 0; + (b[5] => z[35]) = 0; + (b[6] => z[35]) = 0; + (b[7] => z[35]) = 0; + (b[8] => z[35]) = 0; + (b[9] => z[35]) = 0; + (b[10] => z[35]) = 0; + (b[11] => z[35]) = 0; + (b[12] => z[35]) = 0; + (b[13] => z[35]) = 0; + (b[14] => z[35]) = 0; + (b[15] => z[35]) = 0; + (b[16] => z[35]) = 0; + (b[17] => z[35]) = 0; + (a[0] => z[36]) = 0; + (a[1] => z[36]) = 0; + (a[2] => z[36]) = 0; + (a[3] => z[36]) = 0; + (a[4] => z[36]) = 0; + (a[5] => z[36]) = 0; + (a[6] => z[36]) = 0; + (a[7] => z[36]) = 0; + (a[8] => z[36]) = 0; + (a[9] => z[36]) = 0; + (a[10] => z[36]) = 0; + (a[11] => z[36]) = 0; + (a[12] => z[36]) = 0; + (a[13] => z[36]) = 0; + (a[14] => z[36]) = 0; + (a[15] => z[36]) = 0; + (a[16] => z[36]) = 0; + (a[17] => z[36]) = 0; + (a[18] => z[36]) = 0; + (a[19] => z[36]) = 0; + (b[0] => z[36]) = 0; + (b[1] => z[36]) = 0; + (b[2] => z[36]) = 0; + (b[3] => z[36]) = 0; + (b[4] => z[36]) = 0; + (b[5] => z[36]) = 0; + (b[6] => z[36]) = 0; + (b[7] => z[36]) = 0; + (b[8] => z[36]) = 0; + (b[9] => z[36]) = 0; + (b[10] => z[36]) = 0; + (b[11] => z[36]) = 0; + (b[12] => z[36]) = 0; + (b[13] => z[36]) = 0; + (b[14] => z[36]) = 0; + (b[15] => z[36]) = 0; + (b[16] => z[36]) = 0; + (b[17] => z[36]) = 0; + (a[0] => z[37]) = 0; + (a[1] => z[37]) = 0; + (a[2] => z[37]) = 0; + (a[3] => z[37]) = 0; + (a[4] => z[37]) = 0; + (a[5] => z[37]) = 0; + (a[6] => z[37]) = 0; + (a[7] => z[37]) = 0; + (a[8] => z[37]) = 0; + (a[9] => z[37]) = 0; + (a[10] => z[37]) = 0; + (a[11] => z[37]) = 0; + (a[12] => z[37]) = 0; + (a[13] => z[37]) = 0; + (a[14] => z[37]) = 0; + (a[15] => z[37]) = 0; + (a[16] => z[37]) = 0; + (a[17] => z[37]) = 0; + (a[18] => z[37]) = 0; + (a[19] => z[37]) = 0; + (b[0] => z[37]) = 0; + (b[1] => z[37]) = 0; + (b[2] => z[37]) = 0; + (b[3] => z[37]) = 0; + (b[4] => z[37]) = 0; + (b[5] => z[37]) = 0; + (b[6] => z[37]) = 0; + (b[7] => z[37]) = 0; + (b[8] => z[37]) = 0; + (b[9] => z[37]) = 0; + (b[10] => z[37]) = 0; + (b[11] => z[37]) = 0; + (b[12] => z[37]) = 0; + (b[13] => z[37]) = 0; + (b[14] => z[37]) = 0; + (b[15] => z[37]) = 0; + (b[16] => z[37]) = 0; + (b[17] => z[37]) = 0; + (subtract => z[0]) = 0; + (subtract => z[1]) = 0; + (subtract => z[2]) = 0; + (subtract => z[3]) = 0; + (subtract => z[4]) = 0; + (subtract => z[5]) = 0; + (subtract => z[6]) = 0; + (subtract => z[7]) = 0; + (subtract => z[8]) = 0; + (subtract => z[9]) = 0; + (subtract => z[10]) = 0; + (subtract => z[11]) = 0; + (subtract => z[12]) = 0; + (subtract => z[13]) = 0; + (subtract => z[14]) = 0; + (subtract => z[15]) = 0; + (subtract => z[16]) = 0; + (subtract => z[17]) = 0; + (subtract => z[18]) = 0; + (subtract => z[19]) = 0; + (subtract => z[20]) = 0; + (subtract => z[21]) = 0; + (subtract => z[22]) = 0; + (subtract => z[23]) = 0; + (subtract => z[24]) = 0; + (subtract => z[25]) = 0; + (subtract => z[26]) = 0; + (subtract => z[27]) = 0; + (subtract => z[28]) = 0; + (subtract => z[29]) = 0; + (subtract => z[30]) = 0; + (subtract => z[31]) = 0; + (subtract => z[32]) = 0; + (subtract => z[33]) = 0; + (subtract => z[34]) = 0; + (subtract => z[35]) = 0; + (subtract => z[36]) = 0; + (subtract => z[37]) = 0; + (acc_fir[0] => z[0]) = 0; + (acc_fir[1] => z[0]) = 0; + (acc_fir[2] => z[0]) = 0; + (acc_fir[3] => z[0]) = 0; + (acc_fir[4] => z[0]) = 0; + (acc_fir[5] => z[0]) = 0; + (acc_fir[0] => z[1]) = 0; + (acc_fir[1] => z[1]) = 0; + (acc_fir[2] => z[1]) = 0; + (acc_fir[3] => z[1]) = 0; + (acc_fir[4] => z[1]) = 0; + (acc_fir[5] => z[1]) = 0; + (acc_fir[0] => z[2]) = 0; + (acc_fir[1] => z[2]) = 0; + (acc_fir[2] => z[2]) = 0; + (acc_fir[3] => z[2]) = 0; + (acc_fir[4] => z[2]) = 0; + (acc_fir[5] => z[2]) = 0; + (acc_fir[0] => z[3]) = 0; + (acc_fir[1] => z[3]) = 0; + (acc_fir[2] => z[3]) = 0; + (acc_fir[3] => z[3]) = 0; + (acc_fir[4] => z[3]) = 0; + (acc_fir[5] => z[3]) = 0; + (acc_fir[0] => z[4]) = 0; + (acc_fir[1] => z[4]) = 0; + (acc_fir[2] => z[4]) = 0; + (acc_fir[3] => z[4]) = 0; + (acc_fir[4] => z[4]) = 0; + (acc_fir[5] => z[4]) = 0; + (acc_fir[0] => z[5]) = 0; + (acc_fir[1] => z[5]) = 0; + (acc_fir[2] => z[5]) = 0; + (acc_fir[3] => z[5]) = 0; + (acc_fir[4] => z[5]) = 0; + (acc_fir[5] => z[5]) = 0; + (acc_fir[0] => z[6]) = 0; + (acc_fir[1] => z[6]) = 0; + (acc_fir[2] => z[6]) = 0; + (acc_fir[3] => z[6]) = 0; + (acc_fir[4] => z[6]) = 0; + (acc_fir[5] => z[6]) = 0; + (acc_fir[0] => z[7]) = 0; + (acc_fir[1] => z[7]) = 0; + (acc_fir[2] => z[7]) = 0; + (acc_fir[3] => z[7]) = 0; + (acc_fir[4] => z[7]) = 0; + (acc_fir[5] => z[7]) = 0; + (acc_fir[0] => z[8]) = 0; + (acc_fir[1] => z[8]) = 0; + (acc_fir[2] => z[8]) = 0; + (acc_fir[3] => z[8]) = 0; + (acc_fir[4] => z[8]) = 0; + (acc_fir[5] => z[8]) = 0; + (acc_fir[0] => z[9]) = 0; + (acc_fir[1] => z[9]) = 0; + (acc_fir[2] => z[9]) = 0; + (acc_fir[3] => z[9]) = 0; + (acc_fir[4] => z[9]) = 0; + (acc_fir[5] => z[9]) = 0; + (acc_fir[0] => z[10]) = 0; + (acc_fir[1] => z[10]) = 0; + (acc_fir[2] => z[10]) = 0; + (acc_fir[3] => z[10]) = 0; + (acc_fir[4] => z[10]) = 0; + (acc_fir[5] => z[10]) = 0; + (acc_fir[0] => z[11]) = 0; + (acc_fir[1] => z[11]) = 0; + (acc_fir[2] => z[11]) = 0; + (acc_fir[3] => z[11]) = 0; + (acc_fir[4] => z[11]) = 0; + (acc_fir[5] => z[11]) = 0; + (acc_fir[0] => z[12]) = 0; + (acc_fir[1] => z[12]) = 0; + (acc_fir[2] => z[12]) = 0; + (acc_fir[3] => z[12]) = 0; + (acc_fir[4] => z[12]) = 0; + (acc_fir[5] => z[12]) = 0; + (acc_fir[0] => z[13]) = 0; + (acc_fir[1] => z[13]) = 0; + (acc_fir[2] => z[13]) = 0; + (acc_fir[3] => z[13]) = 0; + (acc_fir[4] => z[13]) = 0; + (acc_fir[5] => z[13]) = 0; + (acc_fir[0] => z[14]) = 0; + (acc_fir[1] => z[14]) = 0; + (acc_fir[2] => z[14]) = 0; + (acc_fir[3] => z[14]) = 0; + (acc_fir[4] => z[14]) = 0; + (acc_fir[5] => z[14]) = 0; + (acc_fir[0] => z[15]) = 0; + (acc_fir[1] => z[15]) = 0; + (acc_fir[2] => z[15]) = 0; + (acc_fir[3] => z[15]) = 0; + (acc_fir[4] => z[15]) = 0; + (acc_fir[5] => z[15]) = 0; + (acc_fir[0] => z[16]) = 0; + (acc_fir[1] => z[16]) = 0; + (acc_fir[2] => z[16]) = 0; + (acc_fir[3] => z[16]) = 0; + (acc_fir[4] => z[16]) = 0; + (acc_fir[5] => z[16]) = 0; + (acc_fir[0] => z[17]) = 0; + (acc_fir[1] => z[17]) = 0; + (acc_fir[2] => z[17]) = 0; + (acc_fir[3] => z[17]) = 0; + (acc_fir[4] => z[17]) = 0; + (acc_fir[5] => z[17]) = 0; + (acc_fir[0] => z[18]) = 0; + (acc_fir[1] => z[18]) = 0; + (acc_fir[2] => z[18]) = 0; + (acc_fir[3] => z[18]) = 0; + (acc_fir[4] => z[18]) = 0; + (acc_fir[5] => z[18]) = 0; + (acc_fir[0] => z[19]) = 0; + (acc_fir[1] => z[19]) = 0; + (acc_fir[2] => z[19]) = 0; + (acc_fir[3] => z[19]) = 0; + (acc_fir[4] => z[19]) = 0; + (acc_fir[5] => z[19]) = 0; + (acc_fir[0] => z[20]) = 0; + (acc_fir[1] => z[20]) = 0; + (acc_fir[2] => z[20]) = 0; + (acc_fir[3] => z[20]) = 0; + (acc_fir[4] => z[20]) = 0; + (acc_fir[5] => z[20]) = 0; + (acc_fir[0] => z[21]) = 0; + (acc_fir[1] => z[21]) = 0; + (acc_fir[2] => z[21]) = 0; + (acc_fir[3] => z[21]) = 0; + (acc_fir[4] => z[21]) = 0; + (acc_fir[5] => z[21]) = 0; + (acc_fir[0] => z[22]) = 0; + (acc_fir[1] => z[22]) = 0; + (acc_fir[2] => z[22]) = 0; + (acc_fir[3] => z[22]) = 0; + (acc_fir[4] => z[22]) = 0; + (acc_fir[5] => z[22]) = 0; + (acc_fir[0] => z[23]) = 0; + (acc_fir[1] => z[23]) = 0; + (acc_fir[2] => z[23]) = 0; + (acc_fir[3] => z[23]) = 0; + (acc_fir[4] => z[23]) = 0; + (acc_fir[5] => z[23]) = 0; + (acc_fir[0] => z[24]) = 0; + (acc_fir[1] => z[24]) = 0; + (acc_fir[2] => z[24]) = 0; + (acc_fir[3] => z[24]) = 0; + (acc_fir[4] => z[24]) = 0; + (acc_fir[5] => z[24]) = 0; + (acc_fir[0] => z[25]) = 0; + (acc_fir[1] => z[25]) = 0; + (acc_fir[2] => z[25]) = 0; + (acc_fir[3] => z[25]) = 0; + (acc_fir[4] => z[25]) = 0; + (acc_fir[5] => z[25]) = 0; + (acc_fir[0] => z[26]) = 0; + (acc_fir[1] => z[26]) = 0; + (acc_fir[2] => z[26]) = 0; + (acc_fir[3] => z[26]) = 0; + (acc_fir[4] => z[26]) = 0; + (acc_fir[5] => z[26]) = 0; + (acc_fir[0] => z[27]) = 0; + (acc_fir[1] => z[27]) = 0; + (acc_fir[2] => z[27]) = 0; + (acc_fir[3] => z[27]) = 0; + (acc_fir[4] => z[27]) = 0; + (acc_fir[5] => z[27]) = 0; + (acc_fir[0] => z[28]) = 0; + (acc_fir[1] => z[28]) = 0; + (acc_fir[2] => z[28]) = 0; + (acc_fir[3] => z[28]) = 0; + (acc_fir[4] => z[28]) = 0; + (acc_fir[5] => z[28]) = 0; + (acc_fir[0] => z[29]) = 0; + (acc_fir[1] => z[29]) = 0; + (acc_fir[2] => z[29]) = 0; + (acc_fir[3] => z[29]) = 0; + (acc_fir[4] => z[29]) = 0; + (acc_fir[5] => z[29]) = 0; + (acc_fir[0] => z[30]) = 0; + (acc_fir[1] => z[30]) = 0; + (acc_fir[2] => z[30]) = 0; + (acc_fir[3] => z[30]) = 0; + (acc_fir[4] => z[30]) = 0; + (acc_fir[5] => z[30]) = 0; + (acc_fir[0] => z[31]) = 0; + (acc_fir[1] => z[31]) = 0; + (acc_fir[2] => z[31]) = 0; + (acc_fir[3] => z[31]) = 0; + (acc_fir[4] => z[31]) = 0; + (acc_fir[5] => z[31]) = 0; + (acc_fir[0] => z[32]) = 0; + (acc_fir[1] => z[32]) = 0; + (acc_fir[2] => z[32]) = 0; + (acc_fir[3] => z[32]) = 0; + (acc_fir[4] => z[32]) = 0; + (acc_fir[5] => z[32]) = 0; + (acc_fir[0] => z[33]) = 0; + (acc_fir[1] => z[33]) = 0; + (acc_fir[2] => z[33]) = 0; + (acc_fir[3] => z[33]) = 0; + (acc_fir[4] => z[33]) = 0; + (acc_fir[5] => z[33]) = 0; + (acc_fir[0] => z[34]) = 0; + (acc_fir[1] => z[34]) = 0; + (acc_fir[2] => z[34]) = 0; + (acc_fir[3] => z[34]) = 0; + (acc_fir[4] => z[34]) = 0; + (acc_fir[5] => z[34]) = 0; + (acc_fir[0] => z[35]) = 0; + (acc_fir[1] => z[35]) = 0; + (acc_fir[2] => z[35]) = 0; + (acc_fir[3] => z[35]) = 0; + (acc_fir[4] => z[35]) = 0; + (acc_fir[5] => z[35]) = 0; + (acc_fir[0] => z[36]) = 0; + (acc_fir[1] => z[36]) = 0; + (acc_fir[2] => z[36]) = 0; + (acc_fir[3] => z[36]) = 0; + (acc_fir[4] => z[36]) = 0; + (acc_fir[5] => z[36]) = 0; + (acc_fir[0] => z[37]) = 0; + (acc_fir[1] => z[37]) = 0; + (acc_fir[2] => z[37]) = 0; + (acc_fir[3] => z[37]) = 0; + (acc_fir[4] => z[37]) = 0; + (acc_fir[5] => z[37]) = 0; + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCin (2, 3) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCin (6, 7) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCin (6, 7) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire load_acc, + input wire [ 2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCout (1) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCout (1) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCout (5) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCout (5) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module dsp_t1_20x18x64_cfg_ports ( + input wire [19:0] a_i, + input wire [17:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [37:0] z_o, + output wire [17:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire [ 2:0] output_select_i, + input wire saturate_enable_i, + input wire [ 5:0] shift_right_i, + input wire round_i, + input wire subtract_i, + input wire register_inputs_i +); + + parameter [19:0] COEFF_0 = 20'd0; + parameter [19:0] COEFF_1 = 20'd0; + parameter [19:0] COEFF_2 = 20'd0; + parameter [19:0] COEFF_3 = 20'd0; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a_i), + .b(b_i), + .z(z_o), + .dly_b(dly_b_o), + + .f_mode(1'b0), // 20x18x64 DSP + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + + .saturate_enable(saturate_enable_i), + .output_select(output_select_i), + .round(round_i), + .shift_right(shift_right_i), + .subtract(subtract_i), + .register_inputs(register_inputs_i) + ); +endmodule + +module dsp_t1_10x9x32_cfg_ports ( + input wire [ 9:0] a_i, + input wire [ 8:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [18:0] z_o, + output wire [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire [ 2:0] output_select_i, + input wire saturate_enable_i, + input wire [ 5:0] shift_right_i, + input wire round_i, + input wire subtract_i, + input wire register_inputs_i +); + + parameter [9:0] COEFF_0 = 10'd0; + parameter [9:0] COEFF_1 = 10'd0; + parameter [9:0] COEFF_2 = 10'd0; + parameter [9:0] COEFF_3 = 10'd0; + + wire [18:0] z_rem; + wire [8:0] dly_b_rem; + + QL_DSP2 #( + .MODE_BITS({10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0}) + ) dsp ( + .a({10'd0, a_i}), + .b({9'd0, b_i}), + .z({z_rem, z_o}), + .dly_b({dly_b_rem, dly_b_o}), + + .f_mode(1'b1), // 10x9x32 DSP + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + + .saturate_enable(saturate_enable_i), + .output_select(output_select_i), + .round(round_i), + .shift_right(shift_right_i), + .subtract(subtract_i), + .register_inputs(register_inputs_i) + ); +endmodule + +module dsp_t1_sim_cfg_ports # ( + parameter NBITS_ACC = 64, + parameter NBITS_A = 20, + parameter NBITS_B = 18, + parameter NBITS_Z = 38 +)( + input wire [NBITS_A-1:0] a_i, + input wire [NBITS_B-1:0] b_i, + output wire [NBITS_Z-1:0] z_o, + output reg [NBITS_B-1:0] dly_b_o, + + input wire [5:0] acc_fir_i, + input wire [2:0] feedback_i, + input wire load_acc_i, + + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire clock_i, + input wire s_reset, + + input wire saturate_enable_i, + input wire [2:0] output_select_i, + input wire round_i, + input wire [5:0] shift_right_i, + input wire subtract_i, + input wire register_inputs_i, + input wire [NBITS_A-1:0] coef_0_i, + input wire [NBITS_A-1:0] coef_1_i, + input wire [NBITS_A-1:0] coef_2_i, + input wire [NBITS_A-1:0] coef_3_i +); + +// FIXME: The version of Icarus Verilog from Conda seems not to recognize the +// $error macro. Disable this sanity check for now because of that. + + + // Input registers + reg [NBITS_A-1:0] r_a; + reg [NBITS_B-1:0] r_b; + reg [5:0] r_acc_fir; + reg r_unsigned_a; + reg r_unsigned_b; + reg r_load_acc; + reg [2:0] r_feedback; + reg [5:0] r_shift_d1; + reg [5:0] r_shift_d2; + reg r_subtract; + reg r_sat; + reg r_rnd; + reg [NBITS_ACC-1:0] acc; + + initial begin + r_a <= 0; + r_b <= 0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + end + + always @(posedge clock_i or posedge s_reset) begin + if (s_reset) begin + + r_a <= 'h0; + r_b <= 'h0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + + end else begin + + r_a <= a_i; + r_b <= b_i; + + r_acc_fir <= acc_fir_i; + r_unsigned_a <= unsigned_a_i; + r_unsigned_b <= unsigned_b_i; + r_feedback <= feedback_i; + r_shift_d1 <= shift_right_i; + r_shift_d2 <= r_shift_d1; + r_subtract <= subtract_i; + r_load_acc <= load_acc_i; + r_sat <= r_sat; + r_rnd <= r_rnd; + + end + end + + // Registered / non-registered input path select + wire [NBITS_A-1:0] a = register_inputs_i ? r_a : a_i; + wire [NBITS_B-1:0] b = register_inputs_i ? r_b : b_i; + + wire [5:0] acc_fir = register_inputs_i ? r_acc_fir : acc_fir_i; + wire unsigned_a = register_inputs_i ? r_unsigned_a : unsigned_a_i; + wire unsigned_b = register_inputs_i ? r_unsigned_b : unsigned_b_i; + wire [2:0] feedback = register_inputs_i ? r_feedback : feedback_i; + wire load_acc = register_inputs_i ? r_load_acc : load_acc_i; + wire subtract = register_inputs_i ? r_subtract : subtract_i; + wire sat = register_inputs_i ? r_sat : saturate_enable_i; + wire rnd = register_inputs_i ? r_rnd : round_i; + + // Shift right control + wire [5:0] shift_d1 = register_inputs_i ? r_shift_d1 : shift_right_i; + wire [5:0] shift_d2 = output_select_i[1] ? shift_d1 : r_shift_d2; + + // Multiplier + wire unsigned_mode = unsigned_a & unsigned_b; + wire [NBITS_A-1:0] mult_a; + assign mult_a = (feedback == 3'h0) ? a : + (feedback == 3'h1) ? a : + (feedback == 3'h2) ? a : + (feedback == 3'h3) ? acc[NBITS_A-1:0] : + (feedback == 3'h4) ? coef_0_i : + (feedback == 3'h5) ? coef_1_i : + (feedback == 3'h6) ? coef_2_i : + coef_3_i; // if feedback == 3'h7 + + wire [NBITS_B-1:0] mult_b = (feedback == 2'h2) ? {NBITS_B{1'b0}} : b; + + wire [NBITS_A-1:0] mult_sgn_a = mult_a[NBITS_A-1]; + wire [NBITS_A-1:0] mult_mag_a = (mult_sgn_a && !unsigned_a) ? (~mult_a + 1) : mult_a; + wire [NBITS_B-1:0] mult_sgn_b = mult_b[NBITS_B-1]; + wire [NBITS_B-1:0] mult_mag_b = (mult_sgn_b && !unsigned_b) ? (~mult_b + 1) : mult_b; + + wire [NBITS_A+NBITS_B-1:0] mult_mag = mult_mag_a * mult_mag_b; + wire mult_sgn = (mult_sgn_a && !unsigned_a) ^ (mult_sgn_b && !unsigned_b); + + wire [NBITS_A+NBITS_B-1:0] mult = (unsigned_a && unsigned_b) ? + (mult_a * mult_b) : (mult_sgn ? (~mult_mag + 1) : mult_mag); + + // Sign extension + wire [NBITS_ACC-1:0] mult_xtnd = unsigned_mode ? + {{(NBITS_ACC-NBITS_A-NBITS_B){1'b0}}, mult[NBITS_A+NBITS_B-1:0]} : + {{(NBITS_ACC-NBITS_A-NBITS_B){mult[NBITS_A+NBITS_B-1]}}, mult[NBITS_A+NBITS_B-1:0]}; + + // Adder + wire [NBITS_ACC-1:0] acc_fir_int = unsigned_a ? {{(NBITS_ACC-NBITS_A){1'b0}}, a} : + {{(NBITS_ACC-NBITS_A){a[NBITS_A-1]}}, a} ; + + wire [NBITS_ACC-1:0] add_a = (subtract) ? (~mult_xtnd + 1) : mult_xtnd; + wire [NBITS_ACC-1:0] add_b = (feedback_i == 3'h0) ? acc : + (feedback_i == 3'h1) ? {{NBITS_ACC}{1'b0}} : (acc_fir_int << acc_fir); + + wire [NBITS_ACC-1:0] add_o = add_a + add_b; + + // Accumulator + initial acc <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) acc <= 'h0; + else begin + if (load_acc) + acc <= add_o; + else + acc <= acc; + end + + // Adder/accumulator output selection + wire [NBITS_ACC-1:0] acc_out = (output_select_i[1]) ? add_o : acc; + + // Round, shift, saturate + wire [NBITS_ACC-1:0] acc_rnd = (rnd && (shift_right_i != 0)) ? (acc_out + ({{(NBITS_ACC-1){1'b0}}, 1'b1} << (shift_right_i - 1))) : + acc_out; + + wire [NBITS_ACC-1:0] acc_shr = (unsigned_mode) ? (acc_rnd >> shift_right_i) : + (acc_rnd >>> shift_right_i); + + wire [NBITS_ACC-1:0] acc_sat_u = (acc_shr[NBITS_ACC-1:NBITS_Z] != 0) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{NBITS_Z{1'b1}}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}}; + + wire [NBITS_ACC-1:0] acc_sat_s = ((|acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b0) || + (&acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b1)) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_ACC-1],{NBITS_Z-1{~acc_shr[NBITS_ACC-1]}}}}; + + wire [NBITS_ACC-1:0] acc_sat = (sat) ? ((unsigned_mode) ? acc_sat_u : acc_sat_s) : acc_shr; + + // Output signals + wire [NBITS_Z-1:0] z0; + reg [NBITS_Z-1:0] z1; + wire [NBITS_Z-1:0] z2; + + assign z0 = mult_xtnd[NBITS_Z-1:0]; + assign z2 = acc_sat[NBITS_Z-1:0]; + + initial z1 <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + z1 <= 0; + else begin + z1 <= (output_select_i == 3'b100) ? z0 : z2; + end + + // Output mux + assign z_o = (output_select_i == 3'h0) ? z0 : + (output_select_i == 3'h1) ? z2 : + (output_select_i == 3'h2) ? z2 : + (output_select_i == 3'h3) ? z2 : + (output_select_i == 3'h4) ? z1 : + (output_select_i == 3'h5) ? z1 : + (output_select_i == 3'h6) ? z1 : + z1; // if output_select_i == 3'h7 + + // B input delayed passthrough + initial dly_b_o <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + dly_b_o <= 0; + else + dly_b_o <= b_i; + +endmodule + + + +// ---------------------------------------- // +// ----- DSP cells simulation modules ----- // +// ------ Control bits in parameters ------ // +// ---------------------------------------- // + +module QL_DSP3 ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + input wire [ 5:0] acc_fir, + output wire [37:0] z, + output wire [17:0] dly_b, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + localparam NBITS_ACC = 64; + localparam NBITS_A = 20; + localparam NBITS_B = 18; + localparam NBITS_Z = 38; + + // Fractured + generate if(F_MODE == 1'b1) begin + + wire [(NBITS_Z/2)-1:0] dsp_frac0_z; + wire [(NBITS_Z/2)-1:0] dsp_frac1_z; + + wire [(NBITS_B/2)-1:0] dsp_frac0_dly_b; + wire [(NBITS_B/2)-1:0] dsp_frac1_dly_b; + + dsp_t1_sim_cfg_params #( + .NBITS_A (NBITS_A/2), + .NBITS_B (NBITS_B/2), + .NBITS_ACC (NBITS_ACC/2), + .NBITS_Z (NBITS_Z/2), + .OUTPUT_SELECT (OUTPUT_SELECT), + .SATURATE_ENABLE (SATURATE_ENABLE), + .SHIFT_RIGHT (SHIFT_RIGHT), + .ROUND (ROUND), + .REGISTER_INPUTS (REGISTER_INPUTS) + ) dsp_frac0 ( + .a_i(a[(NBITS_A/2)-1:0]), + .b_i(b[(NBITS_B/2)-1:0]), + .z_o(dsp_frac0_z), + .dly_b_o(dsp_frac0_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .subtract_i(subtract), + .coef_0_i(COEFF_0[(NBITS_A/2)-1:0]), + .coef_1_i(COEFF_1[(NBITS_A/2)-1:0]), + .coef_2_i(COEFF_2[(NBITS_A/2)-1:0]), + .coef_3_i(COEFF_3[(NBITS_A/2)-1:0]) + ); + + dsp_t1_sim_cfg_params #( + .NBITS_A (NBITS_A/2), + .NBITS_B (NBITS_B/2), + .NBITS_ACC (NBITS_ACC/2), + .NBITS_Z (NBITS_Z/2), + .OUTPUT_SELECT (OUTPUT_SELECT), + .SATURATE_ENABLE (SATURATE_ENABLE), + .SHIFT_RIGHT (SHIFT_RIGHT), + .ROUND (ROUND), + .REGISTER_INPUTS (REGISTER_INPUTS) + ) dsp_frac1 ( + .a_i(a[NBITS_A-1:NBITS_A/2]), + .b_i(b[NBITS_B-1:NBITS_B/2]), + .z_o(dsp_frac1_z), + .dly_b_o(dsp_frac1_dly_b), + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .subtract_i(subtract), + .coef_0_i(COEFF_0[NBITS_A-1:NBITS_A/2]), + .coef_1_i(COEFF_1[NBITS_A-1:NBITS_A/2]), + .coef_2_i(COEFF_2[NBITS_A-1:NBITS_A/2]), + .coef_3_i(COEFF_3[NBITS_A-1:NBITS_A/2]) + ); + + assign z = {dsp_frac1_z, dsp_frac0_z}; + assign dly_b = {dsp_frac1_dly_b, dsp_frac0_dly_b}; + + // Whole + end else begin + + dsp_t1_sim_cfg_params #( + .NBITS_A (NBITS_A), + .NBITS_B (NBITS_B), + .NBITS_ACC (NBITS_ACC), + .NBITS_Z (NBITS_Z), + .OUTPUT_SELECT (OUTPUT_SELECT), + .SATURATE_ENABLE (SATURATE_ENABLE), + .SHIFT_RIGHT (SHIFT_RIGHT), + .ROUND (ROUND), + .REGISTER_INPUTS (REGISTER_INPUTS) + ) dsp_full ( + .a_i(a), + .b_i(b), + .z_o(z), + .dly_b_o(dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .subtract_i(subtract), + .coef_0_i(COEFF_0), + .coef_1_i(COEFF_1), + .coef_2_i(COEFF_2), + .coef_3_i(COEFF_3) + ); + + end endgenerate + +endmodule + +module QL_DSP3_MULT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // unregistered output: a * b (0) + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .reset(reset), + + .feedback(feedback), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b) + ); +endmodule + +module QL_DSP3_MULT_REGIN ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + + input wire unsigned_a, + input wire unsigned_b +); + + wire [37:0] dly_b_o; + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // unregistered output: a * b (0) + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // registered inputs + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset) + ); +endmodule + +module QL_DSP3_MULT_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + + input wire unsigned_a, + input wire unsigned_b +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // registered output: a * b (4) + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset) + ); +endmodule + +module QL_DSP3_MULT_REGIN_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + + input wire unsigned_a, + input wire unsigned_b +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // registered output: a * b (4) + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset) + ); +endmodule + +module QL_DSP3_MULTADD ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTADD_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTADD_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTADD_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTACC ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTACC_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTACC_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTACC_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module dsp_t1_20x18x64_cfg_params ( + input wire [19:0] a_i, + input wire [17:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [37:0] z_o, + output wire [17:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + input wire subtract_i +); + + parameter [19:0] COEFF_0 = 20'b0; + parameter [19:0] COEFF_1 = 20'b0; + parameter [19:0] COEFF_2 = 20'b0; + parameter [19:0] COEFF_3 = 20'b0; + + parameter [2:0] OUTPUT_SELECT = 3'b0; + parameter [0:0] SATURATE_ENABLE = 1'b0; + parameter [5:0] SHIFT_RIGHT = 6'b0; + parameter [0:0] ROUND = 1'b0; + parameter [0:0] REGISTER_INPUTS = 1'b0; + + QL_DSP3 #( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b0, // Not fractured + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a_i), + .b(b_i), + .z(z_o), + .dly_b(dly_b_o), + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + .subtract(subtract_i) + ); +endmodule + +module dsp_t1_10x9x32_cfg_params ( + input wire [ 9:0] a_i, + input wire [ 8:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [18:0] z_o, + output wire [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + input wire subtract_i +); + + parameter [9:0] COEFF_0 = 10'b0; + parameter [9:0] COEFF_1 = 10'b0; + parameter [9:0] COEFF_2 = 10'b0; + parameter [9:0] COEFF_3 = 10'b0; + + parameter [2:0] OUTPUT_SELECT = 3'b0; + parameter [0:0] SATURATE_ENABLE = 1'b0; + parameter [5:0] SHIFT_RIGHT = 6'b0; + parameter [0:0] ROUND = 1'b0; + parameter [0:0] REGISTER_INPUTS = 1'b0; + + wire [18:0] z_rem; + wire [8:0] dly_b_rem; + + QL_DSP3 #( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b1, // Fractured + 10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0 + }) + ) dsp ( + .a({10'b0, a_i}), + .b({9'b0, b_i}), + .z({z_rem, z_o}), + .dly_b({dly_b_rem, dly_b_o}), + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + .subtract(subtract_i) + ); +endmodule + +module dsp_t1_sim_cfg_params # ( + parameter NBITS_ACC = 64, + parameter NBITS_A = 20, + parameter NBITS_B = 18, + parameter NBITS_Z = 38, + + parameter [2:0] OUTPUT_SELECT = 3'b0, + parameter [0:0] SATURATE_ENABLE = 1'b0, + parameter [5:0] SHIFT_RIGHT = 6'b0, + parameter [0:0] ROUND = 1'b0, + parameter [0:0] REGISTER_INPUTS = 1'b0 +)( + input wire [NBITS_A-1:0] a_i, + input wire [NBITS_B-1:0] b_i, + output wire [NBITS_Z-1:0] z_o, + output reg [NBITS_B-1:0] dly_b_o, + + input wire [5:0] acc_fir_i, + input wire [2:0] feedback_i, + input wire load_acc_i, + + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire clock_i, + input wire s_reset, + + input wire subtract_i, + input wire [NBITS_A-1:0] coef_0_i, + input wire [NBITS_A-1:0] coef_1_i, + input wire [NBITS_A-1:0] coef_2_i, + input wire [NBITS_A-1:0] coef_3_i +); + +// FIXME: The version of Icarus Verilog from Conda seems not to recognize the +// $error macro. Disable this sanity check for now because of that. + + // Input registers + reg [NBITS_A-1:0] r_a; + reg [NBITS_B-1:0] r_b; + reg [5:0] r_acc_fir; + reg r_unsigned_a; + reg r_unsigned_b; + reg r_load_acc; + reg [2:0] r_feedback; + reg [5:0] r_shift_d1; + reg [5:0] r_shift_d2; + reg r_subtract; + reg r_sat; + reg r_rnd; + reg [NBITS_ACC-1:0] acc; + + initial begin + r_a <= 0; + r_b <= 0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + end + + always @(posedge clock_i or posedge s_reset) begin + if (s_reset) begin + + r_a <= 'h0; + r_b <= 'h0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + + end else begin + + r_a <= a_i; + r_b <= b_i; + + r_acc_fir <= acc_fir_i; + r_unsigned_a <= unsigned_a_i; + r_unsigned_b <= unsigned_b_i; + r_feedback <= feedback_i; + r_shift_d1 <= SHIFT_RIGHT; + r_shift_d2 <= r_shift_d1; + r_subtract <= subtract_i; + r_load_acc <= load_acc_i; + r_sat <= r_sat; + r_rnd <= r_rnd; + + end + end + + // Registered / non-registered input path select + wire [NBITS_A-1:0] a = REGISTER_INPUTS ? r_a : a_i; + wire [NBITS_B-1:0] b = REGISTER_INPUTS ? r_b : b_i; + + wire [5:0] acc_fir = REGISTER_INPUTS ? r_acc_fir : acc_fir_i; + wire unsigned_a = REGISTER_INPUTS ? r_unsigned_a : unsigned_a_i; + wire unsigned_b = REGISTER_INPUTS ? r_unsigned_b : unsigned_b_i; + wire [2:0] feedback = REGISTER_INPUTS ? r_feedback : feedback_i; + wire load_acc = REGISTER_INPUTS ? r_load_acc : load_acc_i; + wire subtract = REGISTER_INPUTS ? r_subtract : subtract_i; + wire sat = REGISTER_INPUTS ? r_sat : SATURATE_ENABLE; + wire rnd = REGISTER_INPUTS ? r_rnd : ROUND; + + // Shift right control + wire [5:0] shift_d1 = REGISTER_INPUTS ? r_shift_d1 : SHIFT_RIGHT; + wire [5:0] shift_d2 = OUTPUT_SELECT[1] ? shift_d1 : r_shift_d2; + + // Multiplier + wire unsigned_mode = unsigned_a & unsigned_b; + wire [NBITS_A-1:0] mult_a; + assign mult_a = (feedback == 3'h0) ? a : + (feedback == 3'h1) ? a : + (feedback == 3'h2) ? a : + (feedback == 3'h3) ? acc[NBITS_A-1:0] : + (feedback == 3'h4) ? coef_0_i : + (feedback == 3'h5) ? coef_1_i : + (feedback == 3'h6) ? coef_2_i : + coef_3_i; // if feedback == 3'h7 + + wire [NBITS_B-1:0] mult_b = (feedback == 2'h2) ? {NBITS_B{1'b0}} : b; + + wire [NBITS_A-1:0] mult_sgn_a = mult_a[NBITS_A-1]; + wire [NBITS_A-1:0] mult_mag_a = (mult_sgn_a && !unsigned_a) ? (~mult_a + 1) : mult_a; + wire [NBITS_B-1:0] mult_sgn_b = mult_b[NBITS_B-1]; + wire [NBITS_B-1:0] mult_mag_b = (mult_sgn_b && !unsigned_b) ? (~mult_b + 1) : mult_b; + + wire [NBITS_A+NBITS_B-1:0] mult_mag = mult_mag_a * mult_mag_b; + wire mult_sgn = (mult_sgn_a && !unsigned_a) ^ (mult_sgn_b && !unsigned_b); + + wire [NBITS_A+NBITS_B-1:0] mult = (unsigned_a && unsigned_b) ? + (mult_a * mult_b) : (mult_sgn ? (~mult_mag + 1) : mult_mag); + + // Sign extension + wire [NBITS_ACC-1:0] mult_xtnd = unsigned_mode ? + {{(NBITS_ACC-NBITS_A-NBITS_B){1'b0}}, mult[NBITS_A+NBITS_B-1:0]} : + {{(NBITS_ACC-NBITS_A-NBITS_B){mult[NBITS_A+NBITS_B-1]}}, mult[NBITS_A+NBITS_B-1:0]}; + + // Adder + wire [NBITS_ACC-1:0] acc_fir_int = unsigned_a ? {{(NBITS_ACC-NBITS_A){1'b0}}, a} : + {{(NBITS_ACC-NBITS_A){a[NBITS_A-1]}}, a} ; + + wire [NBITS_ACC-1:0] add_a = (subtract) ? (~mult_xtnd + 1) : mult_xtnd; + wire [NBITS_ACC-1:0] add_b = (feedback_i == 3'h0) ? acc : + (feedback_i == 3'h1) ? {{NBITS_ACC}{1'b0}} : (acc_fir_int << acc_fir); + + wire [NBITS_ACC-1:0] add_o = add_a + add_b; + + // Accumulator + initial acc <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) acc <= 'h0; + else begin + if (load_acc) + acc <= add_o; + else + acc <= acc; + end + + // Adder/accumulator output selection + wire [NBITS_ACC-1:0] acc_out = (OUTPUT_SELECT[1]) ? add_o : acc; + + // Round, shift, saturate + wire [NBITS_ACC-1:0] acc_rnd = (rnd && (SHIFT_RIGHT != 0)) ? (acc_out + ({{(NBITS_ACC-1){1'b0}}, 1'b1} << (SHIFT_RIGHT - 1))) : + acc_out; + + wire [NBITS_ACC-1:0] acc_shr = (unsigned_mode) ? (acc_rnd >> SHIFT_RIGHT) : + (acc_rnd >>> SHIFT_RIGHT); + + wire [NBITS_ACC-1:0] acc_sat_u = (acc_shr[NBITS_ACC-1:NBITS_Z] != 0) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{NBITS_Z{1'b1}}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}}; + + wire [NBITS_ACC-1:0] acc_sat_s = ((|acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b0) || + (&acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b1)) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_ACC-1],{NBITS_Z-1{~acc_shr[NBITS_ACC-1]}}}}; + + wire [NBITS_ACC-1:0] acc_sat = (sat) ? ((unsigned_mode) ? acc_sat_u : acc_sat_s) : acc_shr; + + // Output signals + wire [NBITS_Z-1:0] z0; + reg [NBITS_Z-1:0] z1; + wire [NBITS_Z-1:0] z2; + + assign z0 = mult_xtnd[NBITS_Z-1:0]; + assign z2 = acc_sat[NBITS_Z-1:0]; + + initial z1 <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + z1 <= 0; + else begin + z1 <= (OUTPUT_SELECT == 3'b100) ? z0 : z2; + end + + // Output mux + assign z_o = (OUTPUT_SELECT == 3'h0) ? z0 : + (OUTPUT_SELECT == 3'h1) ? z2 : + (OUTPUT_SELECT == 3'h2) ? z2 : + (OUTPUT_SELECT == 3'h3) ? z2 : + (OUTPUT_SELECT == 3'h4) ? z1 : + (OUTPUT_SELECT == 3'h5) ? z1 : + (OUTPUT_SELECT == 3'h6) ? z1 : + z1; // if OUTPUT_SELECT == 3'h7 + + // B input delayed passthrough + initial dly_b_o <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + dly_b_o <= 0; + else + dly_b_o <= b_i; + +endmodule diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index d2df6bcff15..9692091909d 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -46,6 +46,15 @@ struct SynthQuickLogicPass : public ScriptPass { log(" - pp3: PolarPro 3 \n"); log(" - qlf_k6n10f: K6N10f\n"); log("\n"); + log(" -nodsp\n"); + log(" do not use dsp_t1_* to implement multipliers and associated logic\n"); + log(" (qlf_k6n10f only).\n"); + log("\n"); + log(" -use_dsp_cfg_params\n"); + log(" By default use DSP blocks with configuration bits available at module\n"); + log(" ports. Specifying this forces usage of DSP block with configuration\n"); + log(" bits available as module parameters.\n"); + log("\n"); log(" -nocarry\n"); log(" do not use adder_carry cells in output netlist.\n"); log("\n"); @@ -74,7 +83,7 @@ struct SynthQuickLogicPass : public ScriptPass { } string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path; - bool abc9, inferAdder, nobram, bramTypes; + bool abc9, inferAdder, nobram, bramTypes, dsp; void clear_flags() override { @@ -89,6 +98,7 @@ struct SynthQuickLogicPass : public ScriptPass { nobram = false; bramTypes = false; lib_path = "+/quicklogic/"; + dsp = true; } void set_scratchpad_defaults(RTLIL::Design *design) { @@ -149,6 +159,14 @@ struct SynthQuickLogicPass : public ScriptPass { bramTypes = true; continue; } + if (args[argidx] == "-nodsp" || args[argidx] == "-no_dsp") { + dsp = false; + continue; + } + if (args[argidx] == "-use_dsp_cfg_params") { + use_dsp_cfg_params = " -use_dsp_cfg_params"; + continue; + } break; } extra_args(args, argidx, design); @@ -184,6 +202,8 @@ struct SynthQuickLogicPass : public ScriptPass { read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path.c_str()); if (bramTypes) read_simlibs += stringf(" %sqlf_k6n10f/bram_types_sim.v", lib_path.c_str()); + if (dsp) + read_simlibs += stringf(" %sqlf_k6n10f/dsp_sim.v", lib_path.c_str()); } run(read_simlibs); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); @@ -208,6 +228,24 @@ struct SynthQuickLogicPass : public ScriptPass { run("share"); } + if (check_label("map_dsp", "(for qlf_k6n10f, skip if -nodsp)") + && ((dsp && family == "qlf_k6n10f") || help_mode)) { + run("wreduce t:$mul"); + run("ql_dsp_macc" + use_dsp_cfg_params); + + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9"); + run("chtype -set $mul t:$__soft_mul"); + + if (use_dsp_cfg_params.empty()) + run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0"); + else + run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1"); + run("ql_dsp_simd"); + run("techmap -map " + lib_path + family + "/dsp_final_map.v"); + run("ql_dsp_io_regs"); + } + if (check_label("coarse")) { run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); run("opt_expr"); @@ -219,15 +257,16 @@ struct SynthQuickLogicPass : public ScriptPass { run("opt_clean"); } - if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)") && (help_mode || family == "qlf_k6n10f")) { + if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)")) { + if(family == "qlf_k6n10f" || help_mode) run("memory_libmap -lib " + lib_path + family + "/libmap_brams.txt"); run("ql_bram_merge"); run("techmap -map " + lib_path + family + "/libmap_brams_map.v"); run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); run("techmap -map " + lib_path + family + "/brams_final_map.v"); - if (help_mode || bramTypes) { - run("ql_bram_types"); + if (bramTypes || help_mode) { + run("ql_bram_types", "(if -bramtypes)"); } } From b80b1ab8b6d80caa98c5af88e494d931072a4129 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 18 Sep 2023 12:45:06 +0200 Subject: [PATCH 171/240] merge brams_final_map.v into brams_map.v --- techlibs/quicklogic/Makefile.inc | 1 - .../quicklogic/qlf_k6n10f/brams_final_map.v | 1464 ----------------- techlibs/quicklogic/qlf_k6n10f/brams_map.v | 1449 ++++++++++++++++ techlibs/quicklogic/synth_quicklogic.cc | 1 - 4 files changed, 1449 insertions(+), 1466 deletions(-) delete mode 100644 techlibs/quicklogic/qlf_k6n10f/brams_final_map.v diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index ce5ff859b2e..852a8a77a88 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -31,7 +31,6 @@ $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_map.v)) -$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_final_map.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v)) diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v deleted file mode 100644 index 43f5dc95e94..00000000000 --- a/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v +++ /dev/null @@ -1,1464 +0,0 @@ -// Copyright 2020-2022 F4PGA Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 - -module BRAM2x18_SP ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o -); - -parameter WR1_ADDR_WIDTH = 10; -parameter RD1_ADDR_WIDTH = 10; -parameter WR1_DATA_WIDTH = 18; -parameter RD1_DATA_WIDTH = 18; -parameter BE1_WIDTH = 2; - -parameter WR2_ADDR_WIDTH = 10; -parameter RD2_ADDR_WIDTH = 10; -parameter WR2_DATA_WIDTH = 18; -parameter RD2_DATA_WIDTH = 18; -parameter BE2_WIDTH = 2; - -input wire RESET_ni; - -input wire WEN1_i; -input wire REN1_i; -input wire WR1_CLK_i; -input wire RD1_CLK_i; -input wire [BE1_WIDTH-1:0] WR1_BE_i; -input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; -input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; -input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; -output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; - -input wire WEN2_i; -input wire REN2_i; -input wire WR2_CLK_i; -input wire RD2_CLK_i; -input wire [BE2_WIDTH-1:0] WR2_BE_i; -input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; -input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; -input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; -output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; - -// Fixed mode settings -localparam [ 0:0] SYNC_FIFO1_i = 1'd0; -localparam [ 0:0] FMODE1_i = 1'd0; -localparam [ 0:0] POWERDN1_i = 1'd0; -localparam [ 0:0] SLEEP1_i = 1'd0; -localparam [ 0:0] PROTECT1_i = 1'd0; -localparam [11:0] UPAE1_i = 12'd10; -localparam [11:0] UPAF1_i = 12'd10; - -localparam [ 0:0] SYNC_FIFO2_i = 1'd0; -localparam [ 0:0] FMODE2_i = 1'd0; -localparam [ 0:0] POWERDN2_i = 1'd0; -localparam [ 0:0] SLEEP2_i = 1'd0; -localparam [ 0:0] PROTECT2_i = 1'd0; -localparam [10:0] UPAE2_i = 11'd10; -localparam [10:0] UPAF2_i = 11'd10; - -// Width mode function -function [2:0] mode; -input integer width; -case (width) -1: mode = 3'b101; -2: mode = 3'b110; -4: mode = 3'b100; -8,9: mode = 3'b001; -16, 18: mode = 3'b010; -32, 36: mode = 3'b011; -default: mode = 3'b000; -endcase -endfunction - -function integer rwmode; -input integer rwwidth; -case (rwwidth) -1: rwmode = 1; -2: rwmode = 2; -4: rwmode = 4; -8,9: rwmode = 9; -16, 18: rwmode = 18; -default: rwmode = 18; -endcase -endfunction - -wire REN_A1_i; -wire REN_A2_i; - -wire REN_B1_i; -wire REN_B2_i; - -wire WEN_A1_i; -wire WEN_A2_i; - -wire WEN_B1_i; -wire WEN_B2_i; - -wire [1:0] BE_A1_i; -wire [1:0] BE_A2_i; - -wire [1:0] BE_B1_i; -wire [1:0] BE_B2_i; - -wire [14:0] ADDR_A1_i; -wire [13:0] ADDR_A2_i; - -wire [14:0] ADDR_B1_i; -wire [13:0] ADDR_B2_i; - -wire [17:0] WDATA_A1_i; -wire [17:0] WDATA_A2_i; - -wire [17:0] WDATA_B1_i; -wire [17:0] WDATA_B2_i; - -wire [17:0] RDATA_A1_o; -wire [17:0] RDATA_A2_o; - -wire [17:0] RDATA_B1_o; -wire [17:0] RDATA_B2_o; - -wire [1:0] WR1_BE; -wire [1:0] WR2_BE; - -wire [17:0] PORT_B1_RDATA; -wire [17:0] PORT_A1_WDATA; - -wire [17:0] PORT_B2_RDATA; -wire [17:0] PORT_A2_WDATA; - -wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; - -wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; - -wire [13:0] PORT_A1_ADDR; -wire [13:0] PORT_B1_ADDR; - -wire [13:0] PORT_A2_ADDR; -wire [13:0] PORT_B2_ADDR; - - -// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) -localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); -localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); -localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); -localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - -localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); -localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); -localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); -localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - -localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); -localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); -localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); -localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - -generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end -endgenerate - -case (WR1_DATA_WIDTH) - 1: begin - assign PORT_A1_ADDR = WR1_ADDR_INT; - end - 2: begin - assign PORT_A1_ADDR = WR1_ADDR_INT << 1; - end - 4: begin - assign PORT_A1_ADDR = WR1_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_A1_ADDR = WR1_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_A1_ADDR = WR1_ADDR_INT << 4; - end - default: begin - assign PORT_A1_ADDR = WR1_ADDR_INT; - end -endcase - -generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end -endgenerate - -case (RD1_DATA_WIDTH) - 1: begin - assign PORT_B1_ADDR = RD1_ADDR_INT; - end - 2: begin - assign PORT_B1_ADDR = RD1_ADDR_INT << 1; - end - 4: begin - assign PORT_B1_ADDR = RD1_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_B1_ADDR = RD1_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_B1_ADDR = RD1_ADDR_INT << 4; - end - default: begin - assign PORT_B1_ADDR = RD1_ADDR_INT; - end -endcase - -generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end -endgenerate - -case (WR2_DATA_WIDTH) - 1: begin - assign PORT_A2_ADDR = WR2_ADDR_INT; - end - 2: begin - assign PORT_A2_ADDR = WR2_ADDR_INT << 1; - end - 4: begin - assign PORT_A2_ADDR = WR2_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_A2_ADDR = WR2_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_A2_ADDR = WR2_ADDR_INT << 4; - end - default: begin - assign PORT_A2_ADDR = WR2_ADDR_INT; - end -endcase - -generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end -endgenerate - -case (RD2_DATA_WIDTH) - 1: begin - assign PORT_B2_ADDR = RD2_ADDR_INT; - end - 2: begin - assign PORT_B2_ADDR = RD2_ADDR_INT << 1; - end - 4: begin - assign PORT_B2_ADDR = RD2_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_B2_ADDR = RD2_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_B2_ADDR = RD2_ADDR_INT << 4; - end - default: begin - assign PORT_B2_ADDR = RD2_ADDR_INT; - end -endcase - -case (BE1_WIDTH) - 2: begin - assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; - end - default: begin - assign WR1_BE[1:BE1_WIDTH] = 0; - assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; - end -endcase - -case (BE2_WIDTH) - 2: begin - assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; - end - default: begin - assign WR2_BE[1:BE2_WIDTH] = 0; - assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; - end -endcase - -assign REN_A1_i = 1'b0; -assign WEN_A1_i = WEN1_i; -assign BE_A1_i = WR1_BE; -assign REN_A2_i = 1'b0; -assign WEN_A2_i = WEN2_i; -assign BE_A2_i = WR2_BE; - -assign REN_B1_i = REN1_i; -assign WEN_B1_i = 1'b0; -assign BE_B1_i = 4'h0; -assign REN_B2_i = REN2_i; -assign WEN_B2_i = 1'b0; -assign BE_B2_i = 4'h0; - -generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end -endgenerate - -assign WDATA_A1_i = PORT_A1_WDATA[17:0]; -assign WDATA_B1_i = 18'h0; - -generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end -endgenerate - -assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; - -generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end -endgenerate - -assign WDATA_A2_i = PORT_A2_WDATA[17:0]; -assign WDATA_B2_i = 18'h0; - -generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end -endgenerate - -assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; - -defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, - UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, - UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i -}; - -(* is_inferred = 0 *) -(* is_split = 0 *) -(* is_fifo = 0 *) -(* port_a_dwidth = PORT_A1_WRWIDTH *) -(* port_b_dwidth = PORT_B1_WRWIDTH *) -TDP36K _TECHMAP_REPLACE_ ( - .RESET_ni(1'b1), - - .CLK_A1_i(WR1_CLK_i), - .ADDR_A1_i({1'b0,PORT_A1_ADDR}), - .WEN_A1_i(WEN_A1_i), - .BE_A1_i(BE_A1_i), - .WDATA_A1_i(WDATA_A1_i), - .REN_A1_i(REN_A1_i), - .RDATA_A1_o(RDATA_A1_o), - - .CLK_A2_i(WR2_CLK_i), - .ADDR_A2_i(PORT_A2_ADDR), - .WEN_A2_i(WEN_A2_i), - .BE_A2_i(BE_A2_i), - .WDATA_A2_i(WDATA_A2_i), - .REN_A2_i(REN_A2_i), - .RDATA_A2_o(RDATA_A2_o), - - .CLK_B1_i(RD1_CLK_i), - .ADDR_B1_i({1'b0,PORT_B1_ADDR}), - .WEN_B1_i(WEN_B1_i), - .BE_B1_i(BE_B1_i), - .WDATA_B1_i(WDATA_B1_i), - .REN_B1_i(REN_B1_i), - .RDATA_B1_o(RDATA_B1_o), - - .CLK_B2_i(RD2_CLK_i), - .ADDR_B2_i(PORT_B2_ADDR), - .WEN_B2_i(WEN_B2_i), - .BE_B2_i(BE_B2_i), - .WDATA_B2_i(WDATA_B2_i), - .REN_B2_i(REN_B2_i), - .RDATA_B2_o(RDATA_B2_o), - - .FLUSH1_i(1'b0), - .FLUSH2_i(1'b0) -); - -endmodule - -module BRAM2x18_dP ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o -); - -parameter PORT_A1_AWIDTH = 10; -parameter PORT_A1_DWIDTH = 18; -parameter PORT_A1_WR_BE_WIDTH = 2; - -parameter PORT_B1_AWIDTH = 10; -parameter PORT_B1_DWIDTH = 18; -parameter PORT_B1_WR_BE_WIDTH = 2; - -parameter PORT_A2_AWIDTH = 10; -parameter PORT_A2_DWIDTH = 18; -parameter PORT_A2_WR_BE_WIDTH = 2; - -parameter PORT_B2_AWIDTH = 10; -parameter PORT_B2_DWIDTH = 18; -parameter PORT_B2_WR_BE_WIDTH = 2; - -input PORT_A1_CLK_i; -input [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; -input [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; -input PORT_A1_WEN_i; -input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; -input PORT_A1_REN_i; -output [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; - -input PORT_B1_CLK_i; -input [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; -input [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; -input PORT_B1_WEN_i; -input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; -input PORT_B1_REN_i; -output [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; - -input PORT_A2_CLK_i; -input [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; -input [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; -input PORT_A2_WEN_i; -input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; -input PORT_A2_REN_i; -output [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; - -input PORT_B2_CLK_i; -input [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; -input [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; -input PORT_B2_WEN_i; -input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; -input PORT_B2_REN_i; -output [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; - - -// Fixed mode settings -localparam [ 0:0] SYNC_FIFO1_i = 1'd0; -localparam [ 0:0] FMODE1_i = 1'd0; -localparam [ 0:0] POWERDN1_i = 1'd0; -localparam [ 0:0] SLEEP1_i = 1'd0; -localparam [ 0:0] PROTECT1_i = 1'd0; -localparam [11:0] UPAE1_i = 12'd10; -localparam [11:0] UPAF1_i = 12'd10; - -localparam [ 0:0] SYNC_FIFO2_i = 1'd0; -localparam [ 0:0] FMODE2_i = 1'd0; -localparam [ 0:0] POWERDN2_i = 1'd0; -localparam [ 0:0] SLEEP2_i = 1'd0; -localparam [ 0:0] PROTECT2_i = 1'd0; -localparam [10:0] UPAE2_i = 11'd10; -localparam [10:0] UPAF2_i = 11'd10; - -// Width mode function -function [2:0] mode; -input integer width; -case (width) -1: mode = 3'b101; -2: mode = 3'b110; -4: mode = 3'b100; -8,9: mode = 3'b001; -16, 18: mode = 3'b010; -32, 36: mode = 3'b011; -default: mode = 3'b000; -endcase -endfunction - -function integer rwmode; -input integer rwwidth; -case (rwwidth) -1: rwmode = 1; -2: rwmode = 2; -4: rwmode = 4; -8,9: rwmode = 9; -16, 18: rwmode = 18; -default: rwmode = 18; -endcase -endfunction - -wire REN_A1_i; -wire REN_A2_i; - -wire REN_B1_i; -wire REN_B2_i; - -wire WEN_A1_i; -wire WEN_A2_i; - -wire WEN_B1_i; -wire WEN_B2_i; - -wire [1:0] BE_A1_i; -wire [1:0] BE_A2_i; - -wire [1:0] BE_B1_i; -wire [1:0] BE_B2_i; - -wire [14:0] ADDR_A1_i; -wire [13:0] ADDR_A2_i; - -wire [14:0] ADDR_B1_i; -wire [13:0] ADDR_B2_i; - -wire [17:0] WDATA_A1_i; -wire [17:0] WDATA_A2_i; - -wire [17:0] WDATA_B1_i; -wire [17:0] WDATA_B2_i; - -wire [17:0] RDATA_A1_o; -wire [17:0] RDATA_A2_o; - -wire [17:0] RDATA_B1_o; -wire [17:0] RDATA_B2_o; - -wire [1:0] PORT_A1_WR_BE; -wire [1:0] PORT_B1_WR_BE; - -wire [1:0] PORT_A2_WR_BE; -wire [1:0] PORT_B2_WR_BE; - -wire [17:0] PORT_B1_WDATA; -wire [17:0] PORT_B1_RDATA; -wire [17:0] PORT_A1_WDATA; -wire [17:0] PORT_A1_RDATA; - -wire [17:0] PORT_B2_WDATA; -wire [17:0] PORT_B2_RDATA; -wire [17:0] PORT_A2_WDATA; -wire [17:0] PORT_A2_RDATA; - -wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; - -wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - -wire [13:0] PORT_A1_ADDR; -wire [13:0] PORT_B1_ADDR; - -wire [13:0] PORT_A2_ADDR; -wire [13:0] PORT_B2_ADDR; - -wire PORT_A1_CLK; -wire PORT_B1_CLK; - -wire PORT_A2_CLK; -wire PORT_B2_CLK; - -// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) -localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); -localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); -localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); -localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); - -localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); -localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); -localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); -localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); - -localparam PORT_A1_WRWIDTH = rwmode(PORT_A1_DWIDTH); -localparam PORT_B1_WRWIDTH = rwmode(PORT_B1_DWIDTH); -localparam PORT_A2_WRWIDTH = rwmode(PORT_A2_DWIDTH); -localparam PORT_B2_WRWIDTH = rwmode(PORT_B2_DWIDTH); - -assign PORT_A1_CLK = PORT_A1_CLK_i; -assign PORT_B1_CLK = PORT_B1_CLK_i; - -assign PORT_A2_CLK = PORT_A2_CLK_i; -assign PORT_B2_CLK = PORT_B2_CLK_i; - -generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end -endgenerate - -case (PORT_A1_DWIDTH) - 1: begin - assign PORT_A1_ADDR = PORT_A1_ADDR_INT; - end - 2: begin - assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; - end - 4: begin - assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; - end - default: begin - assign PORT_A1_ADDR = PORT_A1_ADDR_INT; - end -endcase - -generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end -endgenerate - -case (PORT_B1_DWIDTH) - 1: begin - assign PORT_B1_ADDR = PORT_B1_ADDR_INT; - end - 2: begin - assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; - end - 4: begin - assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; - end - default: begin - assign PORT_B1_ADDR = PORT_B1_ADDR_INT; - end -endcase - -generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end -endgenerate - -case (PORT_A2_DWIDTH) - 1: begin - assign PORT_A2_ADDR = PORT_A2_ADDR_INT; - end - 2: begin - assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; - end - 4: begin - assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; - end - default: begin - assign PORT_A2_ADDR = PORT_A2_ADDR_INT; - end -endcase - -generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end -endgenerate - -case (PORT_B2_DWIDTH) - 1: begin - assign PORT_B2_ADDR = PORT_B2_ADDR_INT; - end - 2: begin - assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; - end - 4: begin - assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; - end - default: begin - assign PORT_B2_ADDR = PORT_B2_ADDR_INT; - end -endcase - -case (PORT_A1_WR_BE_WIDTH) - 2: begin - assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; - end - default: begin - assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; - assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; - end -endcase - -case (PORT_B1_WR_BE_WIDTH) - 2: begin - assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; - end - default: begin - assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; - assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; - end -endcase - -case (PORT_A2_WR_BE_WIDTH) - 2: begin - assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; - end - default: begin - assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; - assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; - end -endcase - -case (PORT_B2_WR_BE_WIDTH) - 2: begin - assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; - end - default: begin - assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; - assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; - end -endcase - -assign REN_A1_i = PORT_A1_REN_i; -assign WEN_A1_i = PORT_A1_WEN_i; -assign BE_A1_i = PORT_A1_WR_BE; - -assign REN_A2_i = PORT_A2_REN_i; -assign WEN_A2_i = PORT_A2_WEN_i; -assign BE_A2_i = PORT_A2_WR_BE; - -assign REN_B1_i = PORT_B1_REN_i; -assign WEN_B1_i = PORT_B1_WEN_i; -assign BE_B1_i = PORT_B1_WR_BE; - -assign REN_B2_i = PORT_B2_REN_i; -assign WEN_B2_i = PORT_B2_WEN_i; -assign BE_B2_i = PORT_B2_WR_BE; - -generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end -endgenerate - -assign WDATA_A1_i = PORT_A1_WDATA; - -generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end -endgenerate - -assign WDATA_A2_i = PORT_A2_WDATA; - -generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end -endgenerate - -assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; - -generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end -endgenerate - -assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; - -generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end -endgenerate - -assign WDATA_B1_i = PORT_B1_WDATA; - -generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end -endgenerate - -assign WDATA_B2_i = PORT_B2_WDATA; - -generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end -endgenerate - -assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; - -generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end -endgenerate - -assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; - -defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, - UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, - UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i -}; - -(* is_inferred = 0 *) -(* is_split = 0 *) -(* is_fifo = 0 *) -(* port_a_dwidth = PORT_A1_WRWIDTH *) -(* port_b_dwidth = PORT_B1_WRWIDTH *) -TDP36K _TECHMAP_REPLACE_ ( - .RESET_ni(1'b1), - - .CLK_A1_i(PORT_A1_CLK), - .ADDR_A1_i({1'b0,PORT_A1_ADDR}), - .WEN_A1_i(WEN_A1_i), - .BE_A1_i(BE_A1_i), - .WDATA_A1_i(WDATA_A1_i), - .REN_A1_i(REN_A1_i), - .RDATA_A1_o(RDATA_A1_o), - - .CLK_A2_i(PORT_A2_CLK), - .ADDR_A2_i(PORT_A2_ADDR), - .WEN_A2_i(WEN_A2_i), - .BE_A2_i(BE_A2_i), - .WDATA_A2_i(WDATA_A2_i), - .REN_A2_i(REN_A2_i), - .RDATA_A2_o(RDATA_A2_o), - - .CLK_B1_i(PORT_B1_CLK), - .ADDR_B1_i({1'b0,PORT_B1_ADDR}), - .WEN_B1_i(WEN_B1_i), - .BE_B1_i(BE_B1_i), - .WDATA_B1_i(WDATA_B1_i), - .REN_B1_i(REN_B1_i), - .RDATA_B1_o(RDATA_B1_o), - - .CLK_B2_i(PORT_B2_CLK), - .ADDR_B2_i(PORT_B2_ADDR), - .WEN_B2_i(WEN_B2_i), - .BE_B2_i(BE_B2_i), - .WDATA_B2_i(WDATA_B2_i), - .REN_B2_i(REN_B2_i), - .RDATA_B2_o(RDATA_B2_o), - - .FLUSH1_i(1'b0), - .FLUSH2_i(1'b0) -); - -endmodule - - -module BRAM2x18_SFIFO ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 -); - - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input CLK1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input CLK2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, - UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, - UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i - }; - - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = PORT_A1_WRWIDTH *) - (* port_b_dwidth = PORT_B1_WRWIDTH *) - TDP36K _TECHMAP_REPLACE_ ( - .RESET_ni(1'b1), - .WDATA_A1_i(in_reg1[17:0]), - .WDATA_A2_i(in_reg2[17:0]), - .RDATA_A1_o(fifo1_flags), - .RDATA_A2_o(fifo2_flags), - .ADDR_A1_i(14'h0), - .ADDR_A2_i(14'h0), - .CLK_A1_i(Push_Clk1), - .CLK_A2_i(Push_Clk2), - .REN_A1_i(1'b1), - .REN_A2_i(1'b1), - .WEN_A1_i(PUSH1), - .WEN_A2_i(PUSH2), - .BE_A1_i(2'b11), - .BE_A2_i(2'b11), - - .WDATA_B1_i(18'h0), - .WDATA_B2_i(18'h0), - .RDATA_B1_o(out_reg1[17:0]), - .RDATA_B2_o(out_reg2[17:0]), - .ADDR_B1_i(14'h0), - .ADDR_B2_i(14'h0), - .CLK_B1_i(Pop_Clk1), - .CLK_B2_i(Pop_Clk2), - .REN_B1_i(POP1), - .REN_B2_i(POP2), - .WEN_B1_i(1'b0), - .WEN_B2_i(1'b0), - .BE_B1_i(2'b11), - .BE_B2_i(2'b11), - - .FLUSH1_i(Async_Flush1), - .FLUSH2_i(Async_Flush2) - ); - -endmodule - - -module BRAM2x18_AFIFO ( - DIN1, - PUSH1, - POP1, - Push_Clk1, - Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, - Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 -); - - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input Push_Clk1, Pop_Clk1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input Push_Clk2, Pop_Clk2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, - UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, - UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i - }; - - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = PORT_A1_WRWIDTH *) - (* port_b_dwidth = PORT_B1_WRWIDTH *) - TDP36K _TECHMAP_REPLACE_ ( - .RESET_ni(1'b1), - .WDATA_A1_i(in_reg1[17:0]), - .WDATA_A2_i(in_reg2[17:0]), - .RDATA_A1_o(fifo1_flags), - .RDATA_A2_o(fifo2_flags), - .ADDR_A1_i(14'h0), - .ADDR_A2_i(14'h0), - .CLK_A1_i(Push_Clk1), - .CLK_A2_i(Push_Clk2), - .REN_A1_i(1'b1), - .REN_A2_i(1'b1), - .WEN_A1_i(PUSH1), - .WEN_A2_i(PUSH2), - .BE_A1_i(2'b11), - .BE_A2_i(2'b11), - - .WDATA_B1_i(18'h0), - .WDATA_B2_i(18'h0), - .RDATA_B1_o(out_reg1[17:0]), - .RDATA_B2_o(out_reg2[17:0]), - .ADDR_B1_i(14'h0), - .ADDR_B2_i(14'h0), - .CLK_B1_i(Pop_Clk1), - .CLK_B2_i(Pop_Clk2), - .REN_B1_i(POP1), - .REN_B2_i(POP2), - .WEN_B1_i(1'b0), - .WEN_B2_i(1'b0), - .BE_B1_i(2'b11), - .BE_B2_i(2'b11), - - .FLUSH1_i(Async_Flush1), - .FLUSH2_i(Async_Flush2) - ); - -endmodule \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_map.v index 82bbceeff52..ba6382a2395 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_map.v @@ -2836,4 +2836,1453 @@ module AFIFO_18K_X2_BLK ( .FLUSH2_i(Async_Flush2) ); +endmodule + +module BRAM2x18_SP ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); +localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); +localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); +localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 4'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 4'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A1_WRWIDTH *) +(* port_b_dwidth = PORT_B1_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + +input PORT_A1_CLK_i; +input [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input PORT_A1_WEN_i; +input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input PORT_A1_REN_i; +output [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input PORT_B1_CLK_i; +input [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input PORT_B1_WEN_i; +input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input PORT_B1_REN_i; +output [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input PORT_A2_CLK_i; +input [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input PORT_A2_WEN_i; +input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input PORT_A2_REN_i; +output [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input PORT_B2_CLK_i; +input [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input PORT_B2_WEN_i; +input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input PORT_B2_REN_i; +output [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(PORT_A1_DWIDTH); +localparam PORT_B1_WRWIDTH = rwmode(PORT_B1_DWIDTH); +localparam PORT_A2_WRWIDTH = rwmode(PORT_A2_DWIDTH); +localparam PORT_B2_WRWIDTH = rwmode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A1_WRWIDTH *) +(* port_b_dwidth = PORT_B1_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + + +module BRAM2x18_SFIFO ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + + +module BRAM2x18_AFIFO ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + endmodule \ No newline at end of file diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 9692091909d..0a85749482e 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -263,7 +263,6 @@ struct SynthQuickLogicPass : public ScriptPass { run("ql_bram_merge"); run("techmap -map " + lib_path + family + "/libmap_brams_map.v"); run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); - run("techmap -map " + lib_path + family + "/brams_final_map.v"); if (bramTypes || help_mode) { run("ql_bram_types", "(if -bramtypes)"); From 4bb4fd358ebd3d0be60ca79d847b9927e98a4da3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 29 Sep 2023 14:31:06 +0200 Subject: [PATCH 172/240] ql_k6n10f: Remove support for parameter-configured DSP variety --- techlibs/quicklogic/ql_dsp_macc.cc | 40 +- techlibs/quicklogic/qlf_k6n10f/dsp_map.v | 123 +-- techlibs/quicklogic/qlf_k6n10f/dsp_sim.v | 1226 ---------------------- techlibs/quicklogic/synth_quicklogic.cc | 18 +- 4 files changed, 49 insertions(+), 1358 deletions(-) diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc index ca898d9d0c2..602fbf3cc1a 100644 --- a/techlibs/quicklogic/ql_dsp_macc.cc +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -27,8 +27,6 @@ PRIVATE_NAMESPACE_BEGIN // ============================================================================ -bool use_dsp_cfg_params; - static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) { auto &st = pm.st_ql_dsp_macc; @@ -122,11 +120,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) return; } - if (use_dsp_cfg_params) - cell_cfg_name = "_cfg_params"; - else - cell_cfg_name = "_cfg_ports"; - + cell_cfg_name = "_cfg_ports"; // TODO: remove cell_full_name = cell_base_name + cell_size_name + cell_cfg_name; type = RTLIL::escape_id(cell_full_name); @@ -237,21 +231,12 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) cell->setPort(RTLIL::escape_id("unsigned_b_i"), RTLIL::SigSpec(b_signed ? RTLIL::S0 : RTLIL::S1)); // Connect config bits - if (use_dsp_cfg_params) { - cell->setParam(RTLIL::escape_id("SATURATE_ENABLE"), RTLIL::Const(RTLIL::S0)); - cell->setParam(RTLIL::escape_id("SHIFT_RIGHT"), RTLIL::Const(RTLIL::S0, 6)); - cell->setParam(RTLIL::escape_id("ROUND"), RTLIL::Const(RTLIL::S0)); - cell->setParam(RTLIL::escape_id("REGISTER_INPUTS"), RTLIL::Const(RTLIL::S0)); - // 3 - output post acc; 1 - output pre acc - cell->setParam(RTLIL::escape_id("OUTPUT_SELECT"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); - } else { - cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0)); - cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6)); - cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0)); - cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0)); - // 3 - output post acc; 1 - output pre acc - cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); - } + cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6)); + cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0)); + // 3 - output post acc; 1 - output pre acc + cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); bool subtract = (st.add->type == RTLIL::escape_id("$sub")); cell->setPort(RTLIL::escape_id("subtract_i"), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); @@ -274,25 +259,14 @@ struct QlDspMacc : public Pass { log("\n"); log(" ql_dsp_macc [options] [selection]\n"); log("\n"); - log(" -use_dsp_cfg_params\n"); - log(" By default use DSP blocks with configuration bits available at module ports.\n"); - log(" Specifying this forces usage of DSP block with configuration bits available as module parameters\n"); - log("\n"); } - void clear_flags() override { use_dsp_cfg_params = false; } - void execute(std::vector a_Args, RTLIL::Design *a_Design) override { log_header(a_Design, "Executing QL_DSP_MACC pass.\n"); size_t argidx; for (argidx = 1; argidx < a_Args.size(); argidx++) { - if (a_Args[argidx] == "-use_dsp_cfg_params") { - use_dsp_cfg_params = true; - continue; - } - break; } extra_args(a_Args, argidx, a_Design); diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_map.v b/techlibs/quicklogic/qlf_k6n10f/dsp_map.v index bb9f05283e7..127145b71a9 100644 --- a/techlibs/quicklogic/qlf_k6n10f/dsp_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_map.v @@ -33,48 +33,25 @@ module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y); (B_SIGNED) ? {{(18 - B_WIDTH){B[B_WIDTH-1]}}, B} : {{(18 - B_WIDTH){1'b0}}, B}; - generate if (`USE_DSP_CFG_PARAMS == 0) begin - (* is_inferred=1 *) - dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ ( - .a_i (a), - .b_i (b), - .acc_fir_i (6'd0), - .z_o (z), - - .feedback_i (3'd0), - .load_acc_i (1'b0), - .unsigned_a_i (!A_SIGNED), - .unsigned_b_i (!B_SIGNED), - - .output_select_i (3'd0), - .saturate_enable_i (1'b0), - .shift_right_i (6'd0), - .round_i (1'b0), - .subtract_i (1'b0), - .register_inputs_i (1'b0) - ); - end else begin - (* is_inferred=1 *) - dsp_t1_20x18x64_cfg_params #( - .OUTPUT_SELECT (3'd0), - .SATURATE_ENABLE (1'b0), - .SHIFT_RIGHT (6'd0), - .ROUND (1'b0), - .REGISTER_INPUTS (1'b0) - ) TECHMAP_REPLACE_ ( - .a_i (a), - .b_i (b), - .acc_fir_i (6'd0), - .z_o (z), - - .feedback_i (3'd0), - .load_acc_i (1'b0), - .unsigned_a_i (!A_SIGNED), - .unsigned_b_i (!B_SIGNED), - - .subtract_i (1'b0) - ); - end endgenerate + (* is_inferred=1 *) + dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .output_select_i (3'd0), + .saturate_enable_i (1'b0), + .shift_right_i (6'd0), + .round_i (1'b0), + .subtract_i (1'b0), + .register_inputs_i (1'b0) + ); assign Y = z; @@ -99,48 +76,26 @@ module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y); (B_SIGNED) ? {{( 9 - B_WIDTH){B[B_WIDTH-1]}}, B} : {{( 9 - B_WIDTH){1'b0}}, B}; - generate if (`USE_DSP_CFG_PARAMS == 0) begin - (* is_inferred=1 *) - dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ ( - .a_i (a), - .b_i (b), - .acc_fir_i (6'd0), - .z_o (z), - - .feedback_i (3'd0), - .load_acc_i (1'b0), - .unsigned_a_i (!A_SIGNED), - .unsigned_b_i (!B_SIGNED), - - .output_select_i (3'd0), - .saturate_enable_i (1'b0), - .shift_right_i (6'd0), - .round_i (1'b0), - .subtract_i (1'b0), - .register_inputs_i (1'b0) - ); - end else begin - (* is_inferred=1 *) - dsp_t1_10x9x32_cfg_params #( - .OUTPUT_SELECT (3'd0), - .SATURATE_ENABLE (1'b0), - .SHIFT_RIGHT (6'd0), - .ROUND (1'b0), - .REGISTER_INPUTS (1'b0) - ) TECHMAP_REPLACE_ ( - .a_i (a), - .b_i (b), - .acc_fir_i (6'd0), - .z_o (z), - - .feedback_i (3'd0), - .load_acc_i (1'b0), - .unsigned_a_i (!A_SIGNED), - .unsigned_b_i (!B_SIGNED), - - .subtract_i (1'b0) - ); - end endgenerate + (* is_inferred=1 *) + dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .output_select_i (3'd0), + .saturate_enable_i (1'b0), + .shift_right_i (6'd0), + .round_i (1'b0), + .subtract_i (1'b0), + .register_inputs_i (1'b0) + ); + assign Y = z; diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v b/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v index 05a4835e868..5f43b322912 100644 --- a/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v @@ -4525,1229 +4525,3 @@ module dsp_t1_sim_cfg_ports # ( dly_b_o <= b_i; endmodule - - - -// ---------------------------------------- // -// ----- DSP cells simulation modules ----- // -// ------ Control bits in parameters ------ // -// ---------------------------------------- // - -module QL_DSP3 ( // TODO: Name subject to change - input wire [19:0] a, - input wire [17:0] b, - input wire [ 5:0] acc_fir, - output wire [37:0] z, - output wire [17:0] dly_b, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [2:0] feedback, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - localparam NBITS_ACC = 64; - localparam NBITS_A = 20; - localparam NBITS_B = 18; - localparam NBITS_Z = 38; - - // Fractured - generate if(F_MODE == 1'b1) begin - - wire [(NBITS_Z/2)-1:0] dsp_frac0_z; - wire [(NBITS_Z/2)-1:0] dsp_frac1_z; - - wire [(NBITS_B/2)-1:0] dsp_frac0_dly_b; - wire [(NBITS_B/2)-1:0] dsp_frac1_dly_b; - - dsp_t1_sim_cfg_params #( - .NBITS_A (NBITS_A/2), - .NBITS_B (NBITS_B/2), - .NBITS_ACC (NBITS_ACC/2), - .NBITS_Z (NBITS_Z/2), - .OUTPUT_SELECT (OUTPUT_SELECT), - .SATURATE_ENABLE (SATURATE_ENABLE), - .SHIFT_RIGHT (SHIFT_RIGHT), - .ROUND (ROUND), - .REGISTER_INPUTS (REGISTER_INPUTS) - ) dsp_frac0 ( - .a_i(a[(NBITS_A/2)-1:0]), - .b_i(b[(NBITS_B/2)-1:0]), - .z_o(dsp_frac0_z), - .dly_b_o(dsp_frac0_dly_b), - - .acc_fir_i(acc_fir), - .feedback_i(feedback), - .load_acc_i(load_acc), - - .unsigned_a_i(unsigned_a), - .unsigned_b_i(unsigned_b), - - .clock_i(clk), - .s_reset(reset), - - .subtract_i(subtract), - .coef_0_i(COEFF_0[(NBITS_A/2)-1:0]), - .coef_1_i(COEFF_1[(NBITS_A/2)-1:0]), - .coef_2_i(COEFF_2[(NBITS_A/2)-1:0]), - .coef_3_i(COEFF_3[(NBITS_A/2)-1:0]) - ); - - dsp_t1_sim_cfg_params #( - .NBITS_A (NBITS_A/2), - .NBITS_B (NBITS_B/2), - .NBITS_ACC (NBITS_ACC/2), - .NBITS_Z (NBITS_Z/2), - .OUTPUT_SELECT (OUTPUT_SELECT), - .SATURATE_ENABLE (SATURATE_ENABLE), - .SHIFT_RIGHT (SHIFT_RIGHT), - .ROUND (ROUND), - .REGISTER_INPUTS (REGISTER_INPUTS) - ) dsp_frac1 ( - .a_i(a[NBITS_A-1:NBITS_A/2]), - .b_i(b[NBITS_B-1:NBITS_B/2]), - .z_o(dsp_frac1_z), - .dly_b_o(dsp_frac1_dly_b), - .acc_fir_i(acc_fir), - .feedback_i(feedback), - .load_acc_i(load_acc), - - .unsigned_a_i(unsigned_a), - .unsigned_b_i(unsigned_b), - - .clock_i(clk), - .s_reset(reset), - - .subtract_i(subtract), - .coef_0_i(COEFF_0[NBITS_A-1:NBITS_A/2]), - .coef_1_i(COEFF_1[NBITS_A-1:NBITS_A/2]), - .coef_2_i(COEFF_2[NBITS_A-1:NBITS_A/2]), - .coef_3_i(COEFF_3[NBITS_A-1:NBITS_A/2]) - ); - - assign z = {dsp_frac1_z, dsp_frac0_z}; - assign dly_b = {dsp_frac1_dly_b, dsp_frac0_dly_b}; - - // Whole - end else begin - - dsp_t1_sim_cfg_params #( - .NBITS_A (NBITS_A), - .NBITS_B (NBITS_B), - .NBITS_ACC (NBITS_ACC), - .NBITS_Z (NBITS_Z), - .OUTPUT_SELECT (OUTPUT_SELECT), - .SATURATE_ENABLE (SATURATE_ENABLE), - .SHIFT_RIGHT (SHIFT_RIGHT), - .ROUND (ROUND), - .REGISTER_INPUTS (REGISTER_INPUTS) - ) dsp_full ( - .a_i(a), - .b_i(b), - .z_o(z), - .dly_b_o(dly_b), - - .acc_fir_i(acc_fir), - .feedback_i(feedback), - .load_acc_i(load_acc), - - .unsigned_a_i(unsigned_a), - .unsigned_b_i(unsigned_b), - - .clock_i(clk), - .s_reset(reset), - - .subtract_i(subtract), - .coef_0_i(COEFF_0), - .coef_1_i(COEFF_1), - .coef_2_i(COEFF_2), - .coef_3_i(COEFF_3) - ); - - end endgenerate - -endmodule - -module QL_DSP3_MULT ( // TODO: Name subject to change - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - input wire reset, - - input wire [2:0] feedback, - input wire unsigned_a, - input wire unsigned_b -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // unregistered output: a * b (0) - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .reset(reset), - - .feedback(feedback), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b) - ); -endmodule - -module QL_DSP3_MULT_REGIN ( // TODO: Name subject to change - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [2:0] feedback, - - input wire unsigned_a, - input wire unsigned_b -); - - wire [37:0] dly_b_o; - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // unregistered output: a * b (0) - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // registered inputs - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset) - ); -endmodule - -module QL_DSP3_MULT_REGOUT ( // TODO: Name subject to change - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [2:0] feedback, - - input wire unsigned_a, - input wire unsigned_b -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // registered output: a * b (4) - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset) - ); -endmodule - -module QL_DSP3_MULT_REGIN_REGOUT ( // TODO: Name subject to change - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [2:0] feedback, - - input wire unsigned_a, - input wire unsigned_b -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // registered output: a * b (4) - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset) - ); -endmodule - -module QL_DSP3_MULTADD ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - input wire reset, - - input wire [ 2:0] feedback, - input wire [ 5:0] acc_fir, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .acc_fir(acc_fir), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTADD_REGIN ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire [ 5:0] acc_fir, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .acc_fir(acc_fir), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTADD_REGOUT ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire [ 5:0] acc_fir, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .acc_fir(acc_fir), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTADD_REGIN_REGOUT ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire [ 5:0] acc_fir, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .acc_fir(acc_fir), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTACC ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTACC_REGIN ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTACC_REGOUT ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTACC_REGIN_REGOUT ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module dsp_t1_20x18x64_cfg_params ( - input wire [19:0] a_i, - input wire [17:0] b_i, - input wire [ 5:0] acc_fir_i, - output wire [37:0] z_o, - output wire [17:0] dly_b_o, - - (* clkbuf_sink *) - input wire clock_i, - input wire reset_i, - - input wire [ 2:0] feedback_i, - input wire load_acc_i, - input wire unsigned_a_i, - input wire unsigned_b_i, - input wire subtract_i -); - - parameter [19:0] COEFF_0 = 20'b0; - parameter [19:0] COEFF_1 = 20'b0; - parameter [19:0] COEFF_2 = 20'b0; - parameter [19:0] COEFF_3 = 20'b0; - - parameter [2:0] OUTPUT_SELECT = 3'b0; - parameter [0:0] SATURATE_ENABLE = 1'b0; - parameter [5:0] SHIFT_RIGHT = 6'b0; - parameter [0:0] ROUND = 1'b0; - parameter [0:0] REGISTER_INPUTS = 1'b0; - - QL_DSP3 #( - .MODE_BITS ({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - 1'b0, // Not fractured - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a_i), - .b(b_i), - .z(z_o), - .dly_b(dly_b_o), - - .acc_fir(acc_fir_i), - .feedback(feedback_i), - .load_acc(load_acc_i), - - .unsigned_a(unsigned_a_i), - .unsigned_b(unsigned_b_i), - - .clk(clock_i), - .reset(reset_i), - .subtract(subtract_i) - ); -endmodule - -module dsp_t1_10x9x32_cfg_params ( - input wire [ 9:0] a_i, - input wire [ 8:0] b_i, - input wire [ 5:0] acc_fir_i, - output wire [18:0] z_o, - output wire [ 8:0] dly_b_o, - - (* clkbuf_sink *) - input wire clock_i, - input wire reset_i, - - input wire [ 2:0] feedback_i, - input wire load_acc_i, - input wire unsigned_a_i, - input wire unsigned_b_i, - input wire subtract_i -); - - parameter [9:0] COEFF_0 = 10'b0; - parameter [9:0] COEFF_1 = 10'b0; - parameter [9:0] COEFF_2 = 10'b0; - parameter [9:0] COEFF_3 = 10'b0; - - parameter [2:0] OUTPUT_SELECT = 3'b0; - parameter [0:0] SATURATE_ENABLE = 1'b0; - parameter [5:0] SHIFT_RIGHT = 6'b0; - parameter [0:0] ROUND = 1'b0; - parameter [0:0] REGISTER_INPUTS = 1'b0; - - wire [18:0] z_rem; - wire [8:0] dly_b_rem; - - QL_DSP3 #( - .MODE_BITS ({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - 1'b1, // Fractured - 10'd0, COEFF_3, - 10'd0, COEFF_2, - 10'd0, COEFF_1, - 10'd0, COEFF_0 - }) - ) dsp ( - .a({10'b0, a_i}), - .b({9'b0, b_i}), - .z({z_rem, z_o}), - .dly_b({dly_b_rem, dly_b_o}), - - .acc_fir(acc_fir_i), - .feedback(feedback_i), - .load_acc(load_acc_i), - - .unsigned_a(unsigned_a_i), - .unsigned_b(unsigned_b_i), - - .clk(clock_i), - .reset(reset_i), - .subtract(subtract_i) - ); -endmodule - -module dsp_t1_sim_cfg_params # ( - parameter NBITS_ACC = 64, - parameter NBITS_A = 20, - parameter NBITS_B = 18, - parameter NBITS_Z = 38, - - parameter [2:0] OUTPUT_SELECT = 3'b0, - parameter [0:0] SATURATE_ENABLE = 1'b0, - parameter [5:0] SHIFT_RIGHT = 6'b0, - parameter [0:0] ROUND = 1'b0, - parameter [0:0] REGISTER_INPUTS = 1'b0 -)( - input wire [NBITS_A-1:0] a_i, - input wire [NBITS_B-1:0] b_i, - output wire [NBITS_Z-1:0] z_o, - output reg [NBITS_B-1:0] dly_b_o, - - input wire [5:0] acc_fir_i, - input wire [2:0] feedback_i, - input wire load_acc_i, - - input wire unsigned_a_i, - input wire unsigned_b_i, - - input wire clock_i, - input wire s_reset, - - input wire subtract_i, - input wire [NBITS_A-1:0] coef_0_i, - input wire [NBITS_A-1:0] coef_1_i, - input wire [NBITS_A-1:0] coef_2_i, - input wire [NBITS_A-1:0] coef_3_i -); - -// FIXME: The version of Icarus Verilog from Conda seems not to recognize the -// $error macro. Disable this sanity check for now because of that. - - // Input registers - reg [NBITS_A-1:0] r_a; - reg [NBITS_B-1:0] r_b; - reg [5:0] r_acc_fir; - reg r_unsigned_a; - reg r_unsigned_b; - reg r_load_acc; - reg [2:0] r_feedback; - reg [5:0] r_shift_d1; - reg [5:0] r_shift_d2; - reg r_subtract; - reg r_sat; - reg r_rnd; - reg [NBITS_ACC-1:0] acc; - - initial begin - r_a <= 0; - r_b <= 0; - - r_acc_fir <= 0; - r_unsigned_a <= 0; - r_unsigned_b <= 0; - r_feedback <= 0; - r_shift_d1 <= 0; - r_shift_d2 <= 0; - r_subtract <= 0; - r_load_acc <= 0; - r_sat <= 0; - r_rnd <= 0; - end - - always @(posedge clock_i or posedge s_reset) begin - if (s_reset) begin - - r_a <= 'h0; - r_b <= 'h0; - - r_acc_fir <= 0; - r_unsigned_a <= 0; - r_unsigned_b <= 0; - r_feedback <= 0; - r_shift_d1 <= 0; - r_shift_d2 <= 0; - r_subtract <= 0; - r_load_acc <= 0; - r_sat <= 0; - r_rnd <= 0; - - end else begin - - r_a <= a_i; - r_b <= b_i; - - r_acc_fir <= acc_fir_i; - r_unsigned_a <= unsigned_a_i; - r_unsigned_b <= unsigned_b_i; - r_feedback <= feedback_i; - r_shift_d1 <= SHIFT_RIGHT; - r_shift_d2 <= r_shift_d1; - r_subtract <= subtract_i; - r_load_acc <= load_acc_i; - r_sat <= r_sat; - r_rnd <= r_rnd; - - end - end - - // Registered / non-registered input path select - wire [NBITS_A-1:0] a = REGISTER_INPUTS ? r_a : a_i; - wire [NBITS_B-1:0] b = REGISTER_INPUTS ? r_b : b_i; - - wire [5:0] acc_fir = REGISTER_INPUTS ? r_acc_fir : acc_fir_i; - wire unsigned_a = REGISTER_INPUTS ? r_unsigned_a : unsigned_a_i; - wire unsigned_b = REGISTER_INPUTS ? r_unsigned_b : unsigned_b_i; - wire [2:0] feedback = REGISTER_INPUTS ? r_feedback : feedback_i; - wire load_acc = REGISTER_INPUTS ? r_load_acc : load_acc_i; - wire subtract = REGISTER_INPUTS ? r_subtract : subtract_i; - wire sat = REGISTER_INPUTS ? r_sat : SATURATE_ENABLE; - wire rnd = REGISTER_INPUTS ? r_rnd : ROUND; - - // Shift right control - wire [5:0] shift_d1 = REGISTER_INPUTS ? r_shift_d1 : SHIFT_RIGHT; - wire [5:0] shift_d2 = OUTPUT_SELECT[1] ? shift_d1 : r_shift_d2; - - // Multiplier - wire unsigned_mode = unsigned_a & unsigned_b; - wire [NBITS_A-1:0] mult_a; - assign mult_a = (feedback == 3'h0) ? a : - (feedback == 3'h1) ? a : - (feedback == 3'h2) ? a : - (feedback == 3'h3) ? acc[NBITS_A-1:0] : - (feedback == 3'h4) ? coef_0_i : - (feedback == 3'h5) ? coef_1_i : - (feedback == 3'h6) ? coef_2_i : - coef_3_i; // if feedback == 3'h7 - - wire [NBITS_B-1:0] mult_b = (feedback == 2'h2) ? {NBITS_B{1'b0}} : b; - - wire [NBITS_A-1:0] mult_sgn_a = mult_a[NBITS_A-1]; - wire [NBITS_A-1:0] mult_mag_a = (mult_sgn_a && !unsigned_a) ? (~mult_a + 1) : mult_a; - wire [NBITS_B-1:0] mult_sgn_b = mult_b[NBITS_B-1]; - wire [NBITS_B-1:0] mult_mag_b = (mult_sgn_b && !unsigned_b) ? (~mult_b + 1) : mult_b; - - wire [NBITS_A+NBITS_B-1:0] mult_mag = mult_mag_a * mult_mag_b; - wire mult_sgn = (mult_sgn_a && !unsigned_a) ^ (mult_sgn_b && !unsigned_b); - - wire [NBITS_A+NBITS_B-1:0] mult = (unsigned_a && unsigned_b) ? - (mult_a * mult_b) : (mult_sgn ? (~mult_mag + 1) : mult_mag); - - // Sign extension - wire [NBITS_ACC-1:0] mult_xtnd = unsigned_mode ? - {{(NBITS_ACC-NBITS_A-NBITS_B){1'b0}}, mult[NBITS_A+NBITS_B-1:0]} : - {{(NBITS_ACC-NBITS_A-NBITS_B){mult[NBITS_A+NBITS_B-1]}}, mult[NBITS_A+NBITS_B-1:0]}; - - // Adder - wire [NBITS_ACC-1:0] acc_fir_int = unsigned_a ? {{(NBITS_ACC-NBITS_A){1'b0}}, a} : - {{(NBITS_ACC-NBITS_A){a[NBITS_A-1]}}, a} ; - - wire [NBITS_ACC-1:0] add_a = (subtract) ? (~mult_xtnd + 1) : mult_xtnd; - wire [NBITS_ACC-1:0] add_b = (feedback_i == 3'h0) ? acc : - (feedback_i == 3'h1) ? {{NBITS_ACC}{1'b0}} : (acc_fir_int << acc_fir); - - wire [NBITS_ACC-1:0] add_o = add_a + add_b; - - // Accumulator - initial acc <= 0; - - always @(posedge clock_i or posedge s_reset) - if (s_reset) acc <= 'h0; - else begin - if (load_acc) - acc <= add_o; - else - acc <= acc; - end - - // Adder/accumulator output selection - wire [NBITS_ACC-1:0] acc_out = (OUTPUT_SELECT[1]) ? add_o : acc; - - // Round, shift, saturate - wire [NBITS_ACC-1:0] acc_rnd = (rnd && (SHIFT_RIGHT != 0)) ? (acc_out + ({{(NBITS_ACC-1){1'b0}}, 1'b1} << (SHIFT_RIGHT - 1))) : - acc_out; - - wire [NBITS_ACC-1:0] acc_shr = (unsigned_mode) ? (acc_rnd >> SHIFT_RIGHT) : - (acc_rnd >>> SHIFT_RIGHT); - - wire [NBITS_ACC-1:0] acc_sat_u = (acc_shr[NBITS_ACC-1:NBITS_Z] != 0) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{NBITS_Z{1'b1}}} : - {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}}; - - wire [NBITS_ACC-1:0] acc_sat_s = ((|acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b0) || - (&acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b1)) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}} : - {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_ACC-1],{NBITS_Z-1{~acc_shr[NBITS_ACC-1]}}}}; - - wire [NBITS_ACC-1:0] acc_sat = (sat) ? ((unsigned_mode) ? acc_sat_u : acc_sat_s) : acc_shr; - - // Output signals - wire [NBITS_Z-1:0] z0; - reg [NBITS_Z-1:0] z1; - wire [NBITS_Z-1:0] z2; - - assign z0 = mult_xtnd[NBITS_Z-1:0]; - assign z2 = acc_sat[NBITS_Z-1:0]; - - initial z1 <= 0; - - always @(posedge clock_i or posedge s_reset) - if (s_reset) - z1 <= 0; - else begin - z1 <= (OUTPUT_SELECT == 3'b100) ? z0 : z2; - end - - // Output mux - assign z_o = (OUTPUT_SELECT == 3'h0) ? z0 : - (OUTPUT_SELECT == 3'h1) ? z2 : - (OUTPUT_SELECT == 3'h2) ? z2 : - (OUTPUT_SELECT == 3'h3) ? z2 : - (OUTPUT_SELECT == 3'h4) ? z1 : - (OUTPUT_SELECT == 3'h5) ? z1 : - (OUTPUT_SELECT == 3'h6) ? z1 : - z1; // if OUTPUT_SELECT == 3'h7 - - // B input delayed passthrough - initial dly_b_o <= 0; - - always @(posedge clock_i or posedge s_reset) - if (s_reset) - dly_b_o <= 0; - else - dly_b_o <= b_i; - -endmodule diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 0a85749482e..101dff66597 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -50,11 +50,6 @@ struct SynthQuickLogicPass : public ScriptPass { log(" do not use dsp_t1_* to implement multipliers and associated logic\n"); log(" (qlf_k6n10f only).\n"); log("\n"); - log(" -use_dsp_cfg_params\n"); - log(" By default use DSP blocks with configuration bits available at module\n"); - log(" ports. Specifying this forces usage of DSP block with configuration\n"); - log(" bits available as module parameters.\n"); - log("\n"); log(" -nocarry\n"); log(" do not use adder_carry cells in output netlist.\n"); log("\n"); @@ -163,10 +158,6 @@ struct SynthQuickLogicPass : public ScriptPass { dsp = false; continue; } - if (args[argidx] == "-use_dsp_cfg_params") { - use_dsp_cfg_params = " -use_dsp_cfg_params"; - continue; - } break; } extra_args(args, argidx, design); @@ -231,16 +222,13 @@ struct SynthQuickLogicPass : public ScriptPass { if (check_label("map_dsp", "(for qlf_k6n10f, skip if -nodsp)") && ((dsp && family == "qlf_k6n10f") || help_mode)) { run("wreduce t:$mul"); - run("ql_dsp_macc" + use_dsp_cfg_params); + run("ql_dsp_macc"); run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18"); run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9"); run("chtype -set $mul t:$__soft_mul"); - - if (use_dsp_cfg_params.empty()) - run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0"); - else - run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1"); + + run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0"); run("ql_dsp_simd"); run("techmap -map " + lib_path + family + "/dsp_final_map.v"); run("ql_dsp_io_regs"); From 7d738b07dacd4c73e82966dc0053862c4b31973a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 2 Oct 2023 14:40:10 +0200 Subject: [PATCH 173/240] ql_dsp_*: Clean up Clean up the code up to Yosys standards. Drop detection of QL_DSP2_MULTADD in io_regs since those cells can't be inferred with the current flow anyway. --- techlibs/quicklogic/ql_dsp_io_regs.cc | 252 +++++++++----------------- techlibs/quicklogic/ql_dsp_simd.cc | 233 ++++++++---------------- 2 files changed, 157 insertions(+), 328 deletions(-) diff --git a/techlibs/quicklogic/ql_dsp_io_regs.cc b/techlibs/quicklogic/ql_dsp_io_regs.cc index 217a5aa5573..efb1ad4d5f3 100644 --- a/techlibs/quicklogic/ql_dsp_io_regs.cc +++ b/techlibs/quicklogic/ql_dsp_io_regs.cc @@ -30,26 +30,24 @@ PRIVATE_NAMESPACE_BEGIN // ============================================================================ struct QlDspIORegs : public Pass { - - const std::vector ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b"}; + const std::vector ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b", + "saturate_enable", "shift_right", "round"}; const std::vector ports2del_mult_acc = {"acc_fir", "dly_b"}; - const std::vector ports2del_mult_add = {"dly_b"}; - const std::vector ports2del_extension = {"saturate_enable", "shift_right", "round"}; - /// Temporary SigBit to SigBit helper map. - SigMap m_SigMap; + SigMap sigmap; // .......................................... - QlDspIORegs() : Pass("ql_dsp_io_regs", "Changes types of QL_DSP2/QL_DSP3 depending on their configuration.") {} + QlDspIORegs() : Pass("ql_dsp_io_regs", "change types of QL_DSP2 depending on configuration") {} void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" ql_dsp_io_regs [options] [selection]\n"); log("\n"); - log("Looks for QL_DSP2/QL_DSP3 cells and changes their types depending\n"); - log("on their configuration.\n"); + log("This pass looks for QL_DSP2 cells and changes their cell type depending on their\n"); + log("configuration.\n"); } void execute(std::vector a_Args, RTLIL::Design *a_Design) override @@ -67,178 +65,92 @@ struct QlDspIORegs : public Pass { } } - // Returns a pair of mask and value describing constant bit connections of - // a SigSpec - std::pair get_constant_mask_value(const RTLIL::SigSpec *sigspec) - { - uint32_t mask = 0L; - uint32_t value = 0L; - - auto sigbits = sigspec->bits(); - for (ssize_t i = (sigbits.size() - 1); i >= 0; --i) { - auto other = m_SigMap(sigbits[i]); - - mask <<= 1; - value <<= 1; - - // A known constant - if (!other.is_wire() && other.data != RTLIL::Sx) { - mask |= 0x1; - value |= (other.data == RTLIL::S1); - } - } - - return std::make_pair(mask, value); - } - void ql_dsp_io_regs_pass(RTLIL::Module *module) { - // Setup the SigMap - m_SigMap.clear(); - m_SigMap.set(module); - - for (auto cell : module->cells_) { - std::string cell_type = cell.second->type.str(); - if (cell_type == RTLIL::escape_id("QL_DSP2") || cell_type == RTLIL::escape_id("QL_DSP3")) { - auto dsp = cell.second; - - // If the cell does not have the "is_inferred" attribute set - // then don't touch it. - if (!dsp->has_attribute(RTLIL::escape_id("is_inferred")) || dsp->get_bool_attribute(RTLIL::escape_id("is_inferred")) == false) { - continue; - } - - bool del_clk = true; - bool use_dsp_cfg_params = (cell_type == RTLIL::escape_id("QL_DSP3")); - - int reg_in_i; - int out_sel_i; - - // Get DSP configuration - if (use_dsp_cfg_params) { - // Read MODE_BITS at correct indexes - auto mode_bits = &dsp->getParam(RTLIL::escape_id("MODE_BITS")); - RTLIL::Const register_inputs; - register_inputs = mode_bits->bits.at(MODE_BITS_REGISTER_INPUTS_ID); - reg_in_i = register_inputs.as_int(); - - RTLIL::Const output_select; - output_select = mode_bits->extract(MODE_BITS_OUTPUT_SELECT_START_ID, MODE_BITS_OUTPUT_SELECT_WIDTH); - out_sel_i = output_select.as_int(); - } else { - // Read dedicated configuration ports - const RTLIL::SigSpec *register_inputs; - register_inputs = &dsp->getPort(RTLIL::escape_id("register_inputs")); - if (!register_inputs) - log_error("register_inputs port not found!"); - auto reg_in_c = register_inputs->as_const(); - reg_in_i = reg_in_c.as_int(); - - const RTLIL::SigSpec *output_select; - output_select = &dsp->getPort(RTLIL::escape_id("output_select")); - if (!output_select) - log_error("output_select port not found!"); - auto out_sel_c = output_select->as_const(); - out_sel_i = out_sel_c.as_int(); - } - - // Get the feedback port - const RTLIL::SigSpec *feedback; - feedback = &dsp->getPort(RTLIL::escape_id("feedback")); - if (!feedback) - log_error("feedback port not found!"); - - // Check if feedback is or can be set to 0 which implies MACC - auto feedback_con = get_constant_mask_value(feedback); - bool have_macc = (feedback_con.second == 0x0); - // log("mask=0x%08X value=0x%08X\n", consts.first, consts.second); - // log_error("=== END HERE ===\n"); - - // Build new type name - std::string new_type = cell_type; - new_type += "_MULT"; - - if (have_macc) { - switch (out_sel_i) { - case 1: - case 2: - case 3: - case 5: - case 7: - del_clk = false; - new_type += "ACC"; - break; - default: - break; - } - } else { - switch (out_sel_i) { - case 1: - case 2: - case 3: - case 5: - case 7: - new_type += "ADD"; - break; - default: - break; - } - } - - if (reg_in_i) { - del_clk = false; - new_type += "_REGIN"; - } - - if (out_sel_i > 3) { - del_clk = false; - new_type += "_REGOUT"; - } - - // Set new type name - dsp->type = RTLIL::IdString(new_type); - - std::vector ports2del; - - if (del_clk) - ports2del.push_back("clk"); - - switch (out_sel_i) { - case 0: - case 4: - case 6: - ports2del.insert(ports2del.end(), ports2del_mult.begin(), ports2del_mult.end()); - // Mark for deleton additional configuration ports - if (!use_dsp_cfg_params) { - ports2del.insert(ports2del.end(), ports2del_extension.begin(), ports2del_extension.end()); - } - break; + sigmap.set(module); + + for (auto cell : module->cells()) { + if (cell->type != ID(QL_DSP2)) + continue; + + // If the cell does not have the "is_inferred" attribute set + // then don't touch it. + if (!cell->get_bool_attribute(ID(is_inferred))) + continue; + + // Get DSP configuration + for (auto cfg_port : {ID(register_inputs), ID(output_select)}) + if (!cell->hasPort(cfg_port) || sigmap(cell->getPort(cfg_port)).is_fully_const()) + log_error("Missing or non-constant '%s' port on DSP cell %s\n", + log_id(cfg_port), log_id(cell)); + int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int(); + int out_sel_i = sigmap(cell->getPort(ID(output_select))).as_int(); + + // Get the feedback port + if (!cell->hasPort(ID(feedback))) + log_error("Missing 'feedback' port on %s", log_id(cell)); + SigSpec feedback = sigmap(cell->getPort(ID(feedback))); + + // Check the top two bits on 'feedback' to be constant zero. + // That's what we are expecting from inference. + if (feedback.extract(1, 2) != SigSpec(0, 2)) + log_error("Unexpected feedback configuration on %s\n", log_id(cell)); + + // Build new type name + std::string new_type = "QL_DSP2_MULT"; + + // Decide if we should be deleting the clock port + bool del_clk = true; + + switch (out_sel_i) { case 1: case 2: case 3: case 5: case 7: - if (have_macc) { - ports2del.insert(ports2del.end(), ports2del_mult_acc.begin(), ports2del_mult_acc.end()); - } else { - ports2del.insert(ports2del.end(), ports2del_mult_add.begin(), ports2del_mult_add.end()); - } + del_clk = false; + new_type += "ACC"; + break; + default: break; - } - - for (auto portname : ports2del) { - const RTLIL::SigSpec *port = &dsp->getPort(RTLIL::escape_id(portname)); - if (!port) - log_error("%s port not found!", portname.c_str()); - dsp->connections_.erase(RTLIL::escape_id(portname)); - } } - } - // Clear the sigmap - m_SigMap.clear(); - } + if (reg_in_i) { + del_clk = false; + new_type += "_REGIN"; + } + + if (out_sel_i > 3) { + del_clk = false; + new_type += "_REGOUT"; + } + // Set new type name + cell->type = RTLIL::IdString(new_type); + + std::vector ports2del; + + if (del_clk) + cell->unsetPort(ID(clk)); + + switch (out_sel_i) { + case 0: + case 4: + case 6: + for (auto port : ports2del_mult) + cell->unsetPort(port); + break; + case 1: + case 2: + case 3: + case 5: + case 7: + for (auto port : ports2del_mult_acc) + cell->unsetPort(port); + break; + } + } + } } QlDspIORegs; PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc index 5213aa1c4ac..153f3995f64 100644 --- a/techlibs/quicklogic/ql_dsp_simd.cc +++ b/techlibs/quicklogic/ql_dsp_simd.cc @@ -24,39 +24,30 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#define MODE_BITS_BASE_SIZE 80 -#define MODE_BITS_EXTENSION_SIZE 13 // ============================================================================ struct QlDspSimdPass : public Pass { - QlDspSimdPass() : Pass("ql_dsp_simd", "Infers QuickLogic k6n10f DSP pairs that can operate in SIMD mode") {} + QlDspSimdPass() : Pass("ql_dsp_simd", "merge QuickLogic K6N10f DSP pairs to operate in SIMD mode") {} void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" ql_dsp_simd [selection]\n"); log("\n"); - log(" This pass identifies k6n10f DSP cells with identical configuration\n"); - log(" and packs pairs of them together into other DSP cells that can\n"); - log(" perform SIMD operation.\n"); + log("This pass identifies K6N10f DSP cells with identical configuration and pack pairs\n"); + log("of them together into other DSP cells that can perform SIMD operation.\n"); } // .......................................... /// Describes DSP config unique to a whole DSP cell struct DspConfig { - // Port connections dict connections; - // Whether DSPs pass configuration bits through ports of parameters - bool use_cfg_params; - - // TODO: Possibly include parameters here. For now we have just - // connections. - DspConfig() = default; DspConfig(const DspConfig &ref) = default; @@ -64,50 +55,50 @@ struct QlDspSimdPass : public Pass { unsigned int hash() const { return connections.hash(); } - bool operator==(const DspConfig &ref) const { return connections == ref.connections && use_cfg_params == ref.use_cfg_params; } + bool operator==(const DspConfig &ref) const { return connections == ref.connections; } }; // .......................................... // DSP control and config ports to consider and how to map them to ports // of the target DSP cell - const std::vector> m_DspCfgPorts = {std::make_pair("clock_i", "clk"), - std::make_pair("reset_i", "reset"), - - std::make_pair("feedback_i", "feedback"), - std::make_pair("load_acc_i", "load_acc"), - std::make_pair("unsigned_a_i", "unsigned_a"), - std::make_pair("unsigned_b_i", "unsigned_b"), - - std::make_pair("subtract_i", "subtract")}; - // For QL_DSP2 expand with configuration ports - const std::vector> m_DspCfgPorts_expand = { - std::make_pair("output_select_i", "output_select"), std::make_pair("saturate_enable_i", "saturate_enable"), - std::make_pair("shift_right_i", "shift_right"), std::make_pair("round_i", "round"), std::make_pair("register_inputs_i", "register_inputs")}; + const std::vector> m_DspCfgPorts = { + std::make_pair(ID(clock_i), ID(clk)), + std::make_pair(ID(reset_i), ID(reset)), + std::make_pair(ID(feedback_i), ID(feedback)), + std::make_pair(ID(load_acc_i), ID(load_acc)), + std::make_pair(ID(unsigned_a_i), ID(unsigned_a)), + std::make_pair(ID(unsigned_b_i), ID(unsigned_b)), + std::make_pair(ID(subtract_i), ID(subtract)), + std::make_pair(ID(output_select_i), ID(output_select)), + std::make_pair(ID(saturate_enable_i), ID(saturate_enable)), + std::make_pair(ID(shift_right_i), ID(shift_right)), + std::make_pair(ID(round_i), ID(round)), + std::make_pair(ID(register_inputs_i), ID(register_inputs)) + }; - // For QL_DSP3 use parameters instead - const std::vector m_DspParams2Mode = {"OUTPUT_SELECT", "SATURATE_ENABLE", "SHIFT_RIGHT", "ROUND", "REGISTER_INPUTS"}; + const int m_ModeBitsSize = 80; // DSP data ports and how to map them to ports of the target DSP cell - const std::vector> m_DspDataPorts = { - std::make_pair("a_i", "a"), std::make_pair("b_i", "b"), std::make_pair("acc_fir_i", "acc_fir"), - std::make_pair("z_o", "z"), std::make_pair("dly_b_o", "dly_b"), + const std::vector> m_DspDataPorts = { + std::make_pair(ID(a_i), ID(a)), + std::make_pair(ID(b_i), ID(b)), + std::make_pair(ID(acc_fir_i), ID(acc_fir)), + std::make_pair(ID(z_o), ID(z)), + std::make_pair(ID(dly_b_o), ID(dly_b)) }; // DSP parameters const std::vector m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"}; // Source DSP cell type (SISD) - const std::string m_SisdDspType = "dsp_t1_10x9x32"; - // Suffix for DSP cell with configuration parameters - const std::string m_SisdDspType_cfg_params_suffix = "_cfg_params"; + const IdString m_SisdDspType = ID(dsp_t1_10x9x32); // Target DSP cell types for the SIMD mode - const std::string m_SimdDspType_cfg_ports = "QL_DSP2"; - const std::string m_SimdDspType_cfg_params = "QL_DSP3"; + const IdString m_SimdDspType = ID(QL_DSP2); /// Temporary SigBit to SigBit helper map. - SigMap m_SigMap; + SigMap sigmap; // .......................................... @@ -120,38 +111,32 @@ struct QlDspSimdPass : public Pass { // Process modules for (auto module : a_Design->selected_modules()) { - // Setup the SigMap - m_SigMap.clear(); - m_SigMap.set(module); + sigmap.set(module); // Assemble DSP cell groups dict> groups; for (auto cell : module->selected_cells()) { - // Check if this is a DSP cell we are looking for (type starts with m_SisdDspType) - if (strncmp(cell->type.c_str(), RTLIL::escape_id(m_SisdDspType).c_str(), RTLIL::escape_id(m_SisdDspType).size()) != 0) { + if (cell->type != m_SisdDspType) continue; - } // Skip if it has the (* keep *) attribute set - if (cell->has_keep_attr()) { + if (cell->has_keep_attr()) continue; - } // Add to a group const auto key = getDspConfig(cell); groups[key].push_back(cell); } - std::vector cellsToRemove; + std::vector cellsToRemove; // Map cell pairs to the target DSP SIMD cell for (const auto &it : groups) { const auto &group = it.second; const auto &config = it.first; - bool use_cfg_params = config.use_cfg_params; // Ensure an even number size_t count = group.size(); if (count & 1) @@ -159,66 +144,45 @@ struct QlDspSimdPass : public Pass { // Map SIMD pairs for (size_t i = 0; i < count; i += 2) { - const RTLIL::Cell *dsp_a = group[i]; - const RTLIL::Cell *dsp_b = group[i + 1]; - - std::string name = stringf("simd%ld", i / 2); - std::string SimdDspType; - - if (use_cfg_params) - SimdDspType = m_SimdDspType_cfg_params; - else - SimdDspType = m_SimdDspType_cfg_ports; - - log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", RTLIL::unescape_id(dsp_a->name).c_str(), RTLIL::unescape_id(dsp_a->type).c_str(), - RTLIL::unescape_id(dsp_b->name).c_str(), RTLIL::unescape_id(dsp_b->type).c_str(), RTLIL::unescape_id(name).c_str(), - SimdDspType.c_str()); + Cell *dsp_a = group[i]; + Cell *dsp_b = group[i + 1]; // Create the new cell - RTLIL::Cell *simd = module->addCell(RTLIL::escape_id(name), RTLIL::escape_id(SimdDspType)); + Cell *simd = module->addCell(NEW_ID, m_SimdDspType); + + log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", log_id(dsp_a), log_id(dsp_a->type), + log_id(dsp_b), log_id(dsp_b->type), log_id(simd), log_id(simd->type)); // Check if the target cell is known (important to know // its port widths) - if (!simd->known()) { - log_error(" The target cell type '%s' is not known!", SimdDspType.c_str()); - } - - std::vector> DspCfgPorts = m_DspCfgPorts; - if (!use_cfg_params) - DspCfgPorts.insert(DspCfgPorts.end(), m_DspCfgPorts_expand.begin(), m_DspCfgPorts_expand.end()); + if (!simd->known()) + log_error(" The target cell type '%s' is not known!", log_id(simd)); // Connect common ports - for (const auto &it : DspCfgPorts) { - auto sport = RTLIL::escape_id(it.first); - auto dport = RTLIL::escape_id(it.second); - - simd->setPort(dport, config.connections.at(sport)); - } + for (const auto &it : m_DspCfgPorts) + simd->setPort(it.first, config.connections.at(it.second)); // Connect data ports for (const auto &it : m_DspDataPorts) { - auto sport = RTLIL::escape_id(it.first); - auto dport = RTLIL::escape_id(it.second); - size_t width; bool isOutput; - std::tie(width, isOutput) = getPortInfo(simd, dport); + std::tie(width, isOutput) = getPortInfo(simd, it.second); auto getConnection = [&](const RTLIL::Cell *cell) { RTLIL::SigSpec sigspec; - if (cell->hasPort(sport)) { - const auto &sig = cell->getPort(sport); + if (cell->hasPort(it.first)) { + const auto &sig = cell->getPort(it.first); sigspec.append(sig); } - if (sigspec.bits().size() < width / 2) { - if (isOutput) { - for (size_t i = 0; i < width / 2 - sigspec.bits().size(); ++i) { - sigspec.append(RTLIL::SigSpec()); - } - } else { - sigspec.append(RTLIL::SigSpec(RTLIL::Sx, width / 2 - sigspec.bits().size())); - } + + int padding = width / 2 - sigspec.bits().size(); + + if (padding) { + if (!isOutput) + sigspec.append(RTLIL::SigSpec(RTLIL::Sx, padding)); + else + sigspec.append(module->addWire(NEW_ID, padding)); } return sigspec; }; @@ -226,49 +190,31 @@ struct QlDspSimdPass : public Pass { RTLIL::SigSpec sigspec; sigspec.append(getConnection(dsp_a)); sigspec.append(getConnection(dsp_b)); - simd->setPort(dport, sigspec); + simd->setPort(it.second, sigspec); } // Concatenate FIR coefficient parameters into the single // MODE_BITS parameter - std::vector mode_bits; + Const mode_bits; for (const auto &it : m_DspParams) { - auto val_a = dsp_a->getParam(RTLIL::escape_id(it)); - auto val_b = dsp_b->getParam(RTLIL::escape_id(it)); + auto val_a = dsp_a->getParam(it); + auto val_b = dsp_b->getParam(it); - mode_bits.insert(mode_bits.end(), val_a.begin(), val_a.end()); - mode_bits.insert(mode_bits.end(), val_b.begin(), val_b.end()); - } - long unsigned int mode_bits_size = MODE_BITS_BASE_SIZE; - if (use_cfg_params) { - // Add additional config parameters if necessary - mode_bits.push_back(RTLIL::S1); // MODE_BITS[80] == F_MODE : Enable fractured mode - for (const auto &it : m_DspParams2Mode) { - log_assert(dsp_a->getParam(RTLIL::escape_id(it)) == dsp_b->getParam(RTLIL::escape_id(it))); - auto param = dsp_a->getParam(RTLIL::escape_id(it)); - if (param.size() > 1) { - mode_bits.insert(mode_bits.end(), param.bits.begin(), param.bits.end()); - } else { - mode_bits.push_back(param.bits[0]); - } - } - mode_bits_size += MODE_BITS_EXTENSION_SIZE; - } else { - // Enable the fractured mode by connecting the control - // port. - simd->setPort(RTLIL::escape_id("f_mode"), RTLIL::S1); + mode_bits.bits.insert(mode_bits.end(), val_a.begin(), val_a.end()); + mode_bits.bits.insert(mode_bits.end(), val_b.begin(), val_b.end()); } - simd->setParam(RTLIL::escape_id("MODE_BITS"), RTLIL::Const(mode_bits)); - log_assert(mode_bits.size() == mode_bits_size); + + // Enable the fractured mode by connecting the control + // port. + simd->setPort(ID(f_mode), State::S1); + simd->setParam(ID(MODE_BITS), mode_bits); + log_assert(mode_bits.size() == m_ModeBitsSize); // Handle the "is_inferred" attribute. If one of the fragments // is not inferred mark the whole DSP as not inferred - bool is_inferred_a = - dsp_a->has_attribute(RTLIL::escape_id("is_inferred")) ? dsp_a->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false; - bool is_inferred_b = - dsp_b->has_attribute(RTLIL::escape_id("is_inferred")) ? dsp_b->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false; - - simd->set_bool_attribute(RTLIL::escape_id("is_inferred"), is_inferred_a && is_inferred_b); + bool is_inferred_a = dsp_a->get_bool_attribute(ID(is_inferred)); + bool is_inferred_b = dsp_b->get_bool_attribute(ID(is_inferred)); + simd->set_bool_attribute(ID(is_inferred), is_inferred_a && is_inferred_b); // Mark DSP parts for removal cellsToRemove.push_back(dsp_a); @@ -277,13 +223,9 @@ struct QlDspSimdPass : public Pass { } // Remove old cells - for (const auto &cell : cellsToRemove) { - module->remove(const_cast(cell)); - } + for (auto cell : cellsToRemove) + module->remove(cell); } - - // Clear - m_SigMap.clear(); } // .......................................... @@ -317,43 +259,18 @@ struct QlDspSimdPass : public Pass { { DspConfig config; - string cell_type = a_Cell->type.str(); - string suffix = m_SisdDspType_cfg_params_suffix; - - bool use_cfg_params = cell_type.size() >= suffix.size() && 0 == cell_type.compare(cell_type.size() - suffix.size(), suffix.size(), suffix); - - std::vector> DspCfgPorts = m_DspCfgPorts; - if (!use_cfg_params) - DspCfgPorts.insert(DspCfgPorts.end(), m_DspCfgPorts_expand.begin(), m_DspCfgPorts_expand.end()); - - config.use_cfg_params = use_cfg_params; - - for (const auto &it : DspCfgPorts) { - auto port = RTLIL::escape_id(it.first); + for (const auto &it : m_DspCfgPorts) { + auto port = it.first; // Port unconnected - if (!a_Cell->hasPort(port)) { - config.connections[port] = RTLIL::SigSpec(RTLIL::Sx); + if (!a_Cell->hasPort(port)) continue; - } - // Get the port connection and map it to unique SigBits - const auto &orgSigSpec = a_Cell->getPort(port); - const auto &orgSigBits = orgSigSpec.bits(); - - RTLIL::SigSpec newSigSpec; - for (size_t i = 0; i < orgSigBits.size(); ++i) { - auto newSigBit = m_SigMap(orgSigBits[i]); - newSigSpec.append(newSigBit); - } - - // Store - config.connections[port] = newSigSpec; + config.connections[port] = sigmap(a_Cell->getPort(port)); } return config; } - } QlDspSimdPass; PRIVATE_NAMESPACE_END From e43810e13f4dc344962df139adff5867914116b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 2 Oct 2023 15:55:41 +0200 Subject: [PATCH 174/240] ql_dsp_macc: Tune DSP inference code --- techlibs/quicklogic/ql_dsp_macc.cc | 381 ++++++++++++---------------- techlibs/quicklogic/ql_dsp_macc.pmg | 55 +++- 2 files changed, 198 insertions(+), 238 deletions(-) diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc index 602fbf3cc1a..b99b32b95cb 100644 --- a/techlibs/quicklogic/ql_dsp_macc.cc +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -29,235 +29,169 @@ PRIVATE_NAMESPACE_BEGIN static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) { - auto &st = pm.st_ql_dsp_macc; - - // Reject if multiplier drives anything else than either $add or $add and - // $mux - if (st.mux == nullptr && st.mul_nusers > 2) { - return; - } - - // Determine whether the output is taken from before or after the ff - bool out_ff; - if (st.ff_d_nusers == 2 && st.ff_q_nusers == 3) { - out_ff = true; - } else if (st.ff_d_nusers == 3 && st.ff_q_nusers == 2) { - out_ff = false; - } else { - // Illegal, cannot take the two outputs simulataneously - return; - } - - // No mux, the adder can driver either the ff or the ff + output - if (st.mux == nullptr) { - if (out_ff && st.add_nusers != 2) { - return; - } - if (!out_ff && st.add_nusers != 3) { - return; - } - } - // Mux present, the adder cannot drive anything else - else { - if (st.add_nusers != 2) { - return; - } - } - - // Mux can driver either the ff or the ff + output - if (st.mux != nullptr) { - if (out_ff && st.mux_nusers != 2) { - return; - } - if (!out_ff && st.mux_nusers != 3) { - return; - } - } - - // Accept only posedge clocked FFs - if (st.ff->getParam(ID(CLK_POLARITY)).as_int() != 1) { - return; - } - - // Get port widths - size_t a_width = GetSize(st.mul->getPort(ID(A))); - size_t b_width = GetSize(st.mul->getPort(ID(B))); - size_t z_width = GetSize(st.ff->getPort(ID(Q))); - - size_t min_width = std::min(a_width, b_width); - size_t max_width = std::max(a_width, b_width); - - // Signed / unsigned - bool a_signed = st.mul->getParam(ID(A_SIGNED)).as_bool(); - bool b_signed = st.mul->getParam(ID(B_SIGNED)).as_bool(); - - // Determine DSP type or discard if too narrow / wide - RTLIL::IdString type; - size_t tgt_a_width; - size_t tgt_b_width; - size_t tgt_z_width; - - string cell_base_name = "dsp_t1"; - string cell_size_name = ""; - string cell_cfg_name = ""; - string cell_full_name = ""; - - if (min_width <= 2 && max_width <= 2 && z_width <= 4) { - // Too narrow - return; - } else if (min_width <= 9 && max_width <= 10 && z_width <= 19) { - cell_size_name = "_10x9x32"; - tgt_a_width = 10; - tgt_b_width = 9; - tgt_z_width = 19; - } else if (min_width <= 18 && max_width <= 20 && z_width <= 38) { - cell_size_name = "_20x18x64"; - tgt_a_width = 20; - tgt_b_width = 18; - tgt_z_width = 38; - } else { - // Too wide - return; - } - - cell_cfg_name = "_cfg_ports"; // TODO: remove - cell_full_name = cell_base_name + cell_size_name + cell_cfg_name; - - type = RTLIL::escape_id(cell_full_name); - log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, RTLIL::unescape_id(type).c_str()); - - for (auto cell : {st.mul, st.add, st.mux, st.ff}) { - if (cell != nullptr) { - log(" %s (%s)\n", RTLIL::unescape_id(cell->name).c_str(), RTLIL::unescape_id(cell->type).c_str()); - } - } - - // Build the DSP cell name - std::string name; - name += RTLIL::unescape_id(st.mul->name) + "_"; - name += RTLIL::unescape_id(st.add->name) + "_"; - if (st.mux != nullptr) { - name += RTLIL::unescape_id(st.mux->name) + "_"; - } - name += RTLIL::unescape_id(st.ff->name); - - // Add the DSP cell - RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id(name), type); - - // Set attributes - cell->set_bool_attribute(RTLIL::escape_id("is_inferred"), true); - - // Get input/output data signals - RTLIL::SigSpec sig_a; - RTLIL::SigSpec sig_b; - RTLIL::SigSpec sig_z; - - if (a_width >= b_width) { - sig_a = st.mul->getPort(ID(A)); - sig_b = st.mul->getPort(ID(B)); - } else { - sig_a = st.mul->getPort(ID(B)); - sig_b = st.mul->getPort(ID(A)); - } - - sig_z = out_ff ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D)); - - // Connect input data ports, sign extend / pad with zeros - sig_a.extend_u0(tgt_a_width, a_signed); - sig_b.extend_u0(tgt_b_width, b_signed); - cell->setPort(RTLIL::escape_id("a_i"), sig_a); - cell->setPort(RTLIL::escape_id("b_i"), sig_b); - - // Connect output data port, pad if needed - if ((size_t)GetSize(sig_z) < tgt_z_width) { - auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z)); - sig_z.append(wire); - } - cell->setPort(RTLIL::escape_id("z_o"), sig_z); - - // Connect clock, reset and enable - cell->setPort(RTLIL::escape_id("clock_i"), st.ff->getPort(ID(CLK))); - - RTLIL::SigSpec rst; - RTLIL::SigSpec ena; - - if (st.ff->hasPort(ID(ARST))) { - if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) { - rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST))); - } else { - rst = st.ff->getPort(ID(ARST)); - } - } else { - rst = RTLIL::SigSpec(RTLIL::S0); - } - - if (st.ff->hasPort(ID(EN))) { - if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) { - ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN))); - } else { - ena = st.ff->getPort(ID(EN)); - } - } else { - ena = RTLIL::SigSpec(RTLIL::S1); - } - - cell->setPort(RTLIL::escape_id("reset_i"), rst); - cell->setPort(RTLIL::escape_id("load_acc_i"), ena); - - // Insert feedback_i control logic used for clearing / loading the accumulator - if (st.mux != nullptr) { - RTLIL::SigSpec sig_s = st.mux->getPort(ID(S)); - - // Depending on the mux port ordering insert inverter if needed - log_assert(st.mux_ab == ID(A) || st.mux_ab == ID(B)); - if (st.mux_ab == ID(A)) { - sig_s = pm.module->Not(NEW_ID, sig_s); - } - - // Assemble the full control signal for the feedback_i port - RTLIL::SigSpec sig_f; - sig_f.append(sig_s); - sig_f.append(RTLIL::S0); - sig_f.append(RTLIL::S0); - cell->setPort(RTLIL::escape_id("feedback_i"), sig_f); - } - // No acc clear/load - else { - cell->setPort(RTLIL::escape_id("feedback_i"), RTLIL::SigSpec(RTLIL::S0, 3)); - } - - // Connect control ports - cell->setPort(RTLIL::escape_id("unsigned_a_i"), RTLIL::SigSpec(a_signed ? RTLIL::S0 : RTLIL::S1)); - cell->setPort(RTLIL::escape_id("unsigned_b_i"), RTLIL::SigSpec(b_signed ? RTLIL::S0 : RTLIL::S1)); - - // Connect config bits - cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0)); - cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6)); - cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0)); - cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0)); - // 3 - output post acc; 1 - output pre acc - cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); - - bool subtract = (st.add->type == RTLIL::escape_id("$sub")); - cell->setPort(RTLIL::escape_id("subtract_i"), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); - - // Mark the cells for removal - pm.autoremove(st.mul); - pm.autoremove(st.add); - if (st.mux != nullptr) { - pm.autoremove(st.mux); - } - pm.autoremove(st.ff); + auto &st = pm.st_ql_dsp_macc; + + // Get port widths + size_t a_width = GetSize(st.mul->getPort(ID(A))); + size_t b_width = GetSize(st.mul->getPort(ID(B))); + size_t z_width = GetSize(st.ff->getPort(ID(Q))); + + size_t min_width = std::min(a_width, b_width); + size_t max_width = std::max(a_width, b_width); + + // Signed / unsigned + bool ab_signed = st.mul->getParam(ID(A_SIGNED)).as_bool(); + log_assert(ab_signed == st.mul->getParam(ID(B_SIGNED)).as_bool()); + + // Determine DSP type or discard if too narrow / wide + RTLIL::IdString type; + size_t tgt_a_width; + size_t tgt_b_width; + size_t tgt_z_width; + + string cell_base_name = "dsp_t1"; + string cell_size_name = ""; + string cell_cfg_name = ""; + string cell_full_name = ""; + + if (min_width <= 2 && max_width <= 2 && z_width <= 4) { + log_debug("\trejected: too narrow (%zd %zd %zd)\n", min_width, max_width, z_width); + return; + } else if (min_width <= 9 && max_width <= 10 && z_width <= 19) { + cell_size_name = "_10x9x32"; + tgt_a_width = 10; + tgt_b_width = 9; + tgt_z_width = 19; + } else if (min_width <= 18 && max_width <= 20 && z_width <= 38) { + cell_size_name = "_20x18x64"; + tgt_a_width = 20; + tgt_b_width = 18; + tgt_z_width = 38; + } else { + log_debug("\trejected: too wide (%zd %zd %zd)\n", min_width, max_width, z_width); + return; + } + + type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports"); + log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, log_id(type)); + + for (auto cell : {st.mul, st.add, st.mux, st.ff}) + if (cell) + log(" %s (%s)\n", log_id(cell), log_id(cell->type)); + + // Add the DSP cell + RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type); + + // Set attributes + cell->set_bool_attribute(ID(is_inferred), true); + + // Get input/output data signals + RTLIL::SigSpec sig_a, sig_b, sig_z; + sig_a = st.mul->getPort(ID(A)); + sig_b = st.mul->getPort(ID(B)); + sig_z = st.output_registered ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D)); + + if (a_width < b_width) + std::swap(sig_a, sig_b); + + // Connect input data ports, sign extend / pad with zeros + sig_a.extend_u0(tgt_a_width, ab_signed); + sig_b.extend_u0(tgt_b_width, ab_signed); + cell->setPort(ID(a_i), sig_a); + cell->setPort(ID(b_i), sig_b); + + // Connect output data port, pad if needed + if ((size_t) GetSize(sig_z) < tgt_z_width) { + auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z)); + sig_z.append(wire); + } + cell->setPort(ID(z_o), sig_z); + + // Connect clock, reset and enable + cell->setPort(ID(clock_i), st.ff->getPort(ID(CLK))); + + RTLIL::SigSpec rst; + RTLIL::SigSpec ena; + + if (st.ff->hasPort(ID(ARST))) { + if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) { + rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST))); + } else { + rst = st.ff->getPort(ID(ARST)); + } + } else { + rst = RTLIL::SigSpec(RTLIL::S0); + } + + if (st.ff->hasPort(ID(EN))) { + if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) { + ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN))); + } else { + ena = st.ff->getPort(ID(EN)); + } + } else { + ena = RTLIL::SigSpec(RTLIL::S1); + } + + cell->setPort(ID(reset_i), rst); + cell->setPort(ID(load_acc_i), ena); + + // Insert feedback_i control logic used for clearing / loading the accumulator + if (st.mux_in_pattern) { + RTLIL::SigSpec sig_s = st.mux->getPort(ID(S)); + + // Depending on the mux port ordering insert inverter if needed + log_assert(st.mux_ab.in(ID(A), ID(B))); + if (st.mux_ab == ID(A)) + sig_s = pm.module->Not(NEW_ID, sig_s); + + // Assemble the full control signal for the feedback_i port + RTLIL::SigSpec sig_f; + sig_f.append(sig_s); + sig_f.append(RTLIL::S0); + sig_f.append(RTLIL::S0); + cell->setPort(ID(feedback_i), sig_f); + } + // No acc clear/load + else { + cell->setPort(ID(feedback_i), RTLIL::SigSpec(RTLIL::S0, 3)); + } + + // Connect control ports + cell->setPort(ID(unsigned_a_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1)); + cell->setPort(ID(unsigned_b_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1)); + + // Connect config bits + cell->setPort(ID(saturate_enable_i), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(ID(shift_right_i), RTLIL::SigSpec(RTLIL::S0, 6)); + cell->setPort(ID(round_i), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(ID(register_inputs_i), RTLIL::SigSpec(RTLIL::S0)); + // 3 - output post acc; 1 - output pre acc + cell->setPort(ID(output_select_i), RTLIL::Const(st.output_registered ? 1 : 3, 3)); + + bool subtract = (st.add->type == ID($sub)); + cell->setPort(ID(subtract_i), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); + + // Mark the cells for removal + pm.autoremove(st.mul); + pm.autoremove(st.add); + if (st.mux != nullptr) { + pm.autoremove(st.mux); + } + pm.autoremove(st.ff); } struct QlDspMacc : public Pass { - - QlDspMacc() : Pass("ql_dsp_macc", "Does something") {} + QlDspMacc() : Pass("ql_dsp_macc", "infer QuickLogic multiplier-accumulator DSP cells") {} void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" ql_dsp_macc [options] [selection]\n"); + log(" ql_dsp_macc [selection]\n"); + log("\n"); + log("This pass looks for a multiply-accumulate pattern based on which it infers a\n"); + log("QuickLogic DSP cell.\n"); log("\n"); } @@ -271,9 +205,8 @@ struct QlDspMacc : public Pass { } extra_args(a_Args, argidx, a_Design); - for (auto module : a_Design->selected_modules()) { + for (auto module : a_Design->selected_modules()) ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp); - } } } QlDspMacc; diff --git a/techlibs/quicklogic/ql_dsp_macc.pmg b/techlibs/quicklogic/ql_dsp_macc.pmg index 4cfd15a2436..df18596d109 100644 --- a/techlibs/quicklogic/ql_dsp_macc.pmg +++ b/techlibs/quicklogic/ql_dsp_macc.pmg @@ -1,48 +1,75 @@ pattern ql_dsp_macc +// Rough sketch: (mux is optional) +// +// /-----------------------\ +// | | +// \ / | +// mul ----> add -----> mux -----> ff -+----> +// | /\ +// | | +// -------------- state add_ba state mux_ab -state mul_nusers -state add_nusers -state mux_nusers -state ff_d_nusers -state ff_q_nusers +// Is the output taken from before or after the FF? +state output_registered +// Is there a mux in the pattern? +state mux_in_pattern + +code mux_in_pattern + mux_in_pattern = false; + branch; + mux_in_pattern = true; +endcode + +// The multiplier is at the center of our pattern match mul select mul->type.in($mul) + // It has either two or three consumers depending on whether there's a mux + // in the pattern or not select nusers(port(mul, \Y)) <= 3 - set mul_nusers nusers(port(mul, \Y)) + filter nusers(port(mul, \Y)) == (mux_in_pattern ? 3 : 2) endmatch +code output_registered + output_registered = false; + branch; + output_registered = true; +endcode + match add select add->type.in($add, $sub) choice AB {\A, \B} define BA (AB == \A ? \B : \A) + // One input to the adder is fed by the multiplier index port(add, AB) === port(mul, \Y) - select nusers(port(add, \Y)) <= 3 - set add_nusers nusers(port(add, \Y)) + // Save the other input port, it needs to be fed by the flip-flop set add_ba BA + // Adder has either two or three consumers; it will have three consumers + // IFF there's no mux in the pattern and the multiplier-accumulator result + // is taken unregistered + filter nusers(port(add, \Y)) == (!mux_in_pattern && !output_registered ? 3 : 2) endmatch match mux + if mux_in_pattern select mux->type.in($mux) choice AB {\A, \B} define BA (AB == \A ? \B : \A) index port(mux, AB) === port(mul, \Y) index port(mux, BA) === port(add, \Y) - select nusers(port(mux, \Y)) <= 3 - set mux_nusers nusers(port(mux, \Y)) + filter nusers(port(mux, \Y)) == (output_registered ? 2 : 3) set mux_ab AB - optional endmatch match ff select ff->type.in($dff, $adff, $dffe, $adffe) - index port(ff, \D) === (mux == nullptr ? port(add, \Y) : port(mux, \Y)) + select param(ff, \CLK_POLARITY).as_bool() + index port(ff, \D) === mux_in_pattern ? port(mux, \Y) : port(add, \Y); index port(ff, \Q) === port(add, add_ba) - set ff_d_nusers nusers(port(ff, \D)) - set ff_q_nusers nusers(port(ff, \Q)) + filter nusers(port(ff, \Q)) == (output_registered ? 3 : 2) endmatch code From 6672b6c1b38bb1556a035c7459078806e935c5ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 9 Oct 2023 13:13:42 +0200 Subject: [PATCH 175/240] quicklogic: Move pp3 tests one level down --- Makefile | 2 +- tests/arch/quicklogic/{ => pp3}/add_sub.ys | 2 +- tests/arch/quicklogic/{ => pp3}/adffs.ys | 2 +- tests/arch/quicklogic/{ => pp3}/counter.ys | 2 +- tests/arch/quicklogic/{ => pp3}/dffs.ys | 2 +- tests/arch/quicklogic/{ => pp3}/fsm.ys | 2 +- tests/arch/quicklogic/{ => pp3}/latches.ys | 2 +- tests/arch/quicklogic/{ => pp3}/logic.ys | 2 +- tests/arch/quicklogic/{ => pp3}/mux.ys | 2 +- tests/arch/quicklogic/{ => pp3}/run-test.sh | 2 +- tests/arch/quicklogic/{ => pp3}/tribuf.ys | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) rename tests/arch/quicklogic/{ => pp3}/add_sub.ys (93%) rename tests/arch/quicklogic/{ => pp3}/adffs.ys (98%) rename tests/arch/quicklogic/{ => pp3}/counter.ys (95%) rename tests/arch/quicklogic/{ => pp3}/dffs.ys (97%) rename tests/arch/quicklogic/{ => pp3}/fsm.ys (96%) rename tests/arch/quicklogic/{ => pp3}/latches.ys (96%) rename tests/arch/quicklogic/{ => pp3}/logic.ys (94%) rename tests/arch/quicklogic/{ => pp3}/mux.ys (98%) rename tests/arch/quicklogic/{ => pp3}/run-test.sh (79%) rename tests/arch/quicklogic/{ => pp3}/tribuf.ys (93%) diff --git a/Makefile b/Makefile index b980bfdd211..f467330c894 100644 --- a/Makefile +++ b/Makefile @@ -880,7 +880,7 @@ endif +cd tests/arch/gowin && bash run-test.sh $(SEEDOPT) +cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT) +cd tests/arch/nexus && bash run-test.sh $(SEEDOPT) - +cd tests/arch/quicklogic && bash run-test.sh $(SEEDOPT) + +cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT) +cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh +cd tests/memfile && bash run-test.sh diff --git a/tests/arch/quicklogic/add_sub.ys b/tests/arch/quicklogic/pp3/add_sub.ys similarity index 93% rename from tests/arch/quicklogic/add_sub.ys rename to tests/arch/quicklogic/pp3/add_sub.ys index 47db42afc9a..c5e9fb29be8 100644 --- a/tests/arch/quicklogic/add_sub.ys +++ b/tests/arch/quicklogic/pp3/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog ../common/add_sub.v +read_verilog ../../common/add_sub.v hierarchy -top top equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/quicklogic/adffs.ys b/tests/arch/quicklogic/pp3/adffs.ys similarity index 98% rename from tests/arch/quicklogic/adffs.ys rename to tests/arch/quicklogic/pp3/adffs.ys index 43f36c20cb5..fb9f34df429 100644 --- a/tests/arch/quicklogic/adffs.ys +++ b/tests/arch/quicklogic/pp3/adffs.ys @@ -1,4 +1,4 @@ -read_verilog ../common/adffs.v +read_verilog ../../common/adffs.v design -save read hierarchy -top adff diff --git a/tests/arch/quicklogic/counter.ys b/tests/arch/quicklogic/pp3/counter.ys similarity index 95% rename from tests/arch/quicklogic/counter.ys rename to tests/arch/quicklogic/pp3/counter.ys index 9a7dcdf0809..5095cb8efe8 100644 --- a/tests/arch/quicklogic/counter.ys +++ b/tests/arch/quicklogic/pp3/counter.ys @@ -1,4 +1,4 @@ -read_verilog ../common/counter.v +read_verilog ../../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/quicklogic/dffs.ys b/tests/arch/quicklogic/pp3/dffs.ys similarity index 97% rename from tests/arch/quicklogic/dffs.ys rename to tests/arch/quicklogic/pp3/dffs.ys index 2bcfbf672de..f5023e48e14 100644 --- a/tests/arch/quicklogic/dffs.ys +++ b/tests/arch/quicklogic/pp3/dffs.ys @@ -1,4 +1,4 @@ -read_verilog ../common/dffs.v +read_verilog ../../common/dffs.v rename dff my_dff # Work around conflicting module names between test and vendor cells rename dffe my_dffe design -save read diff --git a/tests/arch/quicklogic/fsm.ys b/tests/arch/quicklogic/pp3/fsm.ys similarity index 96% rename from tests/arch/quicklogic/fsm.ys rename to tests/arch/quicklogic/pp3/fsm.ys index 50dcb71b142..418db8025bd 100644 --- a/tests/arch/quicklogic/fsm.ys +++ b/tests/arch/quicklogic/pp3/fsm.ys @@ -1,4 +1,4 @@ -read_verilog ../common/fsm.v +read_verilog ../../common/fsm.v hierarchy -top fsm proc flatten diff --git a/tests/arch/quicklogic/latches.ys b/tests/arch/quicklogic/pp3/latches.ys similarity index 96% rename from tests/arch/quicklogic/latches.ys rename to tests/arch/quicklogic/pp3/latches.ys index bcef429904b..90a4f515b75 100644 --- a/tests/arch/quicklogic/latches.ys +++ b/tests/arch/quicklogic/pp3/latches.ys @@ -1,4 +1,4 @@ -read_verilog ../common/latches.v +read_verilog ../../common/latches.v design -save read hierarchy -top latchp diff --git a/tests/arch/quicklogic/logic.ys b/tests/arch/quicklogic/pp3/logic.ys similarity index 94% rename from tests/arch/quicklogic/logic.ys rename to tests/arch/quicklogic/pp3/logic.ys index 9c34ddaeb3d..ecddda577d3 100644 --- a/tests/arch/quicklogic/logic.ys +++ b/tests/arch/quicklogic/pp3/logic.ys @@ -1,4 +1,4 @@ -read_verilog ../common/logic.v +read_verilog ../../common/logic.v hierarchy -top top proc equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check diff --git a/tests/arch/quicklogic/mux.ys b/tests/arch/quicklogic/pp3/mux.ys similarity index 98% rename from tests/arch/quicklogic/mux.ys rename to tests/arch/quicklogic/pp3/mux.ys index 5214bb7872d..a3b12a73d2a 100644 --- a/tests/arch/quicklogic/mux.ys +++ b/tests/arch/quicklogic/pp3/mux.ys @@ -1,4 +1,4 @@ -read_verilog ../common/mux.v +read_verilog ../../common/mux.v design -save read hierarchy -top mux2 diff --git a/tests/arch/quicklogic/run-test.sh b/tests/arch/quicklogic/pp3/run-test.sh similarity index 79% rename from tests/arch/quicklogic/run-test.sh rename to tests/arch/quicklogic/pp3/run-test.sh index 4be4b70ae17..3f8515f9aa6 100755 --- a/tests/arch/quicklogic/run-test.sh +++ b/tests/arch/quicklogic/pp3/run-test.sh @@ -1,4 +1,4 @@ #!/usr/bin/env bash set -eu -source ../../gen-tests-makefile.sh +source ../../../gen-tests-makefile.sh run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'" diff --git a/tests/arch/quicklogic/tribuf.ys b/tests/arch/quicklogic/pp3/tribuf.ys similarity index 93% rename from tests/arch/quicklogic/tribuf.ys rename to tests/arch/quicklogic/pp3/tribuf.ys index d74fbbcdd2a..f68a0d7790e 100644 --- a/tests/arch/quicklogic/tribuf.ys +++ b/tests/arch/quicklogic/pp3/tribuf.ys @@ -1,4 +1,4 @@ -read_verilog ../common/tribuf.v +read_verilog ../../common/tribuf.v hierarchy -top tristate proc tribuf From e19833f8c78846fc30f581259d06d2e34ff9fd86 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 9 Oct 2023 13:18:09 +0200 Subject: [PATCH 176/240] synth_quiclogic: Fix conditioning of bram passes --- techlibs/quicklogic/synth_quicklogic.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 101dff66597..9bfaa191e93 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -245,16 +245,15 @@ struct SynthQuickLogicPass : public ScriptPass { run("opt_clean"); } - if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)")) { - if(family == "qlf_k6n10f" || help_mode) + if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)") + && (family == "qlf_k6n10f" || help_mode)) { run("memory_libmap -lib " + lib_path + family + "/libmap_brams.txt"); run("ql_bram_merge"); run("techmap -map " + lib_path + family + "/libmap_brams_map.v"); run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); - if (bramTypes || help_mode) { + if (bramTypes || help_mode) run("ql_bram_types", "(if -bramtypes)"); - } } if (check_label("map_ffram")) { From 554d8caef7e42e074f825d648adf3c7fd1a32f5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 12:14:48 +0100 Subject: [PATCH 177/240] quicklogic: Add basic k6n10f tests --- Makefile | 1 + tests/arch/quicklogic/qlf_k6n10f/add_sub.ys | 8 ++++ tests/arch/quicklogic/qlf_k6n10f/adffs.ys | 48 ++++++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/counter.ys | 12 +++++ tests/arch/quicklogic/qlf_k6n10f/dffs.ys | 21 +++++++++ tests/arch/quicklogic/qlf_k6n10f/fsm.ys | 17 +++++++ tests/arch/quicklogic/qlf_k6n10f/latches.ys | 29 ++++++++++++ tests/arch/quicklogic/qlf_k6n10f/logic.ys | 10 ++++ tests/arch/quicklogic/qlf_k6n10f/mux.ys | 40 ++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/run-test.sh | 4 ++ 10 files changed, 190 insertions(+) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/add_sub.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/adffs.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/counter.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/dffs.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/fsm.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/latches.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/logic.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/mux.ys create mode 100755 tests/arch/quicklogic/qlf_k6n10f/run-test.sh diff --git a/Makefile b/Makefile index f467330c894..c3d3f57eac8 100644 --- a/Makefile +++ b/Makefile @@ -881,6 +881,7 @@ endif +cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT) +cd tests/arch/nexus && bash run-test.sh $(SEEDOPT) +cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT) + +cd tests/arch/quicklogic/qlf_k6n10f && bash run-test.sh $(SEEDOPT) +cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh +cd tests/memfile && bash run-test.sh diff --git a/tests/arch/quicklogic/qlf_k6n10f/add_sub.ys b/tests/arch/quicklogic/qlf_k6n10f/add_sub.ys new file mode 100644 index 00000000000..30d9bbc9dc3 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog ../../common/add_sub.v +hierarchy -top top +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 9 t:$lut # OOT flow has 8 +select -assert-count 8 t:adder_carry +select -assert-none t:$lut t:adder_carry %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/adffs.ys b/tests/arch/quicklogic/qlf_k6n10f/adffs.ys new file mode 100644 index 00000000000..475355d2bd0 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/adffs.ys @@ -0,0 +1,48 @@ +read_verilog ../../common/adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:$lut r:WIDTH=1 %i +select -assert-none r:WIDTH>1 +select -assert-count 1 t:dffsre + +select -assert-none t:$lut t:dffsre %% t:* %D + + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:dffsre + +select -assert-none t:dffsre %% t:* %D + + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:$lut r:WIDTH=1 %i +select -assert-none r:WIDTH>1 +select -assert-count 1 t:sdffsre + +select -assert-none t:$lut t:sdffsre %% t:* %D + + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:sdffnsre + +select -assert-none t:sdffnsre %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/counter.ys b/tests/arch/quicklogic/qlf_k6n10f/counter.ys new file mode 100644 index 00000000000..ebb6ce243eb --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/counter.ys @@ -0,0 +1,12 @@ +read_verilog ../../common/counter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -multiclock -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:$lut +select -assert-count 8 t:adder_carry +select -assert-count 8 t:dffsre + +select -assert-none t:$lut t:adder_carry t:dffsre %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/dffs.ys b/tests/arch/quicklogic/qlf_k6n10f/dffs.ys new file mode 100644 index 00000000000..a4a159f1b09 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/dffs.ys @@ -0,0 +1,21 @@ +read_verilog ../../common/dffs.v +rename dff my_dff # Work around conflicting module names between test and vendor cells +rename dffe my_dffe +design -save read + +hierarchy -top my_dff +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:sdffsre +select -assert-none t:sdffsre %% t:* %D + +design -load read +hierarchy -top my_dffe +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:sdffsre +select -assert-none t:sdffsre %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/fsm.ys b/tests/arch/quicklogic/qlf_k6n10f/fsm.ys new file mode 100644 index 00000000000..e7a9d962d6e --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/fsm.ys @@ -0,0 +1,17 @@ +read_verilog ../../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f +async2sync +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 9 t:$lut +select -assert-count 6 t:sdffsre + +select -assert-none t:$lut t:sdffsre %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/latches.ys b/tests/arch/quicklogic/qlf_k6n10f/latches.ys new file mode 100644 index 00000000000..59574a1fb77 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/latches.ys @@ -0,0 +1,29 @@ +read_verilog ../../common/latches.v +design -save read + +hierarchy -top latchp +proc +equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f +design -load postopt +cd latchp +select -assert-count 1 t:latchsre +select -assert-none t:latchsre %% t:* %D + +design -load read +hierarchy -top latchn +proc +equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f +design -load postopt +cd latchn +select -assert-count 1 t:latchnsre +select -assert-none t:latchnsre %% t:* %D + +design -load read +hierarchy -top latchsr +proc +equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f +design -load postopt +cd latchsr +select -assert-count 2 t:$lut +select -assert-count 1 t:latchnsre +select -assert-none t:$lut t:latchnsre %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/logic.ys b/tests/arch/quicklogic/qlf_k6n10f/logic.ys new file mode 100644 index 00000000000..a24d5a479f6 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/logic.ys @@ -0,0 +1,10 @@ +read_verilog ../../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:$lut + +select -assert-none t:$lut %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/mux.ys b/tests/arch/quicklogic/qlf_k6n10f/mux.ys new file mode 100644 index 00000000000..633b5fc8656 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/mux.ys @@ -0,0 +1,40 @@ +read_verilog ../../common/mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:$lut r:WIDTH=3 %i +select -assert-none t:$lut r:WIDTH=3 %i %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:$lut r:WIDTH=6 %i +select -assert-none t:$lut r:WIDTH=6 %i %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 2 t:$lut r:WIDTH=6 %i +select -assert-count 1 t:$lut r:WIDTH=3 %i +select -assert-none t:$lut r:WIDTH=6 r:WIDTH=3 %u %i %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-max 5 t:$lut r:WIDTH=6 %i # OOT flow does 2 +select -assert-max 1 t:$lut r:WIDTH=3 %i # and here 1 +select -assert-max 1 t:$lut r:WIDTH=4 r:WIDTH=5 %u %i +select -assert-none t:$lut r:WIDTH>2 %i %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/run-test.sh b/tests/arch/quicklogic/qlf_k6n10f/run-test.sh new file mode 100755 index 00000000000..36689eddedc --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/run-test.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -eu +source ../../../gen-tests-makefile.sh +run_tests --yosys-scripts --bash From 532aca28ab9e5fbe245a4bb943e0b2e88c0015aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 14:21:59 +0100 Subject: [PATCH 178/240] quicklogic: Drop `blackbox` off `adder_carry` --- techlibs/quicklogic/qlf_k6n10f/cells_sim.v | 1 - 1 file changed, 1 deletion(-) diff --git a/techlibs/quicklogic/qlf_k6n10f/cells_sim.v b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v index b9f40625646..ddfd51ee7ce 100644 --- a/techlibs/quicklogic/qlf_k6n10f/cells_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v @@ -121,7 +121,6 @@ module sh_dff( endmodule (* abc9_box, lib_whitebox *) -(* blackbox *) (* keep *) module adder_carry( output wire sumout, From dad85b5178133cbadd25dbf52ddb95ae033acca4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 14:22:28 +0100 Subject: [PATCH 179/240] synth_quicklogic: Fix missing FF mapping --- techlibs/quicklogic/synth_quicklogic.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 9bfaa191e93..0e7aaa75276 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -282,6 +282,7 @@ struct SynthQuickLogicPass : public ScriptPass { run("shregmap -minlen -maxlen ", "(for qlf_k6n10f)"); run("dfflegalize -cell "); run("techmap -map " + lib_path + family + "/cells_map.v", "(for pp3)"); + run("techmap -map " + lib_path + family + "/ffs_map.v", "(for ql_k6n10f)"); } if (family == "pp3") { run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x"); @@ -293,6 +294,7 @@ struct SynthQuickLogicPass : public ScriptPass { // not in the allowed set. As a workaround we put them in the allowed // set explicitly and map them later to $_DLATCHSR_[NP]NN_. run("dfflegalize -cell $_DFFSRE_?NNP_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0" " -cell $_SDFFE_?N?P_ 0"); + run("techmap -map " + lib_path + family + "/ffs_map.v"); } run("opt"); } From db9e5b4f14959ef4b1883a1909b0fcfa7c2cd098 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 17:27:35 +0100 Subject: [PATCH 180/240] quicklogic: Fix `dffs.ys` test --- tests/arch/quicklogic/qlf_k6n10f/dffs.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/dffs.ys b/tests/arch/quicklogic/qlf_k6n10f/dffs.ys index a4a159f1b09..79a16c9412b 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/dffs.ys +++ b/tests/arch/quicklogic/qlf_k6n10f/dffs.ys @@ -7,7 +7,7 @@ hierarchy -top my_dff proc equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dff # Constrain all select calls below inside the top module +cd my_dff # Constrain all select calls below inside the top module select -assert-count 1 t:sdffsre select -assert-none t:sdffsre %% t:* %D @@ -16,6 +16,6 @@ hierarchy -top my_dffe proc equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffe # Constrain all select calls below inside the top module +cd my_dffe # Constrain all select calls below inside the top module select -assert-count 1 t:sdffsre select -assert-none t:sdffsre %% t:* %D From b30544d61d575658cff664d7ffbd52f8d7be7c2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 17:17:03 +0100 Subject: [PATCH 181/240] ql_dsp_io_regs: Fix ID strings, constant detection --- techlibs/quicklogic/ql_dsp_io_regs.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/techlibs/quicklogic/ql_dsp_io_regs.cc b/techlibs/quicklogic/ql_dsp_io_regs.cc index efb1ad4d5f3..523c86e7341 100644 --- a/techlibs/quicklogic/ql_dsp_io_regs.cc +++ b/techlibs/quicklogic/ql_dsp_io_regs.cc @@ -30,9 +30,9 @@ PRIVATE_NAMESPACE_BEGIN // ============================================================================ struct QlDspIORegs : public Pass { - const std::vector ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b", - "saturate_enable", "shift_right", "round"}; - const std::vector ports2del_mult_acc = {"acc_fir", "dly_b"}; + const std::vector ports2del_mult = {ID(load_acc), ID(subtract), ID(acc_fir), ID(dly_b), + ID(saturate_enable), ID(shift_right), ID(round)}; + const std::vector ports2del_mult_acc = {ID(acc_fir), ID(dly_b)}; SigMap sigmap; @@ -80,7 +80,7 @@ struct QlDspIORegs : public Pass { // Get DSP configuration for (auto cfg_port : {ID(register_inputs), ID(output_select)}) - if (!cell->hasPort(cfg_port) || sigmap(cell->getPort(cfg_port)).is_fully_const()) + if (!cell->hasPort(cfg_port) || !sigmap(cell->getPort(cfg_port)).is_fully_const()) log_error("Missing or non-constant '%s' port on DSP cell %s\n", log_id(cfg_port), log_id(cell)); int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int(); @@ -97,7 +97,7 @@ struct QlDspIORegs : public Pass { log_error("Unexpected feedback configuration on %s\n", log_id(cell)); // Build new type name - std::string new_type = "QL_DSP2_MULT"; + std::string new_type = "\\QL_DSP2_MULT"; // Decide if we should be deleting the clock port bool del_clk = true; From a5c8d246f7d618893bacadc516d07ac9df50f448 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 17:18:33 +0100 Subject: [PATCH 182/240] quicklogic: Add k6n10f DSP test --- tests/arch/quicklogic/qlf_k6n10f/dsp.ys | 120 ++++++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/dsp.ys diff --git a/tests/arch/quicklogic/qlf_k6n10f/dsp.ys b/tests/arch/quicklogic/qlf_k6n10f/dsp.ys new file mode 100644 index 00000000000..023ff0d89f6 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/dsp.ys @@ -0,0 +1,120 @@ +read_verilog < 0) + assert(y == y_expected); + i <= i + 1; + end +end +endmodule +EOF +read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v +hierarchy -top testbench +proc +sim -assert -q -clock clk -n 20 From b602c0858f4da092a072b53e84a910c3ee419d1e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 17:31:46 +0100 Subject: [PATCH 183/240] quicklogic: Set initial values on inferred TDP36K --- .../quicklogic/qlf_k6n10f/libmap_brams_map.v | 29 +++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v index 20638c4f9af..f4f4420c1a2 100644 --- a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v @@ -75,6 +75,18 @@ default: mode = 3'b000; endcase endfunction +function [36863:0] pack_init; + integer i; + reg [35:0] ri; + for (i = 0; i < (OPTION_SPLIT ? 512 : 1024); i = i + 1) begin + ri = INIT[i*36 +: 36]; + pack_init[i*36 +: 36] = {ri[35], ri[26], ri[34:27], ri[25:18], + ri[17], ri[8], ri[16:9], ri[7:0]}; + end + if (OPTION_SPLIT) + pack_init[36863:18432] = 18432'bx; +endfunction + wire REN_A1_i; wire REN_A2_i; @@ -168,7 +180,9 @@ defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, (* is_split = 0 *) (* port_a_width = PORT_A_WIDTH *) (* port_b_width = PORT_B_WIDTH *) -TDP36K _TECHMAP_REPLACE_ ( +TDP36K #( + .RAM_INIT(pack_init()), +) _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .CLK_A1_i(PORT_A_CLK), @@ -290,6 +304,15 @@ default: mode = 3'b000; endcase endfunction +function [36863:0] pack_init; + integer i; + reg [35:0] ri; + for (i = 0; i < 1024; i = i + 1) begin + ri = {INIT2[i*18 +: 18], INIT1[i*18 +: 18]}; + pack_init[i*36 +: 36] = {ri[35], ri[26], ri[34:27], ri[25:18], ri[17], ri[8], ri[16:9], ri[7:0]}; + end +endfunction + wire REN_A1_i; wire REN_A2_i; @@ -418,7 +441,9 @@ defparam _TECHMAP_REPLACE_.MODE_BITS = {1'b1, (* port_a2_width = PORT_A2_WIDTH *) (* port_b1_width = PORT_B1_WIDTH *) (* port_b2_width = PORT_B2_WIDTH *) -TDP36K _TECHMAP_REPLACE_ ( +TDP36K #( + .RAM_INIT(pack_init()), +) _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(WDATA_A1_i), .WDATA_A2_i(WDATA_A2_i), From 4903f99f85a9392418c03796d251391f83182276 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 29 Nov 2023 11:04:34 +0100 Subject: [PATCH 184/240] quicklogic: Add missing `RAM_INIT` param on TDP36K sim model --- techlibs/quicklogic/qlf_k6n10f/brams_sim.v | 160 ++------------------- 1 file changed, 14 insertions(+), 146 deletions(-) diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_sim.v b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v index 5f04c0e7fac..de6d992335a 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v @@ -81,150 +81,7 @@ module TDP36K ( // Split (1 bit) localparam [ 0:0] SPLIT_i = MODE_BITS[80]; - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; input wire RESET_ni; input wire WEN_A1_i; @@ -261,6 +118,15 @@ module TDP36K ( output reg [17:0] RDATA_A2_o; output reg [17:0] RDATA_B2_o; input wire FLUSH2_i; + + function [18431:0] split_init; + input index; + integer i; + for (i = 0; i < 1024; i = i + 1) begin + split_init[i * 18 +: 18] = RAM_INIT[i * 36 + index * 18 +: 18]; + end + endfunction + wire EMPTY2; wire EPO2; wire EWM2; @@ -605,7 +471,8 @@ module TDP36K ( .SYNC_FIFO_i(SYNC_FIFO1_i), .POWERDN_i(POWERDN1_i), .SLEEP_i(SLEEP1_i), - .PROTECT_i(PROTECT1_i) + .PROTECT_i(PROTECT1_i), + .INIT_i(split_init(0)) )u1( .RMODE_A_i(ram_rmode_a1), .RMODE_B_i(ram_rmode_b1), @@ -642,7 +509,8 @@ module TDP36K ( .SYNC_FIFO_i(SYNC_FIFO2_i), .POWERDN_i(POWERDN2_i), .SLEEP_i(SLEEP2_i), - .PROTECT_i(PROTECT2_i) + .PROTECT_i(PROTECT2_i), + .INIT_i(split_init(1)) )u2( .RMODE_A_i(ram_rmode_a2), .RMODE_B_i(ram_rmode_b2), From e0a6a01ecb897f39045b12b2135a998ac440b061 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 30 Nov 2023 10:41:55 +0100 Subject: [PATCH 185/240] quicklogic: Add `RAM_INIT` to specialized BRAM models --- techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py b/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py index 5f7da90977e..e57c04a0887 100644 --- a/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py +++ b/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py @@ -31,6 +31,7 @@ def generate(filename): ); parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; input wire RESET_ni; input wire WEN_A1_i, WEN_B1_i; @@ -61,7 +62,7 @@ def generate(filename): input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( .RESET_ni (RESET_ni), .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), @@ -148,6 +149,7 @@ def generate(filename): ); parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; input wire RESET_ni; input wire WEN_A1_i, WEN_B1_i; @@ -178,7 +180,7 @@ def generate(filename): input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( .RESET_ni (RESET_ni), .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), From 991850e1c9de77a1788c886d89106bd0769ae5c7 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 29 Nov 2023 16:48:20 +1300 Subject: [PATCH 186/240] quicklogic: Initial blockram tests Use python script to generate tests for both SDP and TDP across multiple sizes of RAM. Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively. --- tests/arch/common/blockram.v | 51 +++++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/.gitignore | 1 + .../quicklogic/qlf_k6n10f/gen_memories.py | 51 +++++++++++++++++++ 3 files changed, 103 insertions(+) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/.gitignore create mode 100644 tests/arch/quicklogic/qlf_k6n10f/gen_memories.py diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index c06ac96d5bc..d2b2dae56ea 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -45,6 +45,57 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sdp +module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // wd=16, wa=9 + (input wire clk, write_enable, + input wire [(DATA_WIDTH*2)-1:0] data_in, + input wire [ADDRESS_WIDTH-2:0] address_in_w, + input wire [ADDRESS_WIDTH-1:0] address_in_r, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = ((DATA_WIDTH*2)-1); + localparam DEPTH = (2**(ADDRESS_WIDTH-1)-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) begin + memory[address_in_w] <= data_in; + end + data_out_r <= memory[address_in_r>>1]; + end + + assign data_out = address_in_r[0] ? data_out_r[WORD:DATA_WIDTH] : data_out_r[DATA_WIDTH-1:0]; + +endmodule // sync_ram_sdp_wwr + + +module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // rd=16, ra=9 + (input wire clk, write_enable, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in_w, + input wire [ADDRESS_WIDTH-2:0] address_in_r, + output wire [(DATA_WIDTH*1)-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r0; + reg [WORD:0] data_out_r1; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in_w] <= data_in; + data_out_r0 <= memory[address_in_r<<1+0]; + data_out_r1 <= memory[address_in_r<<1+1]; + end + + assign data_out = {data_out_r0, data_out_r1}; + +endmodule // sync_ram_sdp_wrr + + module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) (input wire clk_a, clk_b, input wire write_enable_a, write_enable_b, diff --git a/tests/arch/quicklogic/qlf_k6n10f/.gitignore b/tests/arch/quicklogic/qlf_k6n10f/.gitignore new file mode 100644 index 00000000000..fb232f235f3 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/.gitignore @@ -0,0 +1 @@ +t_*.ys diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py new file mode 100644 index 00000000000..d0eb22a475f --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -0,0 +1,51 @@ +blockram_template = """\ +design -reset; read_verilog -defer ../../common/blockram.v +chparam -set ADDRESS_WIDTH {aw} -set DATA_WIDTH {dw} {top} +hierarchy -top {top} +synth_quicklogic -family qlf_k6n10f -top {top}; cd {top} +log TESTING aw:{aw} dw:{dw} top:{top}\ +""" +blockram_tests: "list[tuple[int, int, str, list[str]]]" = [ + # TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work + (10, 36, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (11, 18, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (12, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + # larger sizes need an extra ram + (10, 48, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + (11, 36, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + (12, 18, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + (12, 10, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + # 4096x20bit *can* fit in 3, albeit somewhat awkwardly + (12, 20, "sync_ram_*dp", ["-assert-min 3 t:TDP36K", + "-assert-max 4 t:TDP36K"]), + # smaller sizes can still fit in one + (10, 32, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (10, 18, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (10, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (11, 16, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (11, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (12, 8, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (13, 4, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (14, 2, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (15, 1, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + # 2x write width (1024x36bit write / 2048x18bit read = 1TDP36K) + (11, 18, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), + (11, 9, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), + # 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K) + (11, 18, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + (10, 36, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), +] + +with open("t_mem.ys", mode="w") as f: + for (aw, dw, top, assertions) in blockram_tests: + if "*" in top: + star_sub = ["s", "t"] + else: + star_sub = [""] + for sub in star_sub: + print( + blockram_template.format(aw=aw, dw=dw, top=top.replace("*", sub)), + file=f + ) + for assertion in assertions: + print("select {}\n".format(assertion), file=f, end=None) From 8d3b238b9b90f61e505025cecba29ac0e18e3ec7 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 29 Nov 2023 17:34:22 +1300 Subject: [PATCH 187/240] quicklogic: Testing split TDP36K Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories. Refactor python blockram template to take a list of params to support the above. Also change the smaller single TDP36K tests to also test `port_a_width` value. --- tests/arch/common/blockram.v | 40 +++++++++ .../quicklogic/qlf_k6n10f/gen_memories.py | 83 ++++++++++++------- 2 files changed, 93 insertions(+), 30 deletions(-) diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index d2b2dae56ea..c37074382b2 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -96,6 +96,46 @@ module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // rd=16, ra endmodule // sync_ram_sdp_wrr +module double_sync_ram_sdp #(parameter DATA_WIDTH_A=8, ADDRESS_WIDTH_A=10, DATA_WIDTH_B=8, ADDRESS_WIDTH_B=10) +( + input wire write_enable_a, clk_a, + input wire [DATA_WIDTH_A-1:0] data_in_a, + input wire [ADDRESS_WIDTH_A-1:0] address_in_r_a, address_in_w_a, + output wire [DATA_WIDTH_A-1:0] data_out_a, + + input wire write_enable_b, clk_b, + input wire [DATA_WIDTH_B-1:0] data_in_b, + input wire [ADDRESS_WIDTH_B-1:0] address_in_r_b, address_in_w_b, + output wire [DATA_WIDTH_B-1:0] data_out_b +); + + sync_ram_sdp #( + .DATA_WIDTH(DATA_WIDTH_A), + .ADDRESS_WIDTH(ADDRESS_WIDTH_A) + ) a_ram ( + .write_enable(write_enable_a), + .clk(clk_a), + .data_in(data_in_a), + .address_in_r(address_in_r_a), + .address_in_w(address_in_w_a), + .data_out(data_out_a) + ); + + sync_ram_sdp #( + .DATA_WIDTH(DATA_WIDTH_B), + .ADDRESS_WIDTH(ADDRESS_WIDTH_B) + ) b_ram ( + .write_enable(write_enable_b), + .clk(clk_b), + .data_in(data_in_b), + .address_in_r(address_in_r_b), + .address_in_w(address_in_w_b), + .data_out(data_out_b) + ); + +endmodule // double_sync_ram_sdp + + module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) (input wire clk_a, clk_b, input wire write_enable_a, write_enable_b, diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index d0eb22a475f..54f29125b45 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -1,51 +1,74 @@ -blockram_template = """\ +blockram_template = """# ====================================== design -reset; read_verilog -defer ../../common/blockram.v -chparam -set ADDRESS_WIDTH {aw} -set DATA_WIDTH {dw} {top} +chparam{param_str} {top} hierarchy -top {top} synth_quicklogic -family qlf_k6n10f -top {top}; cd {top} -log TESTING aw:{aw} dw:{dw} top:{top}\ +log ** TESTING {top} WITH PARAMS{param_str}\ """ -blockram_tests: "list[tuple[int, int, str, list[str]]]" = [ +blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [ # TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work - (10, 36, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (11, 18, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (12, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), # larger sizes need an extra ram - (10, 48, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), - (11, 36, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), - (12, 18, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), - (12, 10, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 48)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 10)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), # 4096x20bit *can* fit in 3, albeit somewhat awkwardly - (12, 20, "sync_ram_*dp", ["-assert-min 3 t:TDP36K", - "-assert-max 4 t:TDP36K"]), - # smaller sizes can still fit in one - (10, 32, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (10, 18, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (10, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (11, 16, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (11, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (12, 8, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (13, 4, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (14, 2, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (15, 1, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 20)], "sync_ram_*dp", ["-assert-min 3 t:TDP36K", + "-assert-max 4 t:TDP36K"]), + + # smaller sizes can still fit in one, and assign the correct width (1, 2, 4, 8, 18 or 36) + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 32)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 24)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]), + ([("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 4)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=4 %i"]), + ([("ADDRESS_WIDTH", 14), ("DATA_WIDTH", 2)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=2 %i"]), + ([("ADDRESS_WIDTH", 15), ("DATA_WIDTH", 1)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=1 %i"]), + # 2x write width (1024x36bit write / 2048x18bit read = 1TDP36K) - (11, 18, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - (11, 9, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), # 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K) - (11, 18, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - (10, 36, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + + # two disjoint 18K memories can share a single TDP36K + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), + ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16), + ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 14), ("DATA_WIDTH_A", 1), + ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]), + # but only if data width is <= 18 + ([("ADDRESS_WIDTH_A", 9), ("DATA_WIDTH_A", 36), + ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 9)], "double_sync_ram_sdp", ["-assert-count 2 t:TDP36K"]), + # sharing a TDP36K sets is_split=1 + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), + ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]), + # an unshared TDP36K sets is_split=0 + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), ] with open("t_mem.ys", mode="w") as f: - for (aw, dw, top, assertions) in blockram_tests: + for (params, top, assertions) in blockram_tests: + param_str = "" + for (key, val) in params: + param_str += f" -set {key} {val}" if "*" in top: star_sub = ["s", "t"] else: star_sub = [""] for sub in star_sub: print( - blockram_template.format(aw=aw, dw=dw, top=top.replace("*", sub)), + blockram_template.format(param_str=param_str, top=top.replace("*", sub)), file=f ) for assertion in assertions: - print("select {}\n".format(assertion), file=f, end=None) + print("select {}".format(assertion), file=f) + print("", file=f) From 7513bfcbfe73f5ef99ab416d10d58f5395edab88 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 30 Nov 2023 09:16:12 +1300 Subject: [PATCH 188/240] quicklogic: fix double width read --- tests/arch/common/blockram.v | 49 +++++++++++-------- .../quicklogic/qlf_k6n10f/gen_memories.py | 2 +- 2 files changed, 29 insertions(+), 22 deletions(-) diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index c37074382b2..43a6864d2a3 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -71,27 +71,34 @@ endmodule // sync_ram_sdp_wwr module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // rd=16, ra=9 - (input wire clk, write_enable, - input wire [DATA_WIDTH-1:0] data_in, - input wire [ADDRESS_WIDTH-1:0] address_in_w, - input wire [ADDRESS_WIDTH-2:0] address_in_r, - output wire [(DATA_WIDTH*1)-1:0] data_out); - - localparam WORD = (DATA_WIDTH-1); - localparam DEPTH = (2**ADDRESS_WIDTH-1); - - reg [WORD:0] data_out_r0; - reg [WORD:0] data_out_r1; - reg [WORD:0] memory [0:DEPTH]; - - always @(posedge clk) begin - if (write_enable) - memory[address_in_w] <= data_in; - data_out_r0 <= memory[address_in_r<<1+0]; - data_out_r1 <= memory[address_in_r<<1+1]; - end - - assign data_out = {data_out_r0, data_out_r1}; +( + input wire clk_w, clk_r, write_enable, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in_w, + input wire [ADDRESS_WIDTH_R-1:0] address_in_r, + output wire [WORD-1:0] data_out +); + localparam ADDRESS_WIDTH_R = ADDRESS_WIDTH-1; + localparam HWORD = DATA_WIDTH; + localparam WORD = 2*DATA_WIDTH; + localparam DEPTH = 2**ADDRESS_WIDTH_R; + + reg [WORD-1:0] data_out_r; + reg [WORD-1:0] memory [0:DEPTH-1]; + + always @(posedge clk_w) begin + if (write_enable) + if (address_in_w[0]) // upper HWORD + memory[address_in_w>>1][WORD-1:HWORD] <= data_in; + else // lower HWORD + memory[address_in_w>>1][HWORD-1:0] <= data_in; + end + + always @(posedge clk_r) begin + data_out_r <= memory[address_in_r]; + end + + assign data_out = data_out_r; endmodule // sync_ram_sdp_wrr diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index 54f29125b45..e4becb77dfc 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -36,7 +36,7 @@ ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), # 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K) ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), # two disjoint 18K memories can share a single TDP36K ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), From 1a843b2a86a8829a9d1dea94e76f8dd2731be2f7 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 30 Nov 2023 11:17:24 +1300 Subject: [PATCH 189/240] quicklogic: testing 1:4 assymetric memory --- tests/arch/common/blockram.v | 74 ++++++++++++------- .../quicklogic/qlf_k6n10f/gen_memories.py | 46 ++++++++++-- 2 files changed, 88 insertions(+), 32 deletions(-) diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index 43a6864d2a3..c7e5aca052d 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -45,57 +45,77 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sdp -module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // wd=16, wa=9 - (input wire clk, write_enable, - input wire [(DATA_WIDTH*2)-1:0] data_in, - input wire [ADDRESS_WIDTH-2:0] address_in_w, - input wire [ADDRESS_WIDTH-1:0] address_in_r, - output wire [DATA_WIDTH-1:0] data_out); +module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, WRITE_SHIFT=1) // wd=16, wa=9 +( + input wire clk_w, clk_r, write_enable, + input wire [WORD-1:0] data_in, + input wire [ADDRESS_WIDTH_W-1:0] address_in_w, + input wire [ADDRESS_WIDTH-1:0] address_in_r, + output wire [DATA_WIDTH-1:0] data_out +); - localparam WORD = ((DATA_WIDTH*2)-1); - localparam DEPTH = (2**(ADDRESS_WIDTH-1)-1); + localparam ADDRESS_WIDTH_W = ADDRESS_WIDTH-WRITE_SHIFT; + localparam BYTE = DATA_WIDTH; + localparam WORD = DATA_WIDTH<>1]; - end + always @(posedge clk_w) begin + if (write_enable) + memory[address_in_w] <= data_in; + end + + always @(posedge clk_r) begin + data_out_r <= memory[address_in_r>>WRITE_SHIFT]; + end - assign data_out = address_in_r[0] ? data_out_r[WORD:DATA_WIDTH] : data_out_r[DATA_WIDTH-1:0]; + wire [WRITE_SHIFT-1:0] inner_address; + assign inner_address = address_in_r[WRITE_SHIFT-1:0]; + genvar i; + generate + for (i=0; i>READ_SHIFT; + assign inner_address = address_in_w[READ_SHIFT-1:0]; + always @(posedge clk_w) begin if (write_enable) - if (address_in_w[0]) // upper HWORD - memory[address_in_w>>1][WORD-1:HWORD] <= data_in; - else // lower HWORD - memory[address_in_w>>1][HWORD-1:0] <= data_in; + for (i=0; i Date: Thu, 30 Nov 2023 11:41:41 +1300 Subject: [PATCH 190/240] quicklogic: testing port widths on split rams --- .../arch/quicklogic/qlf_k6n10f/gen_memories.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index 7dcf2bc8947..3b23254a7c7 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -84,11 +84,29 @@ # but only if data width is <= 18 ([("ADDRESS_WIDTH_A", 9), ("DATA_WIDTH_A", 36), ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 9)], "double_sync_ram_sdp", ["-assert-count 2 t:TDP36K"]), + # sharing a TDP36K sets is_split=1 ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]), # an unshared TDP36K sets is_split=0 ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), + + # sharing a TDP36K sets correct port widths + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("DATA_WIDTH_B", 18), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=18 %i", + "-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16), ("DATA_WIDTH_B", 8), ("ADDRESS_WIDTH_B", 11)], "double_sync_ram_sdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=9 %i " + + "t:TDP36K a:port_a2_width=18 %i a:port_a1_width=9 %i %u", + "-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 12), ("DATA_WIDTH_A", 4), ("DATA_WIDTH_B", 12), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=4 %i a:port_a2_width=18 %i " + + "t:TDP36K a:port_a2_width=4 %i a:port_a1_width=18 %i %u", + "-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 13), ("DATA_WIDTH_A", 2), ("DATA_WIDTH_B", 1), ("ADDRESS_WIDTH_B", 14)], "double_sync_ram_sdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=2 %i a:port_a2_width=1 %i " + + "t:TDP36K a:port_a2_width=2 %i a:port_a1_width=1 %i %u", + "-assert-count 1 t:TDP36K"]), ] with open("t_mem.ys", mode="w") as f: From 8ded7020f46113a0a7a27441029e19df411ec940 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 30 Nov 2023 12:36:21 +1300 Subject: [PATCH 191/240] tests: asymmetric sync rams now correctly asymmetric Also both use the same named parameters for better mirroring. --- tests/arch/common/blockram.v | 57 +++++++++++++++--------------------- 1 file changed, 23 insertions(+), 34 deletions(-) diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index c7e5aca052d..09bc7786346 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -45,7 +45,7 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sdp -module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, WRITE_SHIFT=1) // wd=16, wa=9 +module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, SHIFT_VAL=1) // wd=16, wa=9 ( input wire clk_w, clk_r, write_enable, input wire [WORD-1:0] data_in, @@ -54,36 +54,32 @@ module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, WRITE_SHIFT= output wire [DATA_WIDTH-1:0] data_out ); - localparam ADDRESS_WIDTH_W = ADDRESS_WIDTH-WRITE_SHIFT; + localparam ADDRESS_WIDTH_W = ADDRESS_WIDTH-SHIFT_VAL; localparam BYTE = DATA_WIDTH; - localparam WORD = DATA_WIDTH<>WRITE_SHIFT]; + data_out_r <= memory[address_in_r]; end - wire [WRITE_SHIFT-1:0] inner_address; - assign inner_address = address_in_r[WRITE_SHIFT-1:0]; - genvar i; - generate - for (i=0; i>READ_SHIFT; - assign inner_address = address_in_w[READ_SHIFT-1:0]; + reg [BYTE-1:0] memory [0:DEPTH-1]; always @(posedge clk_w) begin - if (write_enable) - for (i=0; i Date: Thu, 30 Nov 2023 12:41:03 +1300 Subject: [PATCH 192/240] quicklogic: wildcard asymmetric memory tests --- .../quicklogic/qlf_k6n10f/gen_memories.py | 89 +++++++++---------- 1 file changed, 40 insertions(+), 49 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index 3b23254a7c7..353843b7898 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -31,48 +31,35 @@ ([("ADDRESS_WIDTH", 14), ("DATA_WIDTH", 2)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=2 %i"]), ([("ADDRESS_WIDTH", 15), ("DATA_WIDTH", 1)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=1 %i"]), - # 2x write width (1024x36bit write / 2048x18bit read = 1TDP36K) - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("WRITE_SHIFT", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("WRITE_SHIFT", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ("WRITE_SHIFT", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("WRITE_SHIFT", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - # same for read - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ( "READ_SHIFT", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ( "READ_SHIFT", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ( "READ_SHIFT", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ( "READ_SHIFT", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + # 2x asymmetric (1024x36bit write / 2048x18bit read or vice versa = 1TDP36K) + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), - # 4x write width (1024x36bit write / 4096x9bit read = 1TDP36K) - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 4), ("WRITE_SHIFT", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ("WRITE_SHIFT", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("WRITE_SHIFT", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - # and again for read - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 4), ( "READ_SHIFT", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ( "READ_SHIFT", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ( "READ_SHIFT", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - - # etc - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("WRITE_SHIFT", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ( "READ_SHIFT", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("WRITE_SHIFT", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ( "READ_SHIFT", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + # 4x asymmetric (1024x36bit write / 4096x9bit read or vice versa = 1TDP36K) + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 4), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), # can also use an extra TDP36K for higher width - ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("WRITE_SHIFT", 1)], "sync_ram_sdp_wwr", ["-assert-count 2 t:TDP36K"]), - ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ( "READ_SHIFT", 1)], "sync_ram_sdp_wrr", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 4 t:TDP36K"]), + ([("ADDRESS_WIDTH", 9), ("DATA_WIDTH", 36), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 4 t:TDP36K"]), - # not sure why these are different but apparently wide writes pack better? - ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("WRITE_SHIFT", 2)], "sync_ram_sdp_wwr", ["-assert-count 2 t:TDP36K"]), - ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ( "READ_SHIFT", 2)], "sync_ram_sdp_wrr", ["-assert-count 4 t:TDP36K"]), - ([("ADDRESS_WIDTH", 9), ("DATA_WIDTH", 36), ("WRITE_SHIFT", 2)], "sync_ram_sdp_wwr", ["-assert-count 2 t:TDP36K"]), - ([("ADDRESS_WIDTH", 9), ("DATA_WIDTH", 36), ( "READ_SHIFT", 2)], "sync_ram_sdp_wrr", ["-assert-count 4 t:TDP36K"]), + # # SHIFT=0 should be identical to sync_ram_sdp + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 0)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("SHIFT_VAL", 0)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), - # SHIFT=0 should be identical to sync_ram_sdp - ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ( "READ_SHIFT", 0)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ( "READ_SHIFT", 0)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - # but WRITE_SHIFT=0 doesn't generate any read circuitry and optimises the memory away -# ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("WRITE_SHIFT", 0)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), -# ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("WRITE_SHIFT", 0)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), + # asymmetric memories assign different port widths on a and b ports + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i a:port_b_width=18 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i a:port_b_width=9 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i a:port_b_width=9 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i a:port_b_width=36 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i a:port_b_width=18 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i a:port_b_width=36 %i"]), # two disjoint 18K memories can share a single TDP36K ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), @@ -90,6 +77,7 @@ ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]), # an unshared TDP36K sets is_split=0 ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), # sharing a TDP36K sets correct port widths ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("DATA_WIDTH_B", 18), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp", @@ -114,15 +102,18 @@ param_str = "" for (key, val) in params: param_str += f" -set {key} {val}" - if "*" in top: - star_sub = ["s", "t"] - else: - star_sub = [""] - for sub in star_sub: - print( - blockram_template.format(param_str=param_str, top=top.replace("*", sub)), - file=f - ) - for assertion in assertions: - print("select {}".format(assertion), file=f) - print("", file=f) + dp_subs = [""] + if "*dp" in top: + dp_subs = ["sdp", "tdp"] + wr_subs = [""] + if "w*r" in top: + wr_subs = ["wwr", "wrr"] + for db_sub in dp_subs: + for wr_sub in wr_subs: + print( + blockram_template.format(param_str=param_str, top=top.replace("*dp", db_sub).replace("w*r", wr_sub)), + file=f + ) + for assertion in assertions: + print("select {}".format(assertion), file=f) + print("", file=f) From f9c897812826655c61af63fa24361acdc0432d37 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Thu, 30 Nov 2023 19:35:43 +0100 Subject: [PATCH 193/240] add example memory test --- techlibs/quicklogic/Makefile.inc | 5 +- techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v | 344 ++++++++++ .../quicklogic/qlf_k6n10f/sram1024x18_mem.v | 64 ++ techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v | 620 ++++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v | 77 +++ tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys | 5 + .../arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v | 99 +++ 7 files changed, 1213 insertions(+), 1 deletion(-) create mode 100644 techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v create mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v create mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index 852a8a77a88..58dfc5b45f2 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -37,4 +37,7 @@ $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_map.v)) -$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v)) \ No newline at end of file +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v)) \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v b/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v new file mode 100644 index 00000000000..68c2eb0aa13 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v @@ -0,0 +1,344 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype wire +module TDP18K_FIFO ( + RMODE_A_i, + RMODE_B_i, + WMODE_A_i, + WMODE_B_i, + WEN_A_i, + WEN_B_i, + REN_A_i, + REN_B_i, + CLK_A_i, + CLK_B_i, + BE_A_i, + BE_B_i, + ADDR_A_i, + ADDR_B_i, + WDATA_A_i, + WDATA_B_i, + RDATA_A_o, + RDATA_B_o, + EMPTY_o, + EPO_o, + EWM_o, + UNDERRUN_o, + FULL_o, + FMO_o, + FWM_o, + OVERRUN_o, + FLUSH_ni, + FMODE_i, +); + parameter SYNC_FIFO_i = 1'b0; + parameter POWERDN_i = 1'b0; + parameter SLEEP_i = 1'b0; + parameter PROTECT_i = 1'b0; + parameter UPAF_i = 11'b0; + parameter UPAE_i = 11'b0; + parameter [18*1024-1:0] INIT_i = 18431'bx; + + input wire [2:0] RMODE_A_i; + input wire [2:0] RMODE_B_i; + input wire [2:0] WMODE_A_i; + input wire [2:0] WMODE_B_i; + input wire WEN_A_i; + input wire WEN_B_i; + input wire REN_A_i; + input wire REN_B_i; + (* clkbuf_sink *) + input wire CLK_A_i; + (* clkbuf_sink *) + input wire CLK_B_i; + input wire [1:0] BE_A_i; + input wire [1:0] BE_B_i; + input wire [13:0] ADDR_A_i; + input wire [13:0] ADDR_B_i; + input wire [17:0] WDATA_A_i; + input wire [17:0] WDATA_B_i; + output reg [17:0] RDATA_A_o; + output reg [17:0] RDATA_B_o; + output wire EMPTY_o; + output wire EPO_o; + output wire EWM_o; + output wire UNDERRUN_o; + output wire FULL_o; + output wire FMO_o; + output wire FWM_o; + output wire OVERRUN_o; + input wire FLUSH_ni; + input wire FMODE_i; + reg [17:0] wmsk_a; + reg [17:0] wmsk_b; + wire [8:0] addr_a; + wire [8:0] addr_b; + reg [4:0] addr_a_d; + reg [4:0] addr_b_d; + wire [17:0] ram_rdata_a; + wire [17:0] ram_rdata_b; + reg [17:0] aligned_wdata_a; + reg [17:0] aligned_wdata_b; + wire ren_o; + wire [10:0] ff_raddr; + wire [10:0] ff_waddr; + wire [13:0] ram_addr_a; + wire [13:0] ram_addr_b; + wire [3:0] ram_waddr_a; + wire [3:0] ram_waddr_b; + wire initn; + wire smux_rclk; + wire smux_wclk; + wire real_fmode; + wire [3:0] raw_fflags; + reg [1:0] fifo_rmode; + reg [1:0] fifo_wmode; + wire smux_clk_a; + wire smux_clk_b; + wire ram_ren_a; + wire ram_ren_b; + wire ram_wen_a; + wire ram_wen_b; + wire cen_a; + wire cen_b; + wire cen_a_n; + wire cen_b_n; + wire ram_wen_a_n; + wire ram_wen_b_n; + localparam MODE_9 = 3'b001; + always @(*) begin + fifo_rmode = (RMODE_B_i == MODE_9 ? 2'b10 : 2'b01); + fifo_wmode = (WMODE_A_i == MODE_9 ? 2'b10 : 2'b01); + end + assign smux_clk_a = CLK_A_i; + assign smux_clk_b = CLK_B_i; + assign real_fmode = FMODE_i; + assign ram_ren_b = real_fmode ? ren_o : REN_B_i; + assign ram_wen_a = FMODE_i ? ~FULL_o & WEN_A_i : WEN_A_i; + assign ram_ren_a = FMODE_i ? 0 : REN_A_i; + assign ram_wen_b = FMODE_i ? 1'b0 : WEN_B_i; + assign cen_b = ram_ren_b | ram_wen_b; + assign cen_a = ram_ren_a | ram_wen_a; + assign ram_waddr_b = real_fmode ? {ff_raddr[0], 3'b000} : ADDR_B_i[3:0]; + assign ram_waddr_a = real_fmode ? {ff_waddr[0], 3'b000} : ADDR_A_i[3:0]; + assign ram_addr_b = real_fmode ? {ff_raddr[10:0], 3'h0} : {ADDR_B_i[13:4], addr_b_d[3:0]}; + assign ram_addr_a = real_fmode ? {ff_waddr[10:0], 3'h0} : {ADDR_A_i[13:4], addr_a_d[3:0]}; + always @(posedge CLK_A_i) addr_a_d[3:0] <= ADDR_A_i[3:0]; + always @(posedge CLK_B_i) addr_b_d[3:0] <= ADDR_B_i[3:0]; + assign cen_a_n = ~cen_a; + assign ram_wen_a_n = ~ram_wen_a; + assign cen_b_n = ~cen_b; + assign ram_wen_b_n = ~ram_wen_b; + + sram1024x18 #( + .init(INIT_i) + ) uram( + .clk_a(smux_clk_a), + .cen_a(cen_a_n), + .wen_a(ram_wen_a_n), + .addr_a(ram_addr_a[13:4]), + .wmsk_a(wmsk_a), + .wdata_a(aligned_wdata_a), + .rdata_a(ram_rdata_a), + .clk_b(smux_clk_b), + .cen_b(cen_b_n), + .wen_b(ram_wen_b_n), + .addr_b(ram_addr_b[13:4]), + .wmsk_b(wmsk_b), + .wdata_b(aligned_wdata_b), + .rdata_b(ram_rdata_b) + ); + fifo_ctl #( + .ADDR_WIDTH(11), + .FIFO_WIDTH(2), + .DEPTH(6) + ) fifo_ctl( + .rclk(smux_clk_b), + .rst_R_n(FLUSH_ni), + .wclk(smux_clk_a), + .rst_W_n(FLUSH_ni), + .ren(REN_B_i), + .wen(ram_wen_a), + .sync(SYNC_FIFO_i), + .rmode(fifo_rmode), + .wmode(fifo_wmode), + .ren_o(ren_o), + .fflags({FULL_o, FMO_o, FWM_o, OVERRUN_o, EMPTY_o, EPO_o, EWM_o, UNDERRUN_o}), + .raddr(ff_raddr), + .waddr(ff_waddr), + .upaf(UPAF_i), + .upae(UPAE_i) + ); + localparam MODE_1 = 3'b101; + localparam MODE_18 = 3'b010; + localparam MODE_2 = 3'b110; + localparam MODE_4 = 3'b100; + always @(*) begin : WDATA_MODE_SEL + if (ram_wen_a == 1) begin + case (WMODE_A_i) + MODE_18: begin + aligned_wdata_a = WDATA_A_i; + {wmsk_a[17], wmsk_a[15:8]} = (FMODE_i ? 9'h000 : (BE_A_i[1] ? 9'h000 : 9'h1ff)); + {wmsk_a[16], wmsk_a[7:0]} = (FMODE_i ? 9'h000 : (BE_A_i[0] ? 9'h000 : 9'h1ff)); + end + MODE_9: begin + aligned_wdata_a = {{2 {WDATA_A_i[16]}}, {2 {WDATA_A_i[7:0]}}}; + {wmsk_a[17], wmsk_a[15:8]} = (ram_waddr_a[3] ? 9'h000 : 9'h1ff); + {wmsk_a[16], wmsk_a[7:0]} = (ram_waddr_a[3] ? 9'h1ff : 9'h000); + end + MODE_4: begin + aligned_wdata_a = {2'b00, {4 {WDATA_A_i[3:0]}}}; + wmsk_a[17:16] = 2'b00; + wmsk_a[15:12] = (ram_waddr_a[3:2] == 2'b11 ? 4'h0 : 4'hf); + wmsk_a[11:8] = (ram_waddr_a[3:2] == 2'b10 ? 4'h0 : 4'hf); + wmsk_a[7:4] = (ram_waddr_a[3:2] == 2'b01 ? 4'h0 : 4'hf); + wmsk_a[3:0] = (ram_waddr_a[3:2] == 2'b00 ? 4'h0 : 4'hf); + end + MODE_2: begin + aligned_wdata_a = {2'b00, {8 {WDATA_A_i[1:0]}}}; + wmsk_a[17:16] = 2'b00; + wmsk_a[15:14] = (ram_waddr_a[3:1] == 3'b111 ? 2'h0 : 2'h3); + wmsk_a[13:12] = (ram_waddr_a[3:1] == 3'b110 ? 2'h0 : 2'h3); + wmsk_a[11:10] = (ram_waddr_a[3:1] == 3'b101 ? 2'h0 : 2'h3); + wmsk_a[9:8] = (ram_waddr_a[3:1] == 3'b100 ? 2'h0 : 2'h3); + wmsk_a[7:6] = (ram_waddr_a[3:1] == 3'b011 ? 2'h0 : 2'h3); + wmsk_a[5:4] = (ram_waddr_a[3:1] == 3'b010 ? 2'h0 : 2'h3); + wmsk_a[3:2] = (ram_waddr_a[3:1] == 3'b001 ? 2'h0 : 2'h3); + wmsk_a[1:0] = (ram_waddr_a[3:1] == 3'b000 ? 2'h0 : 2'h3); + end + MODE_1: begin + aligned_wdata_a = {2'b00, {16 {WDATA_A_i[0]}}}; + wmsk_a = 18'h0ffff; + wmsk_a[{1'b0, ram_waddr_a[3:0]}] = 0; + end + default: wmsk_a = 18'h3ffff; + endcase + end + else begin + aligned_wdata_a = 18'h00000; + wmsk_a = 18'h3ffff; + end + if (ram_wen_b == 1) + case (WMODE_B_i) + MODE_18: begin + aligned_wdata_b = WDATA_B_i; + {wmsk_b[17], wmsk_b[15:8]} = (BE_B_i[1] ? 9'h000 : 9'h1ff); + {wmsk_b[16], wmsk_b[7:0]} = (BE_B_i[0] ? 9'h000 : 9'h1ff); + end + MODE_9: begin + aligned_wdata_b = {{2 {WDATA_B_i[16]}}, {2 {WDATA_B_i[7:0]}}}; + {wmsk_b[17], wmsk_b[15:8]} = (ram_waddr_b[3] ? 9'h000 : 9'h1ff); + {wmsk_b[16], wmsk_b[7:0]} = (ram_waddr_b[3] ? 9'h1ff : 9'h000); + end + MODE_4: begin + aligned_wdata_b = {2'b00, {4 {WDATA_B_i[3:0]}}}; + wmsk_b[17:16] = 2'b00; + wmsk_b[15:12] = (ram_waddr_b[3:2] == 2'b11 ? 4'h0 : 4'hf); + wmsk_b[11:8] = (ram_waddr_b[3:2] == 2'b10 ? 4'h0 : 4'hf); + wmsk_b[7:4] = (ram_waddr_b[3:2] == 2'b01 ? 4'h0 : 4'hf); + wmsk_b[3:0] = (ram_waddr_b[3:2] == 2'b00 ? 4'h0 : 4'hf); + end + MODE_2: begin + aligned_wdata_b = {2'b00, {8 {WDATA_B_i[1:0]}}}; + wmsk_b[17:16] = 2'b00; + wmsk_b[15:14] = (ram_waddr_b[3:1] == 3'b111 ? 2'h0 : 2'h3); + wmsk_b[13:12] = (ram_waddr_b[3:1] == 3'b110 ? 2'h0 : 2'h3); + wmsk_b[11:10] = (ram_waddr_b[3:1] == 3'b101 ? 2'h0 : 2'h3); + wmsk_b[9:8] = (ram_waddr_b[3:1] == 3'b100 ? 2'h0 : 2'h3); + wmsk_b[7:6] = (ram_waddr_b[3:1] == 3'b011 ? 2'h0 : 2'h3); + wmsk_b[5:4] = (ram_waddr_b[3:1] == 3'b010 ? 2'h0 : 2'h3); + wmsk_b[3:2] = (ram_waddr_b[3:1] == 3'b001 ? 2'h0 : 2'h3); + wmsk_b[1:0] = (ram_waddr_b[3:1] == 3'b000 ? 2'h0 : 2'h3); + end + MODE_1: begin + aligned_wdata_b = {2'b00, {16 {WDATA_B_i[0]}}}; + wmsk_b = 18'h0ffff; + wmsk_b[{1'b0, ram_waddr_b[3:0]}] = 0; + end + default: wmsk_b = 18'h3ffff; + endcase + else begin + aligned_wdata_b = 18'b000000000000000000; + wmsk_b = 18'h3ffff; + end + end + always @(*) begin : RDATA_A_MODE_SEL + case (RMODE_A_i) + default: RDATA_A_o = 18'h00000; + MODE_18: RDATA_A_o = ram_rdata_a; + MODE_9: begin + {RDATA_A_o[17], RDATA_A_o[15:8]} = 9'h000; + {RDATA_A_o[16], RDATA_A_o[7:0]} = (ram_addr_a[3] ? {ram_rdata_a[17], ram_rdata_a[15:8]} : {ram_rdata_a[16], ram_rdata_a[7:0]}); + end + MODE_4: begin + RDATA_A_o[17:4] = 14'h0000; + case (ram_addr_a[3:2]) + 3: RDATA_A_o[3:0] = ram_rdata_a[15:12]; + 2: RDATA_A_o[3:0] = ram_rdata_a[11:8]; + 1: RDATA_A_o[3:0] = ram_rdata_a[7:4]; + 0: RDATA_A_o[3:0] = ram_rdata_a[3:0]; + endcase + end + MODE_2: begin + RDATA_A_o[17:2] = 16'h0000; + case (ram_addr_a[3:1]) + 7: RDATA_A_o[1:0] = ram_rdata_a[15:14]; + 6: RDATA_A_o[1:0] = ram_rdata_a[13:12]; + 5: RDATA_A_o[1:0] = ram_rdata_a[11:10]; + 4: RDATA_A_o[1:0] = ram_rdata_a[9:8]; + 3: RDATA_A_o[1:0] = ram_rdata_a[7:6]; + 2: RDATA_A_o[1:0] = ram_rdata_a[5:4]; + 1: RDATA_A_o[1:0] = ram_rdata_a[3:2]; + 0: RDATA_A_o[1:0] = ram_rdata_a[1:0]; + endcase + end + MODE_1: begin + RDATA_A_o[17:1] = 17'h00000; + RDATA_A_o[0] = ram_rdata_a[ram_addr_a[3:0]]; + end + endcase + end + always @(*) + case (RMODE_B_i) + default: RDATA_B_o = 18'h15566; + MODE_18: RDATA_B_o = ram_rdata_b; + MODE_9: begin + {RDATA_B_o[17], RDATA_B_o[15:8]} = 9'b000000000; + {RDATA_B_o[16], RDATA_B_o[7:0]} = (ram_addr_b[3] ? {ram_rdata_b[17], ram_rdata_b[15:8]} : {ram_rdata_b[16], ram_rdata_b[7:0]}); + end + MODE_4: + case (ram_addr_b[3:2]) + 3: RDATA_B_o[3:0] = ram_rdata_b[15:12]; + 2: RDATA_B_o[3:0] = ram_rdata_b[11:8]; + 1: RDATA_B_o[3:0] = ram_rdata_b[7:4]; + 0: RDATA_B_o[3:0] = ram_rdata_b[3:0]; + endcase + MODE_2: + case (ram_addr_b[3:1]) + 7: RDATA_B_o[1:0] = ram_rdata_b[15:14]; + 6: RDATA_B_o[1:0] = ram_rdata_b[13:12]; + 5: RDATA_B_o[1:0] = ram_rdata_b[11:10]; + 4: RDATA_B_o[1:0] = ram_rdata_b[9:8]; + 3: RDATA_B_o[1:0] = ram_rdata_b[7:6]; + 2: RDATA_B_o[1:0] = ram_rdata_b[5:4]; + 1: RDATA_B_o[1:0] = ram_rdata_b[3:2]; + 0: RDATA_B_o[1:0] = ram_rdata_b[1:0]; + endcase + MODE_1: RDATA_B_o[0] = ram_rdata_b[{1'b0, ram_addr_b[3:0]}]; + endcase +endmodule +`default_nettype none diff --git a/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v b/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v new file mode 100644 index 00000000000..86698ffefd3 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v @@ -0,0 +1,64 @@ +`default_nettype none +module sram1024x18 ( + clk_a, + cen_a, + wen_a, + addr_a, + wmsk_a, + wdata_a, + rdata_a, + clk_b, + cen_b, + wen_b, + addr_b, + wmsk_b, + wdata_b, + rdata_b +); + parameter [1024*18-1:0] init = 18431'bx; + (* clkbuf_sink *) + input wire clk_a; + input wire cen_a; + input wire wen_a; + input wire [9:0] addr_a; + input wire [17:0] wmsk_a; + input wire [17:0] wdata_a; + output reg [17:0] rdata_a; + (* clkbuf_sink *) + input wire clk_b; + input wire cen_b; + input wire wen_b; + input wire [9:0] addr_b; + input wire [17:0] wmsk_b; + input wire [17:0] wdata_b; + output reg [17:0] rdata_b; + reg [17:0] ram [1023:0]; + integer i; + initial begin + for (i = 0; i < 1024; i = i + 1) begin + ram[i] = init[18*i +: 18]; + end + end + + always @(posedge clk_a) begin + if (!cen_a) begin + if (!wen_a) + for (i = 0; i < 18; i++) begin + if (!wmsk_a[i]) ram[addr_a][i] <= wdata_a[i]; + end + rdata_a <= ram[addr_a]; + end + end + + always @(posedge clk_b) begin + if (!cen_b) begin + if (!wen_b) + for (i = 0; i < 18; i++) begin + if (!wmsk_b[i]) ram[addr_b][i] <= wdata_b[i]; + end + rdata_b <= ram[addr_b]; + end + end + +endmodule + diff --git a/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v b/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v new file mode 100644 index 00000000000..441f6bc4a81 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v @@ -0,0 +1,620 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype wire +module fifo_ctl ( + raddr, + waddr, + fflags, + ren_o, + sync, + rmode, + wmode, + rclk, + rst_R_n, + wclk, + rst_W_n, + ren, + wen, + upaf, + upae +); + parameter ADDR_WIDTH = 11; + parameter FIFO_WIDTH = 3'd2; + parameter DEPTH = 6; + output wire [ADDR_WIDTH - 1:0] raddr; + output wire [ADDR_WIDTH - 1:0] waddr; + output wire [7:0] fflags; + output wire ren_o; + input wire sync; + input wire [1:0] rmode; + input wire [1:0] wmode; + (* clkbuf_sink *) + input wire rclk; + input wire rst_R_n; + (* clkbuf_sink *) + input wire wclk; + input wire rst_W_n; + input wire ren; + input wire wen; + input wire [ADDR_WIDTH - 1:0] upaf; + input wire [ADDR_WIDTH - 1:0] upae; + localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; + reg [ADDR_WIDTH:0] pushtopop1; + reg [ADDR_WIDTH:0] pushtopop2; + reg [ADDR_WIDTH:0] poptopush1; + reg [ADDR_WIDTH:0] poptopush2; + wire [ADDR_WIDTH:0] pushtopop0; + wire [ADDR_WIDTH:0] poptopush0; + wire [ADDR_WIDTH:0] smux_poptopush; + wire [ADDR_WIDTH:0] smux_pushtopop; + assign smux_poptopush = (sync ? poptopush0 : poptopush2); + assign smux_pushtopop = (sync ? pushtopop0 : pushtopop2); + always @(posedge rclk or negedge rst_R_n) + if (~rst_R_n) begin + pushtopop1 <= 'h0; + pushtopop2 <= 'h0; + end + else begin + pushtopop1 = pushtopop0; + pushtopop2 = pushtopop1; + end + always @(posedge wclk or negedge rst_W_n) + if (~rst_W_n) begin + poptopush1 <= 'h0; + poptopush2 <= 'h0; + end + else begin + poptopush1 <= poptopush0; + poptopush2 <= poptopush1; + end + fifo_push #( + .ADDR_WIDTH(ADDR_WIDTH), + .DEPTH(DEPTH) + ) u_fifo_push( + .wclk(wclk), + .wen(wen), + .rst_n(rst_W_n), + .rmode(rmode), + .wmode(wmode), + .gcout(pushtopop0), + .gcin(smux_poptopush), + .ff_waddr(waddr), + .pushflags(fflags[7:4]), + .upaf(upaf) + ); + fifo_pop #( + .ADDR_WIDTH(ADDR_WIDTH), + .FIFO_WIDTH(FIFO_WIDTH), + .DEPTH(DEPTH) + ) u_fifo_pop( + .rclk(rclk), + .ren_in(ren), + .rst_n(rst_R_n), + .rmode(rmode), + .wmode(wmode), + .ren_o(ren_o), + .gcout(poptopush0), + .gcin(smux_pushtopop), + .out_raddr(raddr), + .popflags(fflags[3:0]), + .upae(upae) + ); +endmodule +module fifo_push ( + pushflags, + gcout, + ff_waddr, + rst_n, + wclk, + wen, + rmode, + wmode, + gcin, + upaf +); + parameter ADDR_WIDTH = 11; + parameter DEPTH = 6; + output wire [3:0] pushflags; + output wire [ADDR_WIDTH:0] gcout; + output wire [ADDR_WIDTH - 1:0] ff_waddr; + input rst_n; + (* clkbuf_sink *) + input wclk; + input wen; + input [1:0] rmode; + input [1:0] wmode; + input [ADDR_WIDTH:0] gcin; + input [ADDR_WIDTH - 1:0] upaf; + localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; + reg full_next; + reg full; + reg paf_next; + reg paf; + reg fmo; + reg fmo_next; + reg overflow; + reg p1; + reg p2; + reg f1; + reg f2; + reg q1; + reg q2; + reg [1:0] gmode; + reg [ADDR_WIDTH:0] waddr; + reg [ADDR_WIDTH:0] raddr; + reg [ADDR_WIDTH:0] gcout_reg; + reg [ADDR_WIDTH:0] gcout_next; + reg [ADDR_WIDTH:0] raddr_next; + reg [ADDR_WIDTH - 1:0] paf_thresh; + wire overflow_next; + wire [ADDR_WIDTH:0] waddr_next; + wire [ADDR_WIDTH:0] gc8out_next; + wire [ADDR_WIDTH - 1:0] gc16out_next; + wire [ADDR_WIDTH - 2:0] gc32out_next; + wire [ADDR_WIDTH:0] tmp; + wire [ADDR_WIDTH:0] next_count; + wire [ADDR_WIDTH:0] count; + wire [ADDR_WIDTH:0] fbytes; + genvar i; + assign next_count = fbytes - (waddr_next >= raddr_next ? waddr_next - raddr_next : (~raddr_next + waddr_next) + 1); + assign count = fbytes - (waddr >= raddr ? waddr - raddr : (~raddr + waddr) + 1); + assign fbytes = 1 << (DEPTH + 5); + always @(*) begin + paf_thresh = wmode[1] ? upaf : (wmode[0] ? upaf << 1 : upaf << 2); + end + always @(*) + case (wmode) + 2'h0, 2'h1, 2'h2: begin + full_next = (wen ? f1 : f2); + fmo_next = (wen ? p1 : p2); + paf_next = (wen ? q1 : q2); + end + default: begin + full_next = 1'b0; + fmo_next = 1'b0; + paf_next = 1'b0; + end + endcase + always @(*) begin : PUSH_FULL_FLAGS + f1 = 1'b0; + f2 = 1'b0; + p1 = 1'b0; + p2 = 1'b0; + q1 = next_count < {1'b0, paf_thresh}; + q2 = count < {1'b0, paf_thresh}; + case (wmode) + 2'h0: + case (DEPTH) + 3'h6: begin + f1 = {~waddr_next[11], waddr_next[10:2]} == raddr_next[11:2]; + f2 = {~waddr[11], waddr[10:2]} == raddr_next[11:2]; + p1 = ((waddr_next[10:2] + 1) & 9'h1ff) == raddr_next[10:2]; + p2 = ((waddr[10:2] + 1) & 9'h1ff) == raddr_next[10:2]; + end + 3'h5: begin + f1 = {~waddr_next[10], waddr_next[9:2]} == raddr_next[10:2]; + f2 = {~waddr[10], waddr[9:2]} == raddr_next[10:2]; + p1 = ((waddr_next[9:2] + 1) & 8'hff) == raddr_next[9:2]; + p2 = ((waddr[9:2] + 1) & 8'hff) == raddr_next[9:2]; + end + 3'h4: begin + f1 = {~waddr_next[9], waddr_next[8:2]} == raddr_next[9:2]; + f2 = {~waddr[9], waddr[8:2]} == raddr_next[9:2]; + p1 = ((waddr_next[8:2] + 1) & 7'h7f) == raddr_next[8:2]; + p2 = ((waddr[8:2] + 1) & 7'h7f) == raddr_next[8:2]; + end + 3'h3: begin + f1 = {~waddr_next[8], waddr_next[7:2]} == raddr_next[8:2]; + f2 = {~waddr[8], waddr[7:2]} == raddr_next[8:2]; + p1 = ((waddr_next[7:2] + 1) & 6'h3f) == raddr_next[7:2]; + p2 = ((waddr[7:2] + 1) & 6'h3f) == raddr_next[7:2]; + end + 3'h2: begin + f1 = {~waddr_next[7], waddr_next[6:2]} == raddr_next[7:2]; + f2 = {~waddr[7], waddr[6:2]} == raddr_next[7:2]; + p1 = ((waddr_next[6:2] + 1) & 5'h1f) == raddr_next[6:2]; + p2 = ((waddr[6:2] + 1) & 5'h1f) == raddr_next[6:2]; + end + 3'h1: begin + f1 = {~waddr_next[6], waddr_next[5:2]} == raddr_next[6:2]; + f2 = {~waddr[6], waddr[5:2]} == raddr_next[6:2]; + p1 = ((waddr_next[5:2] + 1) & 4'hf) == raddr_next[5:2]; + p2 = ((waddr[5:2] + 1) & 4'hf) == raddr_next[5:2]; + end + 3'h0: begin + f1 = {~waddr_next[5], waddr_next[4:2]} == raddr_next[5:2]; + f2 = {~waddr[5], waddr[4:2]} == raddr_next[5:2]; + p1 = ((waddr_next[4:2] + 1) & 3'h7) == raddr_next[4:2]; + p2 = ((waddr[4:2] + 1) & 3'h7) == raddr_next[4:2]; + end + 3'h7: begin + f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:2]} == raddr_next[ADDR_WIDTH:2]; + f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:2]} == raddr_next[ADDR_WIDTH:2]; + p1 = ((waddr_next[ADDR_WIDTH - 1:2] + 1) & {ADDR_WIDTH - 2 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:2]; + p2 = ((waddr[ADDR_WIDTH - 1:2] + 1) & {ADDR_WIDTH - 2 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:2]; + end + endcase + 2'h1: + case (DEPTH) + 3'h6: begin + f1 = {~waddr_next[11], waddr_next[10:1]} == raddr_next[11:1]; + f2 = {~waddr[11], waddr[10:1]} == raddr_next[11:1]; + p1 = ((waddr_next[10:1] + 1) & 10'h3ff) == raddr_next[10:1]; + p2 = ((waddr[10:1] + 1) & 10'h3ff) == raddr_next[10:1]; + end + 3'h5: begin + f1 = {~waddr_next[10], waddr_next[9:1]} == raddr_next[10:1]; + f2 = {~waddr[10], waddr[9:1]} == raddr_next[10:1]; + p1 = ((waddr_next[9:1] + 1) & 9'h1ff) == raddr_next[9:1]; + p2 = ((waddr[9:1] + 1) & 9'h1ff) == raddr_next[9:1]; + end + 3'h4: begin + f1 = {~waddr_next[9], waddr_next[8:1]} == raddr_next[9:1]; + f2 = {~waddr[9], waddr[8:1]} == raddr_next[9:1]; + p1 = ((waddr_next[8:1] + 1) & 8'hff) == raddr_next[8:1]; + p2 = ((waddr[8:1] + 1) & 8'hff) == raddr_next[8:1]; + end + 3'h3: begin + f1 = {~waddr_next[8], waddr_next[7:1]} == raddr_next[8:1]; + f2 = {~waddr[8], waddr[7:1]} == raddr_next[8:1]; + p1 = ((waddr_next[7:1] + 1) & 7'h7f) == raddr_next[7:1]; + p2 = ((waddr[7:1] + 1) & 7'h7f) == raddr_next[7:1]; + end + 3'h2: begin + f1 = {~waddr_next[7], waddr_next[6:1]} == raddr_next[7:1]; + f2 = {~waddr[7], waddr[6:1]} == raddr_next[7:1]; + p1 = ((waddr_next[6:1] + 1) & 6'h3f) == raddr_next[6:1]; + p2 = ((waddr[6:1] + 1) & 6'h3f) == raddr_next[6:1]; + end + 3'h1: begin + f1 = {~waddr_next[6], waddr_next[5:1]} == raddr_next[6:1]; + f2 = {~waddr[6], waddr[5:1]} == raddr_next[6:1]; + p1 = ((waddr_next[5:1] + 1) & 5'h1f) == raddr_next[5:1]; + p2 = ((waddr[5:1] + 1) & 5'h1f) == raddr_next[5:1]; + end + 3'h0: begin + f1 = {~waddr_next[5], waddr_next[4:1]} == raddr_next[5:1]; + f2 = {~waddr[5], waddr[4:1]} == raddr_next[5:1]; + p1 = ((waddr_next[4:1] + 1) & 4'hf) == raddr_next[4:1]; + p2 = ((waddr[4:1] + 1) & 4'hf) == raddr_next[4:1]; + end + 3'h7: begin + f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:1]} == raddr_next[ADDR_WIDTH:1]; + f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:1]} == raddr_next[ADDR_WIDTH:1]; + p1 = ((waddr_next[ADDR_WIDTH - 1:1] + 1) & {ADDR_WIDTH - 1 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:1]; + p2 = ((waddr[ADDR_WIDTH - 1:1] + 1) & {ADDR_WIDTH - 1 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:1]; + end + endcase + 2'h2: + case (DEPTH) + 3'h6: begin + f1 = {~waddr_next[11], waddr_next[10:0]} == raddr_next[11:0]; + f2 = {~waddr[11], waddr[10:0]} == raddr_next[11:0]; + p1 = ((waddr_next[10:0] + 1) & 11'h7ff) == raddr_next[10:0]; + p2 = ((waddr[10:0] + 1) & 11'h7ff) == raddr_next[10:0]; + end + 3'h5: begin + f1 = {~waddr_next[10], waddr_next[9:0]} == raddr_next[10:0]; + f2 = {~waddr[10], waddr[9:0]} == raddr_next[10:0]; + p1 = ((waddr_next[9:0] + 1) & 10'h3ff) == raddr_next[9:0]; + p2 = ((waddr[9:0] + 1) & 10'h3ff) == raddr_next[9:0]; + end + 3'h4: begin + f1 = {~waddr_next[9], waddr_next[8:0]} == raddr_next[9:0]; + f2 = {~waddr[9], waddr[8:0]} == raddr_next[9:0]; + p1 = ((waddr_next[8:0] + 1) & 9'h1ff) == raddr_next[8:0]; + p2 = ((waddr[8:0] + 1) & 9'h1ff) == raddr_next[8:0]; + end + 3'h3: begin + f1 = {~waddr_next[8], waddr_next[7:0]} == raddr_next[8:0]; + f2 = {~waddr[8], waddr[7:0]} == raddr_next[8:0]; + p1 = ((waddr_next[7:0] + 1) & 8'hff) == raddr_next[7:0]; + p2 = ((waddr[7:0] + 1) & 8'hff) == raddr_next[7:0]; + end + 3'h2: begin + f1 = {~waddr_next[7], waddr_next[6:0]} == raddr_next[7:0]; + f2 = {~waddr[7], waddr[6:0]} == raddr_next[7:0]; + p1 = ((waddr_next[6:0] + 1) & 7'h7f) == raddr_next[6:0]; + p2 = ((waddr[6:0] + 1) & 7'h7f) == raddr_next[6:0]; + end + 3'h1: begin + f1 = {~waddr_next[6], waddr_next[5:0]} == raddr_next[6:0]; + f2 = {~waddr[6], waddr[5:0]} == raddr_next[6:0]; + p1 = ((waddr_next[5:0] + 1) & 6'h3f) == raddr_next[5:0]; + p2 = ((waddr[5:0] + 1) & 6'h3f) == raddr_next[5:0]; + end + 3'h0: begin + f1 = {~waddr_next[5], waddr_next[4:0]} == raddr_next[5:0]; + f2 = {~waddr[5], waddr[4:0]} == raddr_next[5:0]; + p1 = ((waddr_next[4:0] + 1) & 5'h1f) == raddr_next[4:0]; + p2 = ((waddr[4:0] + 1) & 5'h1f) == raddr_next[4:0]; + end + 3'h7: begin + f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:0]} == raddr_next[ADDR_WIDTH:0]; + f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:0]} == raddr_next[ADDR_WIDTH:0]; + p1 = ((waddr_next[ADDR_WIDTH - 1:0] + 1) & {ADDR_WIDTH {1'b1}}) == raddr_next[ADDR_WIDTH - 1:0]; + p2 = ((waddr[ADDR_WIDTH - 1:0] + 1) & {ADDR_WIDTH {1'b1}}) == raddr_next[ADDR_WIDTH - 1:0]; + end + endcase + 2'h3: begin + f1 = 1'b0; + f2 = 1'b0; + p1 = 1'b0; + p2 = 1'b0; + end + endcase + end + always @(*) + case (wmode) + 2'h0: gmode = 2'h0; + 2'h1: gmode = (rmode == 2'h0 ? 2'h0 : 2'h1); + 2'h2: gmode = (rmode == 2'h2 ? 2'h2 : rmode); + 2'h3: gmode = 2'h3; + endcase + assign gc8out_next = (waddr_next >> 1) ^ waddr_next; + assign gc16out_next = (waddr_next >> 2) ^ (waddr_next >> 1); + assign gc32out_next = (waddr_next >> 3) ^ (waddr_next >> 2); + always @(*) + if (wen) + case (gmode) + 2'h2: gcout_next = gc8out_next; + 2'h1: gcout_next = {1'b0, gc16out_next}; + 2'h0: gcout_next = {2'b00, gc32out_next}; + default: gcout_next = {ADDR_PLUS_ONE {1'b0}}; + endcase + else + gcout_next = {ADDR_PLUS_ONE {1'b0}}; + always @(posedge wclk or negedge rst_n) + if (~rst_n) begin + full <= 1'b0; + fmo <= 1'b0; + paf <= 1'b0; + raddr <= {ADDR_PLUS_ONE {1'b0}}; + end + else begin + full <= full_next; + fmo <= fmo_next; + paf <= paf_next; + case (gmode) + 0: raddr <= raddr_next & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00}; + 1: raddr <= raddr_next & {{ADDR_WIDTH {1'b1}}, 1'b0}; + 2: raddr <= raddr_next & {ADDR_WIDTH + 1 {1'b1}}; + 3: raddr <= 12'h000; + endcase + end + assign overflow_next = full & wen; + always @(posedge wclk or negedge rst_n) + if (~rst_n) + overflow <= 1'b0; + else if (wen == 1'b1) + overflow <= overflow_next; + always @(posedge wclk or negedge rst_n) + if (~rst_n) begin + waddr <= {ADDR_WIDTH + 1 {1'b0}}; + gcout_reg <= {ADDR_WIDTH + 1 {1'b0}}; + end + else if (wen == 1'b1) begin + waddr <= waddr_next; + gcout_reg <= gcout_next; + end + assign gcout = gcout_reg; + generate + for (i = 0; i < (ADDR_WIDTH + 1); i = i + 1) begin : genblk1 + assign tmp[i] = ^(gcin >> i); + end + endgenerate + always @(*) + case (gmode) + 2'h0: raddr_next = {tmp[ADDR_WIDTH - 2:0], 2'b00} & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00}; + 2'h1: raddr_next = {tmp[ADDR_WIDTH - 1:0], 1'b0} & {{ADDR_WIDTH {1'b1}}, 1'b0}; + 2'h2: raddr_next = {tmp[ADDR_WIDTH:0]} & {ADDR_WIDTH + 1 {1'b1}}; + default: raddr_next = {ADDR_WIDTH + 1 {1'b0}}; + endcase + assign ff_waddr = waddr[ADDR_WIDTH - 1:0]; + assign pushflags = {full, fmo, paf, overflow}; + assign waddr_next = waddr + (wmode == 2'h0 ? 'h4 : (wmode == 2'h1 ? 'h2 : 'h1)); +endmodule +module fifo_pop ( + ren_o, + popflags, + out_raddr, + gcout, + rst_n, + rclk, + ren_in, + rmode, + wmode, + gcin, + upae +); + parameter ADDR_WIDTH = 11; + parameter FIFO_WIDTH = 3'd2; + parameter DEPTH = 6; + output wire ren_o; + output wire [3:0] popflags; + output reg [ADDR_WIDTH - 1:0] out_raddr; + output wire [ADDR_WIDTH:0] gcout; + input rst_n; + (* clkbuf_sink *) + input rclk; + input ren_in; + input [1:0] rmode; + input [1:0] wmode; + input [ADDR_WIDTH:0] gcin; + input [ADDR_WIDTH - 1:0] upae; + localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; + reg empty; + reg epo; + reg pae; + reg underflow; + reg e1; + reg e2; + reg o1; + reg o2; + reg q1; + reg q2; + reg [1:0] bwl_sel; + reg [1:0] gmode; + reg [ADDR_WIDTH - 1:0] ff_raddr; + reg [ADDR_WIDTH:0] waddr; + reg [ADDR_WIDTH:0] raddr; + reg [ADDR_WIDTH:0] gcout_reg; + reg [ADDR_WIDTH:0] gcout_next; + reg [ADDR_WIDTH:0] waddr_next; + reg [ADDR_WIDTH - 1:0] pae_thresh; + wire ren_out; + wire empty_next; + wire pae_next; + wire epo_next; + wire [ADDR_WIDTH - 2:0] gc32out_next; + wire [ADDR_WIDTH - 1:0] gc16out_next; + wire [ADDR_WIDTH:0] gc8out_next; + wire [ADDR_WIDTH:0] raddr_next; + wire [ADDR_WIDTH - 1:0] ff_raddr_next; + wire [ADDR_WIDTH:0] tmp; + wire [ADDR_PLUS_ONE:0] next_count; + wire [ADDR_PLUS_ONE:0] count; + wire [ADDR_PLUS_ONE:0] fbytes; + genvar i; + assign next_count = waddr - raddr_next; + assign count = waddr - raddr; + assign fbytes = 1 << (DEPTH + 5); + always @(*) pae_thresh = rmode[1] ? upae : (rmode[0] ? upae << 1 : upae << 2); + assign ren_out = (empty ? 1'b1 : ren_in); + always @(*) + case (rmode) + 2'h0: gmode = 2'h0; + 2'h1: gmode = (wmode == 2'h0 ? 2'h0 : 2'h1); + 2'h2: gmode = (wmode == 2'h2 ? 2'h2 : wmode); + 2'h3: gmode = 2'h3; + endcase + always @(*) begin + e1 = 1'b0; + e2 = 1'b0; + o1 = 1'b0; + o2 = 1'b0; + q1 = next_count < {1'b0, pae_thresh}; + q2 = count < {1'b0, pae_thresh}; + case (rmode) + 2'h0: begin + e1 = raddr_next[ADDR_WIDTH:2] == waddr_next[ADDR_WIDTH:2]; + e2 = raddr[ADDR_WIDTH:2] == waddr_next[ADDR_WIDTH:2]; + o1 = (raddr_next[ADDR_WIDTH:2] + 1) == waddr_next[ADDR_WIDTH:2]; + o2 = (raddr[ADDR_WIDTH:2] + 1) == waddr_next[ADDR_WIDTH:2]; + end + 2'h1: begin + e1 = raddr_next[ADDR_WIDTH:1] == waddr_next[ADDR_WIDTH:1]; + e2 = raddr[ADDR_WIDTH:1] == waddr_next[ADDR_WIDTH:1]; + o1 = (raddr_next[ADDR_WIDTH:1] + 1) == waddr_next[ADDR_WIDTH:1]; + o2 = (raddr[ADDR_WIDTH:1] + 1) == waddr_next[ADDR_WIDTH:1]; + end + 2'h2: begin + e1 = raddr_next[ADDR_WIDTH:0] == waddr_next[ADDR_WIDTH:0]; + e2 = raddr[ADDR_WIDTH:0] == waddr_next[ADDR_WIDTH:0]; + o1 = (raddr_next[ADDR_WIDTH:0] + 1) == waddr_next[ADDR_WIDTH:0]; + o2 = (raddr[ADDR_WIDTH:0] + 1) == waddr_next[11:0]; + end + 2'h3: begin + e1 = 1'b0; + e2 = 1'b0; + o1 = 1'b0; + o2 = 1'b0; + end + endcase + end + assign empty_next = (ren_in & !empty ? e1 : e2); + assign epo_next = (ren_in & !empty ? o1 : o2); + assign pae_next = (ren_in & !empty ? q1 : q2); + always @(posedge rclk or negedge rst_n) + if (~rst_n) begin + empty <= 1'b1; + pae <= 1'b1; + epo <= 1'b0; + end + else begin + empty <= empty_next; + pae <= pae_next; + epo <= epo_next; + end + assign gc8out_next = (raddr_next >> 1) ^ raddr_next; + assign gc16out_next = (raddr_next >> 2) ^ (raddr_next >> 1); + assign gc32out_next = (raddr_next >> 3) ^ (raddr_next >> 2); + always @(*) + if (ren_in) + case (gmode) + 2'h2: gcout_next = gc8out_next; + 2'h1: gcout_next = {1'b0, gc16out_next}; + 2'h0: gcout_next = {2'b00, gc32out_next}; + default: gcout_next = 'h0; + endcase + else + gcout_next = 'h0; + always @(posedge rclk or negedge rst_n) + if (~rst_n) + waddr <= 12'h000; + else + waddr <= waddr_next; + always @(posedge rclk or negedge rst_n) + if (~rst_n) begin + underflow <= 1'b0; + bwl_sel <= 2'h0; + gcout_reg <= 12'h000; + end + else if (ren_in) begin + underflow <= empty; + if (!empty) begin + bwl_sel <= raddr_next[1:0]; + gcout_reg <= gcout_next; + end + end + generate + for (i = 0; i < (ADDR_WIDTH + 1); i = i + 1) begin : genblk1 + assign tmp[i] = ^(gcin >> i); + end + endgenerate + always @(*) + case (gmode) + 2'h0: waddr_next = {tmp[ADDR_WIDTH - 2:0], 2'b00} & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00}; + 2'h1: waddr_next = {tmp[ADDR_WIDTH - 1:0], 1'b0} & {{ADDR_WIDTH {1'b1}}, 1'b0}; + 2'h2: waddr_next = {tmp[ADDR_WIDTH:0]} & {ADDR_PLUS_ONE {1'b1}}; + default: waddr_next = {ADDR_PLUS_ONE {1'b0}}; + endcase + assign ff_raddr_next = ff_raddr + (rmode == 2'h0 ? 'h4 : (rmode == 2'h1 ? 'h2 : 'h1)); + assign raddr_next = raddr + (rmode == 2'h0 ? 'h4 : (rmode == 2'h1 ? 'h2 : 'h1)); + always @(posedge rclk or negedge rst_n) + if (~rst_n) + ff_raddr <= 1'sb0; + else if (empty & ~empty_next) + ff_raddr <= raddr_next[ADDR_WIDTH - 1:0]; + else if ((ren_in & !empty) & ~empty_next) + ff_raddr <= ff_raddr_next; + always @(posedge rclk or negedge rst_n) + if (~rst_n) + raddr <= 12'h000; + else if (ren_in & !empty) + raddr <= raddr_next; + always @(*) + case (FIFO_WIDTH) + 3'h2: out_raddr = {ff_raddr[ADDR_WIDTH - 1:1], bwl_sel[0]}; + 3'h4: out_raddr = {ff_raddr[ADDR_WIDTH - 1:2], bwl_sel}; + default: out_raddr = ff_raddr[ADDR_WIDTH - 1:0]; + endcase + assign ren_o = ren_out; + assign gcout = gcout_reg; + assign popflags = {empty, epo, pae, underflow}; +endmodule +`default_nettype none diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v new file mode 100644 index 00000000000..536cce992f0 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v @@ -0,0 +1,77 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module BRAM_TDP #(parameter AWIDTH = 10, +parameter DWIDTH = 36)( + clk_a, + rce_a, + ra_a, + rq_a, + wce_a, + wa_a, + wd_a, + + clk_b, + rce_b, + ra_b, + rq_b, + wce_b, + wa_b, + wd_b +); + + input clk_a; + input rce_a; + input [AWIDTH-1:0] ra_a; + output reg [DWIDTH-1:0] rq_a; + input wce_a; + input [AWIDTH-1:0] wa_a; + input [DWIDTH-1:0] wd_a; + + input clk_b; + input rce_b; + input [AWIDTH-1:0] ra_b; + output reg [DWIDTH-1:0] rq_b; + input wce_b; + input [AWIDTH-1:0] wa_b; + input [DWIDTH-1:0] wd_b; + + (* no_rw_check = 1 *) + reg [DWIDTH-1:0] memory[0:(1< 0) begin + if($past(rce_a)) + assert(rq_a == rq_a_expected[i]); + if($past(rce_b)) + assert(rq_b == rq_b_expected[i]); + end + i <= i + 1; + end +end +endmodule \ No newline at end of file From ba3be3fd1c0051e8b02b51246fbcff437418b39b Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 1 Dec 2023 09:47:46 +1300 Subject: [PATCH 194/240] QLF_TDP36K: test bram_tdp post synth --- tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys | 7 +++++-- tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v | 4 ++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys index 89fcf447280..635769cc0d2 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys +++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys @@ -1,5 +1,8 @@ +read_verilog bram_tdp.v +hierarchy -top BRAM_TDP +synth_quicklogic -family qlf_k6n10f read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v -read_verilog -formal bram_tdp.v bram_tdp_tb.v +read_verilog -formal bram_tdp_tb.v hierarchy -top TB proc -sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd \ No newline at end of file +sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v index 0d5d9159d14..5d4fbe06779 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v @@ -63,10 +63,10 @@ wire wce_b = wce_b_testvector[i]; wire [ADDR_WIDTH-1:0] wa_b = wa_b_testvector[i]; wire [DATA_WIDTH-1:0] wd_b = wd_b_testvector[i]; -uut #( +BRAM_TDP #( .AWIDTH(ADDR_WIDTH), .DWIDTH(DATA_WIDTH) -) BRAM_TDP ( +) uut ( .clk_a(clk), .rce_a(rce_a), .ra_a(ra_a), From 3d08ed216d8734bfd6789a0a651bda147ba8096b Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 1 Dec 2023 12:55:59 +1300 Subject: [PATCH 195/240] QLF_TDP36K: parameterised sim test gen Also limited to 16 tests per file to allow parallelism. Previous tests are converted to new test format with no sim test steps. --- .../quicklogic/qlf_k6n10f/gen_memories.py | 174 ++++++++++++++++-- tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 73 ++++++++ 2 files changed, 227 insertions(+), 20 deletions(-) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/mem_tb.v diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index 353843b7898..ea750b8ed9a 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -1,3 +1,8 @@ +from __future__ import annotations + +from dataclasses import dataclass + + blockram_template = """# ====================================== design -reset; read_verilog -defer ../../common/blockram.v chparam{param_str} {top} @@ -97,23 +102,152 @@ "-assert-count 1 t:TDP36K"]), ] -with open("t_mem.ys", mode="w") as f: - for (params, top, assertions) in blockram_tests: - param_str = "" - for (key, val) in params: - param_str += f" -set {key} {val}" - dp_subs = [""] - if "*dp" in top: - dp_subs = ["sdp", "tdp"] - wr_subs = [""] - if "w*r" in top: - wr_subs = ["wwr", "wrr"] - for db_sub in dp_subs: - for wr_sub in wr_subs: - print( - blockram_template.format(param_str=param_str, top=top.replace("*dp", db_sub).replace("w*r", wr_sub)), - file=f - ) - for assertion in assertions: - print("select {}".format(assertion), file=f) - print("", file=f) +sim_template = """\ +cd +read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v +read_verilog < 1: + top_list.pop(0) + + # iterate over string substitutions + for top in top_list: + # limit number of tests per file to allow parallel make + if not f: + fn = f"t_mem{i}.ys" + f = open(fn, mode="w") + j = 0 + + # output yosys script test file + print( + blockram_template.format(param_str=param_str, top=top), + file=f + ) + for assertion in sim_test.assertions: + print("select {}".format(assertion), file=f) + print("", file=f) + + # prepare simulation tests + test_steps = sim_test.test_steps + if test_steps: + if top == "sync_ram_sdp": + uut_submodule = sync_ram_sdp_submodule + else: + raise NotImplementedError(f"missing submodule header for {top}") + mem_test_vector = "" + for step, test in enumerate(test_steps): + for key, val in test.items(): + key = test_val_map[key] + mem_test_vector += f"\\\n{key}[{step}] = 'h{val:x};" + print( + sim_template.format( + mem_test_vector=mem_test_vector, + uut_submodule=uut_submodule, + param_str=param_str, + vectorlen=len(test_steps) + 2 + ), file=f + ) + # simulation counts for 2 tests + j += 1 + + # increment test counter + j += 1 + if j >= max_j: + f = f.close() + i += 1 + +if f: + f.close() diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v new file mode 100644 index 00000000000..93ba2a31a64 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -0,0 +1,73 @@ +module TB(input clk); + +parameter ADDRESS_WIDTH = 10; +parameter DATA_WIDTH = 36; +parameter VECTORLEN = 16; + +reg rce_a_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH-1:0] ra_a_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0]; + +reg wce_a_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH-1:0] wa_a_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH-1:0] wd_a_testvector [VECTORLEN-1:0]; + +reg rce_b_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH-1:0] ra_b_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0]; + +reg wce_b_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH-1:0] wa_b_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH-1:0] wd_b_testvector [VECTORLEN-1:0]; + +reg [$clog2(VECTORLEN)-1:0] i = 0; + +integer j; +initial begin + for (j = 0; j < VECTORLEN; j = j + 1) begin + rce_a_testvector[j] = 1'b0; + ra_a_testvector[j] = 10'h0; + wce_a_testvector[j] = 1'b0; + wa_a_testvector[j] = 10'h0; + rce_b_testvector[j] = 1'b0; + ra_b_testvector[j] = 10'h0; + wce_b_testvector[j] = 1'b0; + wa_b_testvector[j] = 10'h0; + + end + + `MEM_TEST_VECTOR + +end + + +wire rce_a = rce_a_testvector[i]; +wire [ADDRESS_WIDTH-1:0] ra_a = ra_a_testvector[i]; +wire [DATA_WIDTH-1:0] rq_a; + +wire wce_a = wce_a_testvector[i]; +wire [ADDRESS_WIDTH-1:0] wa_a = wa_a_testvector[i]; +wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i]; + +wire rce_b = rce_b_testvector[i]; +wire [ADDRESS_WIDTH-1:0] ra_b = ra_b_testvector[i]; +wire [DATA_WIDTH-1:0] rq_b; + +wire wce_b = wce_b_testvector[i]; +wire [ADDRESS_WIDTH-1:0] wa_b = wa_b_testvector[i]; +wire [DATA_WIDTH-1:0] wd_b = wd_b_testvector[i]; + +`UUT_SUBMODULE + +always @(posedge clk) begin + if (i < VECTORLEN-1) begin + if (i > 0) begin + if($past(rce_a)) + assert(rq_a == rq_a_expected[i]); + if($past(rce_b)) + assert(rq_b == rq_b_expected[i]); + end + i <= i + 1; + end +end +endmodule From 7f12d0ba95d312e1cfc16b6aa4243430c5b60868 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 1 Dec 2023 17:00:15 +1300 Subject: [PATCH 196/240] QLF_TDP36K: more basic tdp/sdp sim tests Adds TDP submodule to generator. Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests). --- .../quicklogic/qlf_k6n10f/gen_memories.py | 89 ++++++++++++++++++- tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 6 +- 2 files changed, 90 insertions(+), 5 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index ea750b8ed9a..e1d77d9dfd0 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -132,6 +132,26 @@ );\ """ +sync_ram_tdp_submodule = """\ +sync_ram_tdp #(\\ + .ADDRESS_WIDTH(ADDRESS_WIDTH),\\ + .DATA_WIDTH(DATA_WIDTH)\\ +) uut (\\ + .clk_a(clk),\\ + .clk_b(clk),\\ + .write_enable_a(wce_a),\\ + .write_enable_b(wce_b),\\ + .read_enable_a(rce_a),\\ + .read_enable_b(rce_b),\\ + .addr_a(ra_a),\\ + .addr_b(ra_b),\\ + .read_data_a(rq_a),\\ + .read_data_b(rq_b),\\ + .write_data_a(wd_a),\\ + .write_data_b(wd_b)\\ +);\ +""" + @dataclass class TestClass: params: dict[str, int] @@ -155,20 +175,81 @@ class TestClass: } sim_tests: list[TestClass] = [ - TestClass( + TestClass( # basic SDP test + # note that the common SDP model reads every cycle, but the testbench + # still uses the rce signal to check read assertions params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 36}, top="sync_ram_sdp", - assertions=["-assert-count 1 t:TDP36K"], + assertions=[], test_steps=[ {"wce_a": 1, "wa_a": 0x0A, "wd_a": 0xdeadbeef}, {"wce_a": 1, "wa_a": 0xBA, "wd_a": 0x5a5a5a5a}, {"wce_a": 1, "wa_a": 0xFF, "wd_a": 0}, - {"rce_a": 1, "ra_a": 0xA}, + {"rce_a": 1, "ra_a": 0x0A}, {"rq_a": 0xdeadbeef}, {"rce_a": 1, "ra_a": 0xFF}, {"rq_a": 0}, ] ), + TestClass( # SDP read before write + params={"ADDRESS_WIDTH": 4, "DATA_WIDTH": 16}, + top="sync_ram_sdp", + assertions=[], + test_steps=[ + {"wce_a": 1, "wa_a": 0xA, "wd_a": 0x1234}, + {"wce_a": 1, "wa_a": 0xA, "wd_a": 0x5678, "rce_a": 1, "ra_a": 0xA}, + {"rq_a": 0x1234, "rce_a": 1, "ra_a": 0xA}, + {"rq_a": 0x5678}, + ] + ), + TestClass( # basic TDP test + # note that the testbench uses ra and wa, while the common TDP model + # uses a shared address + params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 36}, + top="sync_ram_tdp", + assertions=[], + test_steps=[ + {"wce_a": 1, "ra_a": 0x0A, "wce_b": 1, "ra_b": 0xBA, + "wd_a": 0xdeadbeef, "wd_b": 0x5a5a5a5a}, + {"wce_a": 1, "ra_a": 0xFF, + "wd_a": 0}, + {"rce_a": 1, "ra_a": 0x0A, "rce_b": 1, "ra_b": 0x0A}, + {"rq_a": 0xdeadbeef, "rq_b": 0xdeadbeef}, + {"rce_a": 1, "ra_a": 0xFF, "rce_b": 1, "ra_b": 0xBA}, + {"rq_a": 0, "rq_b": 0x5a5a5a5a}, + ] + ), + TestClass( # TDP with truncation + params={"ADDRESS_WIDTH": 4, "DATA_WIDTH": 16}, + top="sync_ram_tdp", + assertions=[], + test_steps=[ + {"wce_a": 1, "ra_a": 0x0F, "wce_b": 1, "ra_b": 0xBA, + "wd_a": 0xdeadbeef, "wd_b": 0x5a5a5a5a}, + {"wce_a": 1, "ra_a": 0xFF, + "wd_a": 0}, + {"rce_a": 1, "ra_a": 0x0F, "rce_b": 1, "ra_b": 0x0A}, + {"rq_a": 0, "rq_b": 0x00005a5a}, + ] + ), + TestClass( # TDP read before write + # note that the testbench uses rce and wce, while the common TDP model + # uses a single enable for write, with reads on no write + params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 36}, + top="sync_ram_tdp", + assertions=[], + test_steps=[ + {"wce_a": 1, "ra_a": 0x0A, "wce_b": 1, "ra_b": 0xBA, + "wd_a": 0xdeadbeef, "wd_b": 0x5a5a5a5a}, + {"wce_a": 1, "ra_a": 0xBA, "rce_b": 1, "ra_b": 0xBA, + "wd_a": 0xa5a5a5a5}, + { "rq_b": 0x5a5a5a5a}, + {"rce_a": 1, "ra_a": 0x0A, "rce_b": 1, "ra_b": 0x0A}, + {"rq_a": 0xdeadbeef, "rq_b": 0xdeadbeef}, + { "rce_b": 1, "ra_b": 0xBA}, + { "rq_b": 0xa5a5a5a5}, + ] + ), ] for (params, top, assertions) in blockram_tests: @@ -225,6 +306,8 @@ class TestClass: if test_steps: if top == "sync_ram_sdp": uut_submodule = sync_ram_sdp_submodule + elif top == "sync_ram_tdp": + uut_submodule = sync_ram_tdp_submodule else: raise NotImplementedError(f"missing submodule header for {top}") mem_test_vector = "" diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v index 93ba2a31a64..22ff63642ea 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -43,6 +43,7 @@ end wire rce_a = rce_a_testvector[i]; wire [ADDRESS_WIDTH-1:0] ra_a = ra_a_testvector[i]; +wire [DATA_WIDTH-1:0] rq_a_e = rq_a_expected[i]; wire [DATA_WIDTH-1:0] rq_a; wire wce_a = wce_a_testvector[i]; @@ -51,6 +52,7 @@ wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i]; wire rce_b = rce_b_testvector[i]; wire [ADDRESS_WIDTH-1:0] ra_b = ra_b_testvector[i]; +wire [DATA_WIDTH-1:0] rq_b_e = rq_b_expected[i]; wire [DATA_WIDTH-1:0] rq_b; wire wce_b = wce_b_testvector[i]; @@ -63,9 +65,9 @@ always @(posedge clk) begin if (i < VECTORLEN-1) begin if (i > 0) begin if($past(rce_a)) - assert(rq_a == rq_a_expected[i]); + assert(rq_a == rq_a_e); if($past(rce_b)) - assert(rq_b == rq_b_expected[i]); + assert(rq_b == rq_b_e); end i <= i + 1; end From 497cd021af5743c23a90fbe01eb2d1c9c25dedb6 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 1 Dec 2023 17:14:01 +1300 Subject: [PATCH 197/240] QLF_TDP36K: truncation tests matter Expected values are now stored in full precision rather than truncating to the same value as the input. i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read. --- tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v index 22ff63642ea..4572bb976bb 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -3,10 +3,11 @@ module TB(input clk); parameter ADDRESS_WIDTH = 10; parameter DATA_WIDTH = 36; parameter VECTORLEN = 16; +localparam MAX_WIDTH = 36; reg rce_a_testvector [VECTORLEN-1:0]; reg [ADDRESS_WIDTH-1:0] ra_a_testvector [VECTORLEN-1:0]; -reg [DATA_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0]; +reg [MAX_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0]; reg wce_a_testvector [VECTORLEN-1:0]; reg [ADDRESS_WIDTH-1:0] wa_a_testvector [VECTORLEN-1:0]; @@ -14,7 +15,7 @@ reg [DATA_WIDTH-1:0] wd_a_testvector [VECTORLEN-1:0]; reg rce_b_testvector [VECTORLEN-1:0]; reg [ADDRESS_WIDTH-1:0] ra_b_testvector [VECTORLEN-1:0]; -reg [DATA_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0]; +reg [MAX_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0]; reg wce_b_testvector [VECTORLEN-1:0]; reg [ADDRESS_WIDTH-1:0] wa_b_testvector [VECTORLEN-1:0]; @@ -43,7 +44,7 @@ end wire rce_a = rce_a_testvector[i]; wire [ADDRESS_WIDTH-1:0] ra_a = ra_a_testvector[i]; -wire [DATA_WIDTH-1:0] rq_a_e = rq_a_expected[i]; +wire [MAX_WIDTH-1:0] rq_a_e = rq_a_expected[i]; wire [DATA_WIDTH-1:0] rq_a; wire wce_a = wce_a_testvector[i]; @@ -52,7 +53,7 @@ wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i]; wire rce_b = rce_b_testvector[i]; wire [ADDRESS_WIDTH-1:0] ra_b = ra_b_testvector[i]; -wire [DATA_WIDTH-1:0] rq_b_e = rq_b_expected[i]; +wire [MAX_WIDTH-1:0] rq_b_e = rq_b_expected[i]; wire [DATA_WIDTH-1:0] rq_b; wire wce_b = wce_b_testvector[i]; From 0d1668c1ee86c9a14eddfd4bd946ea603bd48fb8 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 1 Dec 2023 20:47:39 +1300 Subject: [PATCH 198/240] QLF_TDP36K: asymmetric simulation tests --- .../quicklogic/qlf_k6n10f/gen_memories.py | 88 +++++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 1 + 2 files changed, 89 insertions(+) diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index e1d77d9dfd0..eddc341c275 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -152,6 +152,38 @@ );\ """ +sync_ram_sdp_wwr_submodule = """\ +sync_ram_sdp_wwr #(\\ + .ADDRESS_WIDTH(ADDRESS_WIDTH),\\ + .DATA_WIDTH(DATA_WIDTH),\\ + .SHIFT_VAL(SHIFT_VAL)\\ +) uut (\\ + .clk_w(clk),\\ + .clk_r(clk),\\ + .write_enable(wce_a),\\ + .data_in(wd_a),\\ + .address_in_w(wa_a),\\ + .address_in_r(ra_a),\\ + .data_out(rq_a)\\ +);\ +""" + +sync_ram_sdp_wrr_submodule = """\ +sync_ram_sdp_wrr #(\\ + .ADDRESS_WIDTH(ADDRESS_WIDTH),\\ + .DATA_WIDTH(DATA_WIDTH),\\ + .SHIFT_VAL(SHIFT_VAL)\\ +) uut (\\ + .clk_w(clk),\\ + .clk_r(clk),\\ + .write_enable(wce_a),\\ + .data_in(wd_a),\\ + .address_in_w(wa_a),\\ + .address_in_r(ra_a),\\ + .data_out(rq_a)\\ +);\ +""" + @dataclass class TestClass: params: dict[str, int] @@ -250,6 +282,58 @@ class TestClass: { "rq_b": 0xa5a5a5a5}, ] ), + TestClass( # 2x wide write + params={"ADDRESS_WIDTH": 11, "DATA_WIDTH": 18, "SHIFT_VAL": 1}, + top="sync_ram_sdp_wwr", + assertions=[], + test_steps=[ + {"wce_a": 1, "wa_a": 0b0000000001, "wd_a": 0xdeadbeef}, + {"rce_a": 0, "ra_a": 0b00000000010}, + {"rq_a": 0xdead}, + {"rce_a": 0, "ra_a": 0b00000000011}, + {"rq_a": 0xbeef}, + ] + ), + TestClass( # 4x wide write + params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 8, "SHIFT_VAL": 2}, + top="sync_ram_sdp_wwr", + assertions=[], + test_steps=[ + {"wce_a": 1, "wa_a": 0b000100001, "wd_a": 0xdeadbeef}, + {"rce_a": 0, "ra_a": 0b00010000100}, + {"rq_a": 0xde}, + {"rce_a": 0, "ra_a": 0b00010000101}, + {"rq_a": 0xad}, + {"rce_a": 0, "ra_a": 0b00010000110}, + {"rq_a": 0xbe}, + {"rce_a": 0, "ra_a": 0b00010000111}, + {"rq_a": 0xef}, + ] + ), + TestClass( # 2x wide read + params={"ADDRESS_WIDTH": 11, "DATA_WIDTH": 18, "SHIFT_VAL": 1}, + top="sync_ram_sdp_wrr", + assertions=[], + test_steps=[ + {"wce_a": 1, "wa_a": 0b00000000010, "wd_a": 0xdead}, + {"wce_a": 1, "wa_a": 0b00000000011, "wd_a": 0xbeef}, + {"rce_a": 0, "ra_a": 0b0000000001}, + {"rq_a": 0xdeadbeef}, + ] + ), + TestClass( # 4x wide read + params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 8, "SHIFT_VAL": 2}, + top="sync_ram_sdp_wrr", + assertions=[], + test_steps=[ + {"wce_a": 1, "wa_a": 0b00010000100, "wd_a": 0xde}, + {"wce_a": 1, "wa_a": 0b00010000101, "wd_a": 0xad}, + {"wce_a": 1, "wa_a": 0b00010000110, "wd_a": 0xbe}, + {"wce_a": 1, "wa_a": 0b00010000111, "wd_a": 0xef}, + {"rce_a": 0, "ra_a": 0b000100001}, + {"rq_a": 0xdeadbeef}, + ] + ), ] for (params, top, assertions) in blockram_tests: @@ -308,6 +392,10 @@ class TestClass: uut_submodule = sync_ram_sdp_submodule elif top == "sync_ram_tdp": uut_submodule = sync_ram_tdp_submodule + elif top == "sync_ram_sdp_wwr": + uut_submodule = sync_ram_sdp_wwr_submodule + elif top == "sync_ram_sdp_wrr": + uut_submodule = sync_ram_sdp_wrr_submodule else: raise NotImplementedError(f"missing submodule header for {top}") mem_test_vector = "" diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v index 4572bb976bb..9a44243f8ba 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -3,6 +3,7 @@ module TB(input clk); parameter ADDRESS_WIDTH = 10; parameter DATA_WIDTH = 36; parameter VECTORLEN = 16; +parameter SHIFT_VAL = 0; localparam MAX_WIDTH = 36; reg rce_a_testvector [VECTORLEN-1:0]; From 509d1765234d207183de81fd66b8eda478d124e6 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 1 Dec 2023 21:16:58 +1300 Subject: [PATCH 199/240] attempting to sim split memory tests and failing --- .../quicklogic/qlf_k6n10f/gen_memories.py | 39 +++++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 32 ++++++++------- 2 files changed, 57 insertions(+), 14 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index eddc341c275..631289800f0 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -113,6 +113,7 @@ EOF read_verilog -defer -formal mem_tb.v chparam{param_str} -set VECTORLEN {vectorlen} TB +read_verilog +/quicklogic/qlf_k6n10f/cells_sim.v hierarchy -top TB -check proc sim -clock clk -n {vectorlen} -assert @@ -184,6 +185,28 @@ );\ """ +double_sync_ram_sdp_submodule = """\ +double_sync_ram_sdp #(\\ + .ADDRESS_WIDTH_A(ADDRESS_WIDTH_A),\\ + .DATA_WIDTH_A(DATA_WIDTH_A),\\ + .ADDRESS_WIDTH_B(ADDRESS_WIDTH_B),\\ + .DATA_WIDTH_B(DATA_WIDTH_B)\\ +) uut (\\ + .clk_a(clk),\\ + .write_enable_a(wce_a),\\ + .address_in_w_a(wa_a),\\ + .address_in_r_a(ra_a),\\ + .data_in_a(wd_a),\\ + .data_out_b(rq_b),\\ + .clk_b(clk),\\ + .write_enable_b(wce_b),\\ + .address_in_w_b(wa_b),\\ + .address_in_r_b(ra_b),\\ + .data_in_b(wd_b),\\ + .data_out_b(rq_b)\\ +);\ +""" + @dataclass class TestClass: params: dict[str, int] @@ -334,6 +357,20 @@ class TestClass: {"rq_a": 0xdeadbeef}, ] ), + TestClass( # basic split SDP test + params={"ADDRESS_WIDTH_A": 10, "DATA_WIDTH_A": 16, + "ADDRESS_WIDTH_B": 10, "DATA_WIDTH_B": 16}, + top="double_sync_ram_sdp", + assertions=[], + test_steps=[ + {"wce_a": 1, "wa_a": 0x0A, "wce_b": 1, "wa_b": 0xBA, + "wd_a": 0x1234, "wd_b": 0x4567}, + {"wce_a": 1, "wa_a": 0xFF, "wce_b": 1, "wa_b": 0x0A, + "wd_a": 0, "wd_b": 0xbeef}, + {"rce_a": 1, "ra_a": 0x0A, "rce_b": 1, "ra_b": 0x0A}, + {"rq_a": 0x1234, "rq_b": 0xbeef}, + ] + ), ] for (params, top, assertions) in blockram_tests: @@ -396,6 +433,8 @@ class TestClass: uut_submodule = sync_ram_sdp_wwr_submodule elif top == "sync_ram_sdp_wrr": uut_submodule = sync_ram_sdp_wrr_submodule + elif top == "double_sync_ram_sdp": + uut_submodule = double_sync_ram_sdp_submodule else: raise NotImplementedError(f"missing submodule header for {top}") mem_test_vector = "" diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v index 9a44243f8ba..cb64269a17c 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -1,26 +1,30 @@ module TB(input clk); parameter ADDRESS_WIDTH = 10; +parameter ADDRESS_WIDTH_A = ADDRESS_WIDTH; +parameter ADDRESS_WIDTH_B = ADDRESS_WIDTH; parameter DATA_WIDTH = 36; +parameter DATA_WIDTH_A = DATA_WIDTH; +parameter DATA_WIDTH_B = DATA_WIDTH; parameter VECTORLEN = 16; parameter SHIFT_VAL = 0; localparam MAX_WIDTH = 36; reg rce_a_testvector [VECTORLEN-1:0]; -reg [ADDRESS_WIDTH-1:0] ra_a_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH_A-1:0] ra_a_testvector [VECTORLEN-1:0]; reg [MAX_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0]; reg wce_a_testvector [VECTORLEN-1:0]; -reg [ADDRESS_WIDTH-1:0] wa_a_testvector [VECTORLEN-1:0]; -reg [DATA_WIDTH-1:0] wd_a_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH_A-1:0] wa_a_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH_A-1:0] wd_a_testvector [VECTORLEN-1:0]; reg rce_b_testvector [VECTORLEN-1:0]; -reg [ADDRESS_WIDTH-1:0] ra_b_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH_B-1:0] ra_b_testvector [VECTORLEN-1:0]; reg [MAX_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0]; reg wce_b_testvector [VECTORLEN-1:0]; -reg [ADDRESS_WIDTH-1:0] wa_b_testvector [VECTORLEN-1:0]; -reg [DATA_WIDTH-1:0] wd_b_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH_B-1:0] wa_b_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH_B-1:0] wd_b_testvector [VECTORLEN-1:0]; reg [$clog2(VECTORLEN)-1:0] i = 0; @@ -44,22 +48,22 @@ end wire rce_a = rce_a_testvector[i]; -wire [ADDRESS_WIDTH-1:0] ra_a = ra_a_testvector[i]; +wire [ADDRESS_WIDTH_A-1:0] ra_a = ra_a_testvector[i]; wire [MAX_WIDTH-1:0] rq_a_e = rq_a_expected[i]; -wire [DATA_WIDTH-1:0] rq_a; +wire [DATA_WIDTH_A-1:0] rq_a; wire wce_a = wce_a_testvector[i]; -wire [ADDRESS_WIDTH-1:0] wa_a = wa_a_testvector[i]; -wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i]; +wire [ADDRESS_WIDTH_A-1:0] wa_a = wa_a_testvector[i]; +wire [DATA_WIDTH_A-1:0] wd_a = wd_a_testvector[i]; wire rce_b = rce_b_testvector[i]; -wire [ADDRESS_WIDTH-1:0] ra_b = ra_b_testvector[i]; +wire [ADDRESS_WIDTH_B-1:0] ra_b = ra_b_testvector[i]; wire [MAX_WIDTH-1:0] rq_b_e = rq_b_expected[i]; -wire [DATA_WIDTH-1:0] rq_b; +wire [DATA_WIDTH_B-1:0] rq_b; wire wce_b = wce_b_testvector[i]; -wire [ADDRESS_WIDTH-1:0] wa_b = wa_b_testvector[i]; -wire [DATA_WIDTH-1:0] wd_b = wd_b_testvector[i]; +wire [ADDRESS_WIDTH_B-1:0] wa_b = wa_b_testvector[i]; +wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i]; `UUT_SUBMODULE From 3c5b0ab1641409a09252b488c7f08ced631753d8 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Fri, 1 Dec 2023 10:47:39 +0100 Subject: [PATCH 200/240] fix test setup for synth_quicklogic memory tests --- tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys | 5 +- .../arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v | 2 +- .../quicklogic/qlf_k6n10f/gen_memories.py | 47 +++++++------------ tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 2 +- tests/arch/quicklogic/qlf_k6n10f/run-test.sh | 1 + 5 files changed, 21 insertions(+), 36 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys index 635769cc0d2..ccce5882f65 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys +++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys @@ -1,8 +1,7 @@ read_verilog bram_tdp.v hierarchy -top BRAM_TDP synth_quicklogic -family qlf_k6n10f -read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v read_verilog -formal bram_tdp_tb.v -hierarchy -top TB -proc +read_verilog -overwrite +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v +prep -top TB sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v index 5d4fbe06779..351c334d035 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v @@ -57,7 +57,7 @@ wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i]; wire rce_b = rce_b_testvector[i]; wire [ADDR_WIDTH-1:0] ra_b = ra_b_testvector[i]; -wire [DATA_WIDTH-1:0] rq_b = rq_b_expected[i]; +wire [DATA_WIDTH-1:0] rq_b; wire wce_b = wce_b_testvector[i]; wire [ADDR_WIDTH-1:0] wa_b = wa_b_testvector[i]; diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index 631289800f0..1d596b3c731 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -4,11 +4,11 @@ blockram_template = """# ====================================== +log ** GENERATING TEST {top} WITH PARAMS{param_str} design -reset; read_verilog -defer ../../common/blockram.v chparam{param_str} {top} hierarchy -top {top} -synth_quicklogic -family qlf_k6n10f -top {top}; cd {top} -log ** TESTING {top} WITH PARAMS{param_str}\ +synth_quicklogic -family qlf_k6n10f -top {top} """ blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [ # TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work @@ -103,8 +103,10 @@ ] sim_template = """\ -cd -read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v +design -stash synthesized +design -copy-from synthesized -as {top}_synth {top} +design -delete synthesized +read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v read_verilog < Date: Fri, 1 Dec 2023 14:28:50 +0100 Subject: [PATCH 201/240] remove example test --- tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v | 77 --------------- tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys | 7 -- .../arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v | 99 ------------------- 3 files changed, 183 deletions(-) delete mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v delete mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys delete mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v deleted file mode 100644 index 536cce992f0..00000000000 --- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v +++ /dev/null @@ -1,77 +0,0 @@ -// Copyright 2020-2022 F4PGA Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 - -module BRAM_TDP #(parameter AWIDTH = 10, -parameter DWIDTH = 36)( - clk_a, - rce_a, - ra_a, - rq_a, - wce_a, - wa_a, - wd_a, - - clk_b, - rce_b, - ra_b, - rq_b, - wce_b, - wa_b, - wd_b -); - - input clk_a; - input rce_a; - input [AWIDTH-1:0] ra_a; - output reg [DWIDTH-1:0] rq_a; - input wce_a; - input [AWIDTH-1:0] wa_a; - input [DWIDTH-1:0] wd_a; - - input clk_b; - input rce_b; - input [AWIDTH-1:0] ra_b; - output reg [DWIDTH-1:0] rq_b; - input wce_b; - input [AWIDTH-1:0] wa_b; - input [DWIDTH-1:0] wd_b; - - (* no_rw_check = 1 *) - reg [DWIDTH-1:0] memory[0:(1< 0) begin - if($past(rce_a)) - assert(rq_a == rq_a_expected[i]); - if($past(rce_b)) - assert(rq_b == rq_b_expected[i]); - end - i <= i + 1; - end -end -endmodule \ No newline at end of file From 215a777eb32ea2c1d688b800af50e13c2851417b Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 4 Dec 2023 09:24:19 +1300 Subject: [PATCH 202/240] qlf_tests: minor adjustment Renamed python script so that it sits next to the testbench file when alphabetically sorted. Reverted `MAX_WIDTH` to full precision for truncation testing. --- .../quicklogic/qlf_k6n10f/{gen_memories.py => mem_gen.py} | 0 tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 5 ++++- tests/arch/quicklogic/qlf_k6n10f/run-test.sh | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) rename tests/arch/quicklogic/qlf_k6n10f/{gen_memories.py => mem_gen.py} (100%) diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py similarity index 100% rename from tests/arch/quicklogic/qlf_k6n10f/gen_memories.py rename to tests/arch/quicklogic/qlf_k6n10f/mem_gen.py diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v index 89e41f8bc32..a0d15bd6222 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -8,7 +8,10 @@ parameter DATA_WIDTH_A = DATA_WIDTH; parameter DATA_WIDTH_B = DATA_WIDTH; parameter VECTORLEN = 16; parameter SHIFT_VAL = 0; -localparam MAX_WIDTH = DATA_WIDTH; + +// intentionally keep expected values at full width precision to allow testing +// of truncation +localparam MAX_WIDTH = 36; reg rce_a_testvector [VECTORLEN-1:0]; reg [ADDRESS_WIDTH_A-1:0] ra_a_testvector [VECTORLEN-1:0]; diff --git a/tests/arch/quicklogic/qlf_k6n10f/run-test.sh b/tests/arch/quicklogic/qlf_k6n10f/run-test.sh index be16b782916..2fe33619418 100755 --- a/tests/arch/quicklogic/qlf_k6n10f/run-test.sh +++ b/tests/arch/quicklogic/qlf_k6n10f/run-test.sh @@ -1,5 +1,5 @@ #!/usr/bin/env bash set -eu -python3 gen_memories.py +python3 mem_gen.py source ../../../gen-tests-makefile.sh run_tests --yosys-scripts --bash From 97354782c088f2cad3b4bae09c31b9ec32aac896 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 4 Dec 2023 11:16:50 +1300 Subject: [PATCH 203/240] Adding double_sync_ram_tdp to blockram.v --- tests/arch/common/blockram.v | 65 ++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index 09bc7786346..4a9d45a6b4a 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -181,3 +181,68 @@ module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_tdp +module double_sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) +( + input wire clk_a_0, + input wire write_enable_a_0, read_enable_a_0, + input wire [DATA_WIDTH-1:0] write_data_a_0, + input wire [ADDRESS_WIDTH-1:0] addr_a_0, + output wire [DATA_WIDTH-1:0] read_data_a_0, + + input wire clk_a_1, + input wire write_enable_a_1, read_enable_a_1, + input wire [DATA_WIDTH-1:0] write_data_a_1, + input wire [ADDRESS_WIDTH-1:0] addr_a_1, + output wire [DATA_WIDTH-1:0] read_data_a_1, + + input wire clk_b_0, + input wire write_enable_b_0, read_enable_b_0, + input wire [DATA_WIDTH-1:0] write_data_b_0, + input wire [ADDRESS_WIDTH-1:0] addr_b_0, + output wire [DATA_WIDTH-1:0] read_data_b_0, + + input wire clk_b_1, + input wire write_enable_b_1, read_enable_b_1, + input wire [DATA_WIDTH-1:0] write_data_b_1, + input wire [ADDRESS_WIDTH-1:0] addr_b_1, + output wire [DATA_WIDTH-1:0] read_data_b_1 +); + + sync_ram_tdp #( + .DATA_WIDTH(DATA_WIDTH), + .ADDRESS_WIDTH(ADDRESS_WIDTH) + ) ram_0 ( + .clk_a(clk_a_0), + .clk_b(clk_b_0), + .write_enable_a(write_enable_a_0), + .write_enable_b(write_enable_b_0), + .read_enable_a(read_enable_a_0), + .read_enable_b(read_enable_b_0), + .write_data_a(write_data_a_0), + .write_data_b(write_data_b_0), + .addr_a(addr_a_0), + .addr_b(addr_b_0), + .read_data_a(read_data_a_0), + .read_data_b(read_data_b_0) + ); + + sync_ram_tdp #( + .DATA_WIDTH(DATA_WIDTH), + .ADDRESS_WIDTH(ADDRESS_WIDTH) + ) ram_1 ( + .clk_a(clk_a_1), + .clk_b(clk_b_1), + .write_enable_a(write_enable_a_1), + .write_enable_b(write_enable_b_1), + .read_enable_a(read_enable_a_1), + .read_enable_b(read_enable_b_1), + .write_data_a(write_data_a_1), + .write_data_b(write_data_b_1), + .addr_a(addr_a_1), + .addr_b(addr_b_1), + .read_data_a(read_data_a_1), + .read_data_b(read_data_b_1) + ); + +endmodule // double_sync_ram_tdp + From e5c32f399a5efc49028f791315f7d87a7bff2dc8 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 4 Dec 2023 11:17:18 +1300 Subject: [PATCH 204/240] synth_quicklogic: Testing double_sync_ram_tdp --- tests/arch/quicklogic/qlf_k6n10f/mem_gen.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py b/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py index 1d596b3c731..226d6a1a0d7 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py @@ -77,9 +77,20 @@ ([("ADDRESS_WIDTH_A", 9), ("DATA_WIDTH_A", 36), ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 9)], "double_sync_ram_sdp", ["-assert-count 2 t:TDP36K"]), + # also for tdp + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 16)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 8)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 4)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 2)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 14), ("DATA_WIDTH", 1)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + # still only if data width is <= 18 + ([("ADDRESS_WIDTH", 9), ("DATA_WIDTH", 36)], "double_sync_ram_tdp", ["-assert-count 2 t:TDP36K"]), + # sharing a TDP36K sets is_split=1 ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]), # an unshared TDP36K sets is_split=0 ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), @@ -88,6 +99,9 @@ ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("DATA_WIDTH_B", 18), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=18 %i", "-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "double_sync_ram_tdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=18 %i", + "-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16), ("DATA_WIDTH_B", 8), ("ADDRESS_WIDTH_B", 11)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=9 %i " + "t:TDP36K a:port_a2_width=18 %i a:port_a1_width=9 %i %u", From 22cc4aff5116fe51b63c0e78a381f53091044444 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 4 Dec 2023 15:47:50 +0100 Subject: [PATCH 205/240] quicklogic: Test TDP36K inference with initial data --- .../quicklogic/qlf_k6n10f/libmap_brams_map.v | 1 + tests/arch/quicklogic/qlf_k6n10f/meminit.v | 50 +++++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/meminit.ys | 14 ++++++ 3 files changed, 65 insertions(+) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/meminit.v create mode 100644 tests/arch/quicklogic/qlf_k6n10f/meminit.ys diff --git a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v index f4f4420c1a2..3a5641bb880 100644 --- a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v @@ -178,6 +178,7 @@ defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, (* is_inferred = 1 *) (* is_split = 0 *) +(* was_split_candidate = OPTION_SPLIT *) (* port_a_width = PORT_A_WIDTH *) (* port_b_width = PORT_B_WIDTH *) TDP36K #( diff --git a/tests/arch/quicklogic/qlf_k6n10f/meminit.v b/tests/arch/quicklogic/qlf_k6n10f/meminit.v new file mode 100644 index 00000000000..46a7dcac710 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/meminit.v @@ -0,0 +1,50 @@ +module top(clk); +parameter DEPTH_LOG2 = 10; +parameter WIDTH = 36; +parameter PRIME = 237481091; +localparam DEPTH = 2**DEPTH_LOG2; + +input wire clk; + +(* syn_ramstyle = "block_ram" *) +reg [WIDTH-1:0] mem [DEPTH-1:0]; + +integer i; +initial begin + for (i = 0; i < DEPTH; i = i + 1) begin + // Make up data by multiplying a large prime with the address, + // then cropping and retaining the lower bits + mem[i] = PRIME * i; + end +end + +reg [DEPTH_LOG2-1:0] counter = 0; +reg done = 1'b0; + +reg did_read = 1'b0; +reg [DEPTH_LOG2-1:0] read_addr; +reg [WIDTH-1:0] read_val; + +always @(posedge clk) begin + if (!done) begin + did_read <= 1'b1; + read_addr <= counter; + read_val <= mem[counter]; + end else begin + did_read <= 1'b0; + end + + if (!done) + counter = counter + 1; + if (counter == 0) + done = 1; +end + +wire [WIDTH-1:0] expect_val = PRIME * read_addr; +always @(posedge clk) begin + if (did_read) begin + $display("addr %x expected %x actual %x", read_addr, expect_val, read_val); + assert(read_val == expect_val); + end +end +endmodule diff --git a/tests/arch/quicklogic/qlf_k6n10f/meminit.ys b/tests/arch/quicklogic/qlf_k6n10f/meminit.ys new file mode 100644 index 00000000000..2949e1590d9 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/meminit.ys @@ -0,0 +1,14 @@ +read_verilog -sv meminit.v +chparam -set DEPTH_LOG2 3 -set WIDTH 36 +prep +opt_dff +prep -rdff +synth_quicklogic -family qlf_k6n10f -run map_bram:map_bram +select -assert-none t:$mem_v2 t:$mem +select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K a:is_split=0 %i +select -assert-count 1 t:TDP36K a:was_split_candidate=0 %i +read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v +prep +hierarchy -top top +sim -assert -q -n 12 -clock clk From 96fecf0716ed07897dbc87379baa3cdd0b1f0748 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 4 Dec 2023 16:37:01 +0100 Subject: [PATCH 206/240] Revert "Add attributes to module instantiation" This reverts commit 8f207eed1baf85ad185c7139729b10f9756a0041. --- frontends/verific/verific.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ce687601fec..9737fde89c2 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1980,7 +1980,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma } RTLIL::Cell *cell = module->addCell(inst_name, inst_type); - import_attributes(cell->attributes, inst); if (inst->IsPrimitive() && mode_keep) cell->attributes[ID::keep] = 1; From e0fc48e196353a245119f93f2136712da24fe5ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 4 Dec 2023 18:07:08 +0100 Subject: [PATCH 207/240] quicklogic: Generate `bram_types_sim.v` at build time --- techlibs/quicklogic/Makefile.inc | 5 +- techlibs/quicklogic/qlf_k6n10f/.gitignore | 1 + .../quicklogic/qlf_k6n10f/bram_types_sim.v | 73374 ---------------- 3 files changed, 5 insertions(+), 73375 deletions(-) create mode 100644 techlibs/quicklogic/qlf_k6n10f/.gitignore delete mode 100644 techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index 58dfc5b45f2..054f272a803 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,6 +1,9 @@ %_pm.h: passes/pmgen/pmgen.py %.pmg $(P) mkdir -p pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^) +techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v: techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py + $(P) $(PYTHON_EXECUTABLE) $^ $@ + OBJS += techlibs/quicklogic/synth_quicklogic.o OBJS += techlibs/quicklogic/ql_bram_merge.o OBJS += techlibs/quicklogic/ql_bram_types.o @@ -10,7 +13,7 @@ OBJS += techlibs/quicklogic/ql_dsp_io_regs.o # -------------------------------------- OBJS += techlibs/quicklogic/ql_dsp_macc.o -GENFILES += techlibs/quicklogic/ql_dsp_macc_pm.h +GENFILES += techlibs/quicklogic/ql_dsp_macc_pm.h techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v techlibs/quicklogic/ql_dsp_macc.o: techlibs/quicklogic/ql_dsp_macc_pm.h $(eval $(call add_extra_objs,techlibs/quicklogic/ql_dsp_macc_pm.h)) diff --git a/techlibs/quicklogic/qlf_k6n10f/.gitignore b/techlibs/quicklogic/qlf_k6n10f/.gitignore new file mode 100644 index 00000000000..b5ba978ce2a --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/.gitignore @@ -0,0 +1 @@ +/bram_types_sim.v diff --git a/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v b/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v deleted file mode 100644 index 39e59d43f08..00000000000 --- a/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v +++ /dev/null @@ -1,73374 +0,0 @@ -// **AUTOGENERATED FILE** **DO NOT EDIT** -// Generated by generate_bram_types_sim.py at 2023-08-17 16:34:43.930013+00:00 -`timescale 1ns /10ps - -module TDP36K_BRAM_A_X1_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X1_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X1_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X1_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X1_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X1_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X2_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X2_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X2_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X2_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X2_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X2_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X4_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X4_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X4_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X4_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X4_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X4_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X9_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X9_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X9_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X9_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X9_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X9_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X18_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X18_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X18_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X18_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X18_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X18_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X36_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X36_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X36_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X36_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X36_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A_X36_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule - -module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif -endmodule From 2ffea67b043fcde3854618aca01a8aed0f41ec56 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 5 Dec 2023 00:16:14 +0000 Subject: [PATCH 208/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index c3d3f57eac8..6b7ba917480 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.35+58 +YOSYS_VER := 0.35+102 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 8f07a0d8404f63349d8d3111217b73c9eafbd667 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 5 Dec 2023 08:55:12 +0100 Subject: [PATCH 209/240] Release version 0.36 --- CHANGELOG | 24 +++++++++++++++++++++++- Makefile | 4 ++-- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 9bf1d9e2b1d..75c954f206f 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,12 +2,34 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.35 .. Yosys 0.36-dev +Yosys 0.35 .. Yosys 0.36 -------------------------- * New commands and options - Added option "--" to pass arguments down to tcl when using -c option. - Added ability on MacOS and Windows to pass options after arguments on cli. + - Added option "-cmp2softlogic" to synth_lattice. + - Added option "-lowpower" to "booth" pass. + + * QuickLogic support + - Added "K6N10f" support. + - Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to + "synth_quicklogic" pass. + - Added "ql_bram_merge" pass to merge 18K BRAM cells into TDP36K. + - Added "ql_bram_types" pass to change TDP36K depending on configuration. + - Added "ql_dsp_io_regs" pass to update QL_DSP2 depending on configuration. + - Added "ql_dsp_macc" pass to infer multiplier-accumulator DSP cells. + - Added "ql_dsp_simd" pass to merge DSP pairs to operate in SIMD mode. + + * ECP5,iCE40 and Gowin support + - Enabled abc9 by default, added "-noabc9" option to disable. + + * MachXO3 support + - Quality of results improvements. + - Enabled "booth" pass by default for it in "synth_lattice". + * Various + - Improved "peepopt" by adding shiftadd pattern support. + - Added "--incremental" mode to smtbmc. Yosys 0.34 .. Yosys 0.35 -------------------------- diff --git a/Makefile b/Makefile index 6b7ba917480..3ac96e2f12b 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.35+102 +YOSYS_VER := 0.36 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -157,7 +157,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline cc31c6e.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline cc31c6e.. | wc -l`/;" Makefile # set 'ABCREV = default' to use abc/ as it is # From 0ccff570622b8141bd5c1ea48c94430f91030512 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 5 Dec 2023 08:58:28 +0100 Subject: [PATCH 210/240] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 75c954f206f..4fb60904ae5 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.36 .. Yosys 0.37-dev +-------------------------- + Yosys 0.35 .. Yosys 0.36 -------------------------- * New commands and options diff --git a/Makefile b/Makefile index 3ac96e2f12b..0a7eeb7c595 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.36 +YOSYS_VER := 0.36+0 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -157,7 +157,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: -# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline cc31c6e.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 8f07a0d.. | wc -l`/;" Makefile # set 'ABCREV = default' to use abc/ as it is # From 16ea497d7cdde1c33374efb1d0268d3ee5c4aec9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 5 Dec 2023 18:29:14 +0100 Subject: [PATCH 211/240] pmgen: Have a single make pattern Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode the other, and in some conditions there were build races as to whether the target directory for the generated header would exist. Instead have a single rule which is properly generalized. --- passes/pmgen/Makefile.inc | 2 +- techlibs/quicklogic/Makefile.inc | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index 884e1252224..ed872b7212d 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -1,5 +1,5 @@ %_pm.h: passes/pmgen/pmgen.py %.pmg - $(P) mkdir -p passes/pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^) + $(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^) # -------------------------------------- diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index 054f272a803..8ec8e3e8da8 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,6 +1,3 @@ -%_pm.h: passes/pmgen/pmgen.py %.pmg - $(P) mkdir -p pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^) - techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v: techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py $(P) $(PYTHON_EXECUTABLE) $^ $@ From a530321042c53d19eb170d7a4085d629734be41c Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 6 Dec 2023 00:16:15 +0000 Subject: [PATCH 212/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 0a7eeb7c595..6fd3ac55557 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.36+0 +YOSYS_VER := 0.36+3 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From d71dd5b9bb0257cef794f575569c2d3307202656 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 6 Dec 2023 09:11:51 +0100 Subject: [PATCH 213/240] Fix out of tree build --- techlibs/quicklogic/ql_dsp_macc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc index b99b32b95cb..f0669da6c9b 100644 --- a/techlibs/quicklogic/ql_dsp_macc.cc +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#include "ql_dsp_macc_pm.h" +#include "techlibs/quicklogic/ql_dsp_macc_pm.h" // ============================================================================ From 56abf92b855b30bd0dcc850032e5dc0dfd94890d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 6 Dec 2023 09:19:11 +0100 Subject: [PATCH 214/240] Add WASI CI build --- .github/workflows/wasi.yml | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 .github/workflows/wasi.yml diff --git a/.github/workflows/wasi.yml b/.github/workflows/wasi.yml new file mode 100644 index 00000000000..74900c38822 --- /dev/null +++ b/.github/workflows/wasi.yml @@ -0,0 +1,30 @@ +name: WASI Build + +on: [push, pull_request] + +jobs: + wasi: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + - name: Build + run: | + WASI_SDK=wasi-sdk-19.0 + WASI_SDK_URL=https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/wasi-sdk-19.0-linux.tar.gz + if ! [ -d ${WASI_SDK} ]; then curl -L ${WASI_SDK_URL} | tar xzf -; fi + + mkdir -p build + cat > build/Makefile.conf < Date: Wed, 6 Dec 2023 09:56:35 +0100 Subject: [PATCH 215/240] Fix out of tree build --- techlibs/quicklogic/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index 8ec8e3e8da8..ade1443713c 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,5 +1,5 @@ techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v: techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py - $(P) $(PYTHON_EXECUTABLE) $^ $@ + $(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $^ $@ OBJS += techlibs/quicklogic/synth_quicklogic.o OBJS += techlibs/quicklogic/ql_bram_merge.o @@ -32,7 +32,7 @@ $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_map.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v)) -$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v)) +$(eval $(call add_gen_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_sim.v)) From 6581b5593c01ca208da95b4579f5c131f2bd1a5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 6 Dec 2023 11:59:19 +0100 Subject: [PATCH 216/240] sim: Print hierarchy for failed assertions --- passes/sat/sim.cc | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index a8516470cfe..8c4fadb699b 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -775,6 +775,30 @@ struct SimInstance return did_something; } + static void log_source(RTLIL::AttrObject *src) + { + for (auto src : src->get_strpool_attribute(ID::src)) + log(" %s\n", src.c_str()); + } + + void log_cell_w_hierarchy(std::string opening_verbiage, RTLIL::Cell *cell) + { + log_assert(cell->module == module); + bool has_src = cell->has_attribute(ID::src); + log("%s %s%s\n", opening_verbiage.c_str(), + log_id(cell), has_src ? " at" : ""); + log_source(cell); + + struct SimInstance *sim = this; + while (sim->instance) { + has_src = sim->instance->has_attribute(ID::src); + log(" in instance %s of module %s%s\n", log_id(sim->instance), + log_id(sim->instance->type), has_src ? " at" : ""); + log_source(sim->instance); + sim = sim->parent; + } + } + void update_ph3(bool check_assertions) { for (auto &it : ff_database) @@ -876,10 +900,11 @@ struct SimInstance log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); if (cell->type == ID($assert) && en == State::S1 && a != State::S1) { + log_cell_w_hierarchy("Failed assertion", cell); if (shared->serious_asserts) - log_error("Assert %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); + log_error("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); else - log_warning("Assert %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); + log_warning("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); } } } From 7b74caa5db86a10c152940f76a0b71eeb340f18f Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 6 Dec 2023 18:22:19 +0100 Subject: [PATCH 217/240] peepopt: Fix padding for the peepopt_shiftmul_right pattern The previous version could easily generate a large amount of padding when the constant factor was significantly larger than the width of the shift data input. This could lead to huge amounts of logic being generated before then being optimized away at a huge performance and memory cost. Additionally and more critically, when the input width was not a multiple of the constant factor, the input data was padded with 'x bits to such a multiple before interspersing the 'x padding needed to align the selectable windows to power-of-two offsets. Such a final padding would not be correct for shifts besides $shiftx, and the previous version did attempt to remove that final padding at the end so that the native zero/sign/x-extension behavior of the shift cell would be used, but since the last selectable window also got power-of-two padding appended after the padding the code is trying to remove got added, it did not actually fully remove it in some cases. I changed the code to only add 'x padding between selectable windows, leaving the last selectable window unpadded. This omits the need to add final padding to a multiple of the constant factor in the first place. In turn, that means the only 'x bits added are actually impossible to select. As a side effect no padding is added when the constant factor is equal to or larger than the width of the shift data input, also solving the reported performance bug. This fixes #4056 --- passes/pmgen/peepopt_shiftmul_right.pmg | 19 +++++++----------- tests/various/peepopt.ys | 26 ++++++++++++++++++++++++- 2 files changed, 32 insertions(+), 13 deletions(-) diff --git a/passes/pmgen/peepopt_shiftmul_right.pmg b/passes/pmgen/peepopt_shiftmul_right.pmg index 71e0980234a..108829d4f9d 100644 --- a/passes/pmgen/peepopt_shiftmul_right.pmg +++ b/passes/pmgen/peepopt_shiftmul_right.pmg @@ -82,22 +82,17 @@ code int new_const_factor = 1 << factor_bits; SigSpec padding(State::Sx, new_const_factor-const_factor); SigSpec old_a = port(shift, \A), new_a; - int trunc = 0; - - if (GetSize(old_a) % const_factor != 0) { - trunc = const_factor - GetSize(old_a) % const_factor; - old_a.append(SigSpec(State::Sx, trunc)); - } for (int i = 0; i*const_factor < GetSize(old_a); i++) { - SigSpec slice = old_a.extract(i*const_factor, const_factor); - new_a.append(slice); - new_a.append(padding); + if ((i+1)*const_factor < GetSize(old_a)) { + SigSpec slice = old_a.extract(i*const_factor, const_factor); + new_a.append(slice); + new_a.append(padding); + } else { + new_a.append(old_a.extract_end(i*const_factor)); + } } - if (trunc > 0) - new_a.remove(GetSize(new_a)-trunc, trunc); - SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)}; if (param(shift, \B_SIGNED).as_bool()) new_b.append(State::S0); diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 45e936a21e6..cbbd477e8b1 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -46,7 +46,31 @@ design -import gold -as gold peepopt_shiftmul_2 design -import gate -as gate peepopt_shiftmul_2 miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter -sat -show-public -enable_undef -prove-asserts miter +sat -verify -show-public -enable_undef -prove-asserts miter +cd gate +select -assert-count 1 t:$shr +select -assert-count 1 t:$mul +select -assert-count 0 t:$shr t:$mul %% t:* %D + +#################### + +design -reset +read_verilog <> (S*5); +endmodule +EOT + +prep +design -save gold +peepopt +design -stash gate + +design -import gold -as gold peepopt_shiftmul_3 +design -import gate -as gate peepopt_shiftmul_3 + +miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter +sat -verify -show-public -enable_undef -prove-asserts miter cd gate select -assert-count 1 t:$shr select -assert-count 1 t:$mul From fb4cbfa735e12592653ae74501688e63468ab498 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 7 Dec 2023 00:16:21 +0000 Subject: [PATCH 218/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 6fd3ac55557..4c880a65e76 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.36+3 +YOSYS_VER := 0.36+8 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 44c72e52232e3ad3fb320b70746948c33df4c85f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 7 Dec 2023 14:31:56 +0100 Subject: [PATCH 219/240] python: Fix import in plugin example When a plugin is being loaded from Python source, the binding will be available under import libyosys That is unfortunately different from how a self-standing Python program would import the Yosys interface, which is from pyosys import libyosys Until that is made consistent, at least fix the example to have it working as is. --- examples/python-api/pass.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/python-api/pass.py b/examples/python-api/pass.py index d67cf4a23c5..dbef0a13fb9 100755 --- a/examples/python-api/pass.py +++ b/examples/python-api/pass.py @@ -1,6 +1,6 @@ #!/usr/bin/python3 -from pyosys import libyosys as ys +import libyosys as ys import matplotlib.pyplot as plt import numpy as np From 189064b8da0a5e3718cec83632eac069f677c10f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 9 Dec 2023 18:43:38 +0100 Subject: [PATCH 220/240] rtlil, hashlib: Remove deprecated `std::iterator` usage `std::iterator` has been deprecated in C++17. Yosys is being compiled against the C++11 standard but plugins can opt to compile against a newer one. To silence some deprecation warnings when those plugins are being compiled, replace the `std::iterator` inheritance with the equivalent type declarations. --- kernel/hashlib.h | 35 ++++++++++++++++++++++++++++++----- kernel/rtlil.h | 16 ++++++++++++++-- 2 files changed, 44 insertions(+), 7 deletions(-) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index 9cf43da6ca5..47aba71a834 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -371,7 +371,7 @@ class dict } public: - class const_iterator : public std::iterator> + class const_iterator { friend class dict; protected: @@ -379,6 +379,11 @@ class dict int index; const_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { } public: + typedef std::forward_iterator_tag iterator_category; + typedef std::pair value_type; + typedef ptrdiff_t difference_type; + typedef std::pair* pointer; + typedef std::pair& reference; const_iterator() { } const_iterator operator++() { index--; return *this; } const_iterator operator+=(int amt) { index -= amt; return *this; } @@ -389,7 +394,7 @@ class dict const std::pair *operator->() const { return &ptr->entries[index].udata; } }; - class iterator : public std::iterator> + class iterator { friend class dict; protected: @@ -397,6 +402,11 @@ class dict int index; iterator(dict *ptr, int index) : ptr(ptr), index(index) { } public: + typedef std::forward_iterator_tag iterator_category; + typedef std::pair value_type; + typedef ptrdiff_t difference_type; + typedef std::pair* pointer; + typedef std::pair& reference; iterator() { } iterator operator++() { index--; return *this; } iterator operator+=(int amt) { index -= amt; return *this; } @@ -800,7 +810,7 @@ class pool } public: - class const_iterator : public std::iterator + class const_iterator { friend class pool; protected: @@ -808,6 +818,11 @@ class pool int index; const_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { } public: + typedef std::forward_iterator_tag iterator_category; + typedef K value_type; + typedef ptrdiff_t difference_type; + typedef K* pointer; + typedef K& reference; const_iterator() { } const_iterator operator++() { index--; return *this; } bool operator==(const const_iterator &other) const { return index == other.index; } @@ -816,7 +831,7 @@ class pool const K *operator->() const { return &ptr->entries[index].udata; } }; - class iterator : public std::iterator + class iterator { friend class pool; protected: @@ -824,6 +839,11 @@ class pool int index; iterator(pool *ptr, int index) : ptr(ptr), index(index) { } public: + typedef std::forward_iterator_tag iterator_category; + typedef K value_type; + typedef ptrdiff_t difference_type; + typedef K* pointer; + typedef K& reference; iterator() { } iterator operator++() { index--; return *this; } bool operator==(const iterator &other) const { return index == other.index; } @@ -1021,7 +1041,7 @@ class idict pool database; public: - class const_iterator : public std::iterator + class const_iterator { friend class idict; protected: @@ -1029,6 +1049,11 @@ class idict int index; const_iterator(const idict &container, int index) : container(container), index(index) { } public: + typedef std::forward_iterator_tag iterator_category; + typedef K value_type; + typedef ptrdiff_t difference_type; + typedef K* pointer; + typedef K& reference; const_iterator() { } const_iterator operator++() { index++; return *this; } bool operator==(const const_iterator &other) const { return index == other.index; } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 17853fae163..9af3d41eca6 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -803,8 +803,14 @@ struct RTLIL::SigBit unsigned int hash() const; }; -struct RTLIL::SigSpecIterator : public std::iterator +struct RTLIL::SigSpecIterator { + typedef std::input_iterator_tag iterator_category; + typedef RTLIL::SigSpec value_type; + typedef ptrdiff_t difference_type; + typedef RTLIL::SigSpec* pointer; + typedef RTLIL::SigSpec& reference; + RTLIL::SigSpec *sig_p; int index; @@ -814,8 +820,14 @@ struct RTLIL::SigSpecIterator : public std::iterator +struct RTLIL::SigSpecConstIterator { + typedef std::input_iterator_tag iterator_category; + typedef RTLIL::SigSpec value_type; + typedef ptrdiff_t difference_type; + typedef RTLIL::SigSpec* pointer; + typedef RTLIL::SigSpec& reference; + const RTLIL::SigSpec *sig_p; int index; From 80b8cd19c49c1a2b1ae4d2cd0acdd17b7c4a318a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 9 Dec 2023 18:48:30 +0100 Subject: [PATCH 221/240] rtlil: Fix value type for iterator over `SigSpec` When we are iterating over a `SigSpec`, the visited values will be of type `SigBit` (as is the return type of `operator*()`). Account for that in the publicly declared types. --- kernel/rtlil.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 9af3d41eca6..d419872c66a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -806,10 +806,10 @@ struct RTLIL::SigBit struct RTLIL::SigSpecIterator { typedef std::input_iterator_tag iterator_category; - typedef RTLIL::SigSpec value_type; + typedef RTLIL::SigBit value_type; typedef ptrdiff_t difference_type; - typedef RTLIL::SigSpec* pointer; - typedef RTLIL::SigSpec& reference; + typedef RTLIL::SigBit* pointer; + typedef RTLIL::SigBit& reference; RTLIL::SigSpec *sig_p; int index; @@ -823,10 +823,10 @@ struct RTLIL::SigSpecIterator struct RTLIL::SigSpecConstIterator { typedef std::input_iterator_tag iterator_category; - typedef RTLIL::SigSpec value_type; + typedef RTLIL::SigBit value_type; typedef ptrdiff_t difference_type; - typedef RTLIL::SigSpec* pointer; - typedef RTLIL::SigSpec& reference; + typedef RTLIL::SigBit* pointer; + typedef RTLIL::SigBit& reference; const RTLIL::SigSpec *sig_p; int index; From 99c8143ded6120692ea509fa55d31da0826e65b8 Mon Sep 17 00:00:00 2001 From: Merry Date: Sat, 9 Dec 2023 14:07:54 +0000 Subject: [PATCH 222/240] cxxrtl: Remove redundant divmod --- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 92 +------------------------ 1 file changed, 3 insertions(+), 89 deletions(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index c1cc81e44a2..bc171717f10 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -519,14 +519,6 @@ struct value : public expr_base> { return count; } - size_t chunks_used() const { - for (size_t n = chunks; n > 0; n--) { - if (data[n - 1] != 0) - return n; - } - return 0; - } - template std::pair, bool /*CarryOut*/> alu(const value &other) const { value result; @@ -584,84 +576,6 @@ struct value : public expr_base> { result.data[result.chunks - 1] &= result.msb_mask; return result; } - - // parallel to BigUnsigned::divideWithRemainder; quotient is stored in q, - // *this is left with the remainder. See that function for commentary describing - // how/why this works. - void divideWithRemainder(const value &b, value &q) { - assert(this != &q); - - if (this == &b || &q == &b) { - value tmpB(b); - divideWithRemainder(tmpB, q); - return; - } - - q = value {0u}; - - size_t blen = b.chunks_used(); - if (blen == 0) { - return; - } - - size_t len = chunks_used(); - if (len < blen) { - return; - } - - size_t i, j, k; - size_t i2; - chunk_t temp; - bool borrowIn, borrowOut; - - size_t origLen = len; - len++; - chunk::type blk[len]; - std::copy(data, data + origLen, blk); - blk[origLen] = 0; - chunk::type subtractBuf[len]; - std::fill(subtractBuf, subtractBuf + len, 0); - - size_t qlen = origLen - blen + 1; - - i = qlen; - while (i > 0) { - i--; - i2 = chunk::bits; - while (i2 > 0) { - i2--; - for (j = 0, k = i, borrowIn = false; j <= blen; j++, k++) { - temp = blk[k] - getShiftedBlock(b, j, i2); - borrowOut = (temp > blk[k]); - if (borrowIn) { - borrowOut |= (temp == 0); - temp--; - } - subtractBuf[k] = temp; - borrowIn = borrowOut; - } - for (; k < origLen && borrowIn; k++) { - borrowIn = (blk[k] == 0); - subtractBuf[k] = blk[k] - 1; - } - if (!borrowIn) { - q.data[i] |= (chunk::type(1) << i2); - while (k > i) { - k--; - blk[k] = subtractBuf[k]; - } - } - } - } - - std::copy(blk, blk + origLen, data); - } - - static chunk::type getShiftedBlock(const value &num, size_t x, size_t y) { - chunk::type part1 = (x == 0 || y == 0) ? 0 : (num.data[x - 1] >> (chunk::bits - y)); - chunk::type part2 = (x == num.chunks) ? 0 : (num.data[x] << y); - return part1 | part2; - } }; // Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here. @@ -849,9 +763,9 @@ std::ostream &operator<<(std::ostream &os, const value_formatted &vf) if (val.is_zero()) buf += '0'; while (!val.is_zero()) { - value quotient; - val.divideWithRemainder(value{10u}, quotient); - buf += '0' + val.template trunc<(Bits > 4 ? 4 : Bits)>().val().template get(); + value quotient, remainder; + std::tie(quotient, remainder) = val.template divmod_uu(value{10u}); + buf += '0' + remainder.template trunc<(Bits > 4 ? 4 : Bits)>().val().template get(); val = quotient; } if (negative || vf.plus) From 0681baae19283e52f3343e1362e49d9d933a753c Mon Sep 17 00:00:00 2001 From: Merry Date: Sat, 9 Dec 2023 14:37:53 +0000 Subject: [PATCH 223/240] cxxrtl: Extract divmod algorithm into value --- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 65 ++++++++++++++++--------- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index bc171717f10..bd4affc3035 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -576,6 +576,37 @@ struct value : public expr_base> { result.data[result.chunks - 1] &= result.msb_mask; return result; } + + std::pair, value> udivmod(value divisor) const { + value quotient; + value dividend = *this; + if (dividend.ucmp(divisor)) + return {/*quotient=*/value{0u}, /*remainder=*/dividend}; + uint32_t divisor_shift = dividend.ctlz() - divisor.ctlz(); + divisor = divisor.shl(value{divisor_shift}); + for (size_t step = 0; step <= divisor_shift; step++) { + quotient = quotient.shl(value{1u}); + if (!dividend.ucmp(divisor)) { + dividend = dividend.sub(divisor); + quotient.set_bit(0, true); + } + divisor = divisor.shr(value{1u}); + } + return {quotient, /*remainder=*/dividend}; + } + + std::pair, value> sdivmod(const value &other) const { + value quotient; + value remainder; + value dividend = sext(); + value divisor = other.template sext(); + if (dividend.is_neg()) dividend = dividend.neg(); + if (divisor.is_neg()) divisor = divisor.neg(); + std::tie(quotient, remainder) = dividend.udivmod(divisor); + if (dividend.is_neg() != divisor.is_neg()) quotient = quotient.neg(); + if (dividend.is_neg()) remainder = remainder.neg(); + return {quotient.template trunc(), remainder.template trunc()}; + } }; // Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here. @@ -764,7 +795,7 @@ std::ostream &operator<<(std::ostream &os, const value_formatted &vf) buf += '0'; while (!val.is_zero()) { value quotient, remainder; - std::tie(quotient, remainder) = val.template divmod_uu(value{10u}); + std::tie(quotient, remainder) = val.udivmod(value{10u}); buf += '0' + remainder.template trunc<(Bits > 4 ? 4 : Bits)>().val().template get(); val = quotient; } @@ -1649,35 +1680,23 @@ CXXRTL_ALWAYS_INLINE std::pair, value> divmod_uu(const value &a, const value &b) { constexpr size_t Bits = max(BitsY, max(BitsA, BitsB)); value quotient; + value remainder; value dividend = a.template zext(); value divisor = b.template zext(); - if (dividend.ucmp(divisor)) - return {/*quotient=*/value { 0u }, /*remainder=*/dividend.template trunc()}; - uint32_t divisor_shift = dividend.ctlz() - divisor.ctlz(); - divisor = divisor.shl(value<32> { divisor_shift }); - for (size_t step = 0; step <= divisor_shift; step++) { - quotient = quotient.shl(value<1> { 1u }); - if (!dividend.ucmp(divisor)) { - dividend = dividend.sub(divisor); - quotient.set_bit(0, true); - } - divisor = divisor.shr(value<1> { 1u }); - } - return {quotient.template trunc(), /*remainder=*/dividend.template trunc()}; + std::tie(quotient, remainder) = dividend.udivmod(divisor); + return {quotient.template trunc(), remainder.template trunc()}; } template CXXRTL_ALWAYS_INLINE std::pair, value> divmod_ss(const value &a, const value &b) { - value ua = a.template sext(); - value ub = b.template sext(); - if (ua.is_neg()) ua = ua.neg(); - if (ub.is_neg()) ub = ub.neg(); - value y, r; - std::tie(y, r) = divmod_uu(ua, ub); - if (a.is_neg() != b.is_neg()) y = y.neg(); - if (a.is_neg()) r = r.neg(); - return {y, r}; + constexpr size_t Bits = max(BitsY, max(BitsA, BitsB)); + value quotient; + value remainder; + value dividend = a.template sext(); + value divisor = b.template sext(); + std::tie(quotient, remainder) = dividend.sdivmod(divisor); + return {quotient.template trunc(), remainder.template trunc()}; } template From 373b651d5b59bdf86cb3e1a59458fdbdb35b8b72 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 10 Dec 2023 00:17:47 +0000 Subject: [PATCH 224/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 4c880a65e76..0a92a58567f 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.36+8 +YOSYS_VER := 0.36+13 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From cda470d63efd1ce7dcd3db11cdd37b28df7ba7c2 Mon Sep 17 00:00:00 2001 From: Dag Lem Date: Mon, 27 Nov 2023 15:28:06 +0100 Subject: [PATCH 225/240] Respect the sign of the right operand of AST_SHIFT and AST_SHIFTX The $shift and $shiftx cells perform a left logical shift if the second operand is negative. This change passes the sign of the second operand of AST_SHIFT and AST_SHIFTX into $shift and $shiftx cells, respectively. --- frontends/ast/genrtlil.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 6e750863fbe..0bae0f67374 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1740,7 +1740,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (width_hint < 0) detectSignWidth(width_hint, sign_hint); RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint); - RTLIL::SigSpec right = children[1]->genRTLIL(); + // for $shift and $shiftx, the second operand can be negative + RTLIL::SigSpec right = children[1]->genRTLIL(-1, type == AST_SHIFT || type == AST_SHIFTX); int width = width_hint > 0 ? width_hint : left.size(); is_signed = children[0]->is_signed; return binop2rtlil(this, type_name, width, left, right); From 655921e851cba90e30a66b82494e3836c9fa1639 Mon Sep 17 00:00:00 2001 From: Dag Lem Date: Fri, 11 Aug 2023 23:23:57 +0200 Subject: [PATCH 226/240] Uncloak array expressions generated by read_verilog -dump_vlog2 Explicit conversion of AST_TO_SIGNED, AST_TO_UNSIGNED, and AST_CAST_SIZE makes it possible to reason about simplified array expressions. --- frontends/ast/ast.cc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 5335a3992d6..34e6249939e 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -658,11 +658,20 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const if (0) { case AST_NEG: txt = "-"; } if (0) { case AST_LOGIC_NOT: txt = "!"; } if (0) { case AST_SELFSZ: txt = "@selfsz@"; } + if (0) { case AST_TO_SIGNED: txt = "signed'"; } + if (0) { case AST_TO_UNSIGNED: txt = "unsigned'"; } fprintf(f, "%s(", txt.c_str()); children[0]->dumpVlog(f, ""); fprintf(f, ")"); break; + case AST_CAST_SIZE: + children[0]->dumpVlog(f, ""); + fprintf(f, "'("); + children[1]->dumpVlog(f, ""); + fprintf(f, ")"); + break; + if (0) { case AST_BIT_AND: txt = "&"; } if (0) { case AST_BIT_OR: txt = "|"; } if (0) { case AST_BIT_XOR: txt = "^"; } From bcf5e923896eb84d9d342246a5c2dfd5c3b61c92 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 11 Dec 2023 22:10:51 +0100 Subject: [PATCH 227/240] cxxrtl: Fix `ctlz` implementation --- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index bd4affc3035..0be7ab2b214 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -508,12 +508,13 @@ struct value : public expr_base> { size_t count = 0; for (size_t n = 0; n < chunks; n++) { chunk::type x = data[chunks - 1 - n]; - if (x == 0) { - count += (n == 0 ? Bits % chunk::bits : chunk::bits); - } else { - // This loop implements the find first set idiom as recognized by LLVM. - for (; x != 0; count++) + // First add to `count` as if the chunk is zero + count += (n == 0 ? Bits % chunk::bits : chunk::bits); + // If the chunk isn't zero, correct the `count` value and return + if (x != 0) { + for (; x != 0; count--) x >>= 1; + break; } } return count; From c848d98d9196a9c86acc1a27c9f07b6b52872861 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 11 Dec 2023 22:11:35 +0100 Subject: [PATCH 228/240] cxxrtl: Fix `udivmod` logic --- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index 0be7ab2b214..a1d32fa605d 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -583,7 +583,7 @@ struct value : public expr_base> { value dividend = *this; if (dividend.ucmp(divisor)) return {/*quotient=*/value{0u}, /*remainder=*/dividend}; - uint32_t divisor_shift = dividend.ctlz() - divisor.ctlz(); + uint32_t divisor_shift = divisor.ctlz() - dividend.ctlz(); divisor = divisor.shl(value{divisor_shift}); for (size_t step = 0; step <= divisor_shift; step++) { quotient = quotient.shl(value{1u}); From 6206a3af304d25db1f8e057b9c88e0ad2d15dac4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 12 Dec 2023 09:51:17 +0100 Subject: [PATCH 229/240] cxxrtl: Handle case of `Bits < 4` in formatting of values --- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index a1d32fa605d..04ed48eb38e 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -796,7 +796,10 @@ std::ostream &operator<<(std::ostream &os, const value_formatted &vf) buf += '0'; while (!val.is_zero()) { value quotient, remainder; - std::tie(quotient, remainder) = val.udivmod(value{10u}); + if (Bits >= 4) + std::tie(quotient, remainder) = val.udivmod(value{10u}); + else + std::tie(quotient, remainder) = std::make_pair(value{0u}, val); buf += '0' + remainder.template trunc<(Bits > 4 ? 4 : Bits)>().val().template get(); val = quotient; } From 18d1907fa85eebb2c1d1ac9457b2f3d5928970be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 12 Dec 2023 09:52:35 +0100 Subject: [PATCH 230/240] cxxrtl: Assert well-formedness of input to `udivmod` --- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index 04ed48eb38e..2d545128754 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -583,8 +583,9 @@ struct value : public expr_base> { value dividend = *this; if (dividend.ucmp(divisor)) return {/*quotient=*/value{0u}, /*remainder=*/dividend}; - uint32_t divisor_shift = divisor.ctlz() - dividend.ctlz(); - divisor = divisor.shl(value{divisor_shift}); + int64_t divisor_shift = divisor.ctlz() - dividend.ctlz(); + assert(divisor_shift >= 0); + divisor = divisor.shl(value{(chunk::type) divisor_shift}); for (size_t step = 0; step <= divisor_shift; step++) { quotient = quotient.shl(value{1u}); if (!dividend.ucmp(divisor)) { From 3ea6bca23ec62d0869bc7c48fa6cc6ec4c3c0109 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 13 Dec 2023 00:16:10 +0000 Subject: [PATCH 231/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 0a92a58567f..8f3e473ea8b 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.36+13 +YOSYS_VER := 0.36+30 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From dbff694e3d6b48907d496e8b2517ad794243467a Mon Sep 17 00:00:00 2001 From: Henri Nurmi Date: Sat, 9 Dec 2023 22:27:05 +0200 Subject: [PATCH 232/240] cxxrtl: Use the base name of the interface file for the include directive Prior to this fix, the `CxxrtlBackend` used the entire path for the include directive when a separated interface file is generated (via the `-header` option). This commit updates the code to use the base name of the interface file. Since the C++11 standard is used by default, we cannot take advantage of the `std::filesystem` to get the basename. --- backends/cxxrtl/cxxrtl_backend.cc | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index a322ed3085c..ef276d9a534 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -628,6 +628,22 @@ std::string escape_cxx_string(const std::string &input) return output; } +std::string basename(const std::string &filepath) +{ +#ifndef _WIN32 + const std::string dir_seps = "/"; +#else + const std::string dir_seps = "\\/"; +#endif + size_t sep_pos = filepath.find_last_of(dir_seps); + if (sep_pos != std::string::npos && sep_pos + 1 < filepath.length()) { + return filepath.substr(sep_pos + 1); + } + else { + return filepath; + } +} + template std::string get_hdl_name(T *object) { @@ -2571,7 +2587,7 @@ struct CxxrtlWorker { } if (split_intf) - f << "#include \"" << intf_filename << "\"\n"; + f << "#include \"" << basename(intf_filename) << "\"\n"; else f << "#include \n"; if (has_prints) From 79c0bfcb2283d1a7665290a9a2074d0205c77fdc Mon Sep 17 00:00:00 2001 From: Henri Nurmi Date: Sun, 10 Dec 2023 07:42:27 +0200 Subject: [PATCH 233/240] cxxrtl: Remove unnecessary length check --- backends/cxxrtl/cxxrtl_backend.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index ef276d9a534..ab4456bba9a 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -636,7 +636,7 @@ std::string basename(const std::string &filepath) const std::string dir_seps = "\\/"; #endif size_t sep_pos = filepath.find_last_of(dir_seps); - if (sep_pos != std::string::npos && sep_pos + 1 < filepath.length()) { + if (sep_pos != std::string::npos) { return filepath.substr(sep_pos + 1); } else { From 1c8e58a7362e4dc5f0780ecfda43d81e4866c973 Mon Sep 17 00:00:00 2001 From: Henri Nurmi Date: Sun, 10 Dec 2023 08:15:41 +0200 Subject: [PATCH 234/240] cxxrtl: Fix formating --- backends/cxxrtl/cxxrtl_backend.cc | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index ab4456bba9a..1ab865a279c 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -630,18 +630,16 @@ std::string escape_cxx_string(const std::string &input) std::string basename(const std::string &filepath) { -#ifndef _WIN32 - const std::string dir_seps = "/"; -#else +#ifdef _WIN32 const std::string dir_seps = "\\/"; +#else + const std::string dir_seps = "/"; #endif size_t sep_pos = filepath.find_last_of(dir_seps); - if (sep_pos != std::string::npos) { + if (sep_pos != std::string::npos) return filepath.substr(sep_pos + 1); - } - else { + else return filepath; - } } template From ff53f3d2b6e267358cf4c3d08574416c79441ef9 Mon Sep 17 00:00:00 2001 From: Merry Date: Wed, 13 Dec 2023 12:02:30 +0000 Subject: [PATCH 235/240] cxxrtl: Fix value::shl --- Makefile | 1 + backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 1 + tests/cxxrtl/.gitignore | 1 + tests/cxxrtl/run-test.sh | 12 ++++++++++++ tests/cxxrtl/test_value.cc | 15 +++++++++++++++ 5 files changed, 30 insertions(+) create mode 100644 tests/cxxrtl/.gitignore create mode 100755 tests/cxxrtl/run-test.sh create mode 100644 tests/cxxrtl/test_value.cc diff --git a/Makefile b/Makefile index 8f3e473ea8b..8a72e3c7049 100644 --- a/Makefile +++ b/Makefile @@ -888,6 +888,7 @@ endif +cd tests/verilog && bash run-test.sh +cd tests/xprop && bash run-test.sh $(SEEDOPT) +cd tests/fmt && bash run-test.sh + +cd tests/cxxrtl && bash run-test.sh @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index 2d545128754..635c867aee7 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -419,6 +419,7 @@ struct value : public expr_base> { carry = (shift_bits == 0) ? 0 : data[n] >> (chunk::bits - shift_bits); } + result.data[result.chunks - 1] &= result.msb_mask; return result; } diff --git a/tests/cxxrtl/.gitignore b/tests/cxxrtl/.gitignore new file mode 100644 index 00000000000..91caee98625 --- /dev/null +++ b/tests/cxxrtl/.gitignore @@ -0,0 +1 @@ +cxxrtl-test-* diff --git a/tests/cxxrtl/run-test.sh b/tests/cxxrtl/run-test.sh new file mode 100755 index 00000000000..473a5a349ae --- /dev/null +++ b/tests/cxxrtl/run-test.sh @@ -0,0 +1,12 @@ +#!/bin/bash + +set -ex + +run_subtest () { + local subtest=$1; shift + + ${CC:-gcc} -std=c++11 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++ + ./cxxrtl-test-${subtest} +} + +run_subtest value diff --git a/tests/cxxrtl/test_value.cc b/tests/cxxrtl/test_value.cc new file mode 100644 index 00000000000..ca05b89ab48 --- /dev/null +++ b/tests/cxxrtl/test_value.cc @@ -0,0 +1,15 @@ +#include +#include + +#include "cxxrtl/cxxrtl.h" + +int main() +{ + { + // shl exceeding Bits should be masked + cxxrtl::value<6> a(1u); + cxxrtl::value<6> b(8u); + cxxrtl::value<6> c = a.shl(b); + assert(c.get() == 0); + } +} \ No newline at end of file From ded63bedd589255e6e06747edcdbf262444ac379 Mon Sep 17 00:00:00 2001 From: Merry Date: Wed, 13 Dec 2023 12:11:57 +0000 Subject: [PATCH 236/240] cxxrtl: Fix value::sshr --- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 11 ++++++----- tests/cxxrtl/test_value.cc | 24 ++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 5 deletions(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index 635c867aee7..c9ddb815f5c 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -430,12 +430,12 @@ struct value : public expr_base> { // Detect shifts definitely large than Bits early. for (size_t n = 1; n < amount.chunks; n++) if (amount.data[n] != 0) - return {}; + return (Signed && is_neg()) ? value().bit_not() : value(); // Past this point we can use the least significant chunk as the shift size. size_t shift_chunks = amount.data[0] / chunk::bits; size_t shift_bits = amount.data[0] % chunk::bits; if (shift_chunks >= chunks) - return {}; + return (Signed && is_neg()) ? value().bit_not() : value(); value result; chunk::type carry = 0; for (size_t n = 0; n < chunks - shift_chunks; n++) { @@ -444,12 +444,13 @@ struct value : public expr_base> { : data[chunks - 1 - n] << (chunk::bits - shift_bits); } if (Signed && is_neg()) { - size_t top_chunk_idx = (Bits - shift_bits) / chunk::bits; - size_t top_chunk_bits = (Bits - shift_bits) % chunk::bits; + size_t top_chunk_idx = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) / chunk::bits; + size_t top_chunk_bits = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) % chunk::bits; for (size_t n = top_chunk_idx + 1; n < chunks; n++) result.data[n] = chunk::mask; - if (shift_bits != 0) + if (amount.data[0] != 0) result.data[top_chunk_idx] |= chunk::mask << top_chunk_bits; + result.data[result.chunks - 1] &= result.msb_mask; } return result; } diff --git a/tests/cxxrtl/test_value.cc b/tests/cxxrtl/test_value.cc index ca05b89ab48..c553f61121c 100644 --- a/tests/cxxrtl/test_value.cc +++ b/tests/cxxrtl/test_value.cc @@ -12,4 +12,28 @@ int main() cxxrtl::value<6> c = a.shl(b); assert(c.get() == 0); } + + { + // sshr of unreasonably large size should sign extend correctly + cxxrtl::value<64> a(0u, 0x80000000u); + cxxrtl::value<64> b(0u, 1u); + cxxrtl::value<64> c = a.sshr(b); + assert(c.get() == 0xffffffffffffffffu); + } + + { + // sshr of exteeding Bits should sign extend correctly + cxxrtl::value<8> a(0x80u); + cxxrtl::value<8> b(10u); + cxxrtl::value<8> c = a.sshr(b); + assert(c.get() == 0xffu); + } + + { + // Sign extension should occur correctly + cxxrtl::value<64> a(0x23456789u, 0x8abcdef1u); + cxxrtl::value<8> b(32u); + cxxrtl::value<64> c = a.sshr(b); + assert(c.get() == 0xffffffff8abcdef1u); + } } \ No newline at end of file From d7cb6981b55a15eee3d0d9be84446826a65c0403 Mon Sep 17 00:00:00 2001 From: Merry Date: Wed, 13 Dec 2023 12:15:12 +0000 Subject: [PATCH 237/240] cxxrtl: Fix value::ctlz --- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 3 ++- tests/cxxrtl/test_value.cc | 8 +++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index c9ddb815f5c..d861b7e072a 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -511,7 +511,8 @@ struct value : public expr_base> { for (size_t n = 0; n < chunks; n++) { chunk::type x = data[chunks - 1 - n]; // First add to `count` as if the chunk is zero - count += (n == 0 ? Bits % chunk::bits : chunk::bits); + constexpr size_t msb_chunk_bits = Bits % chunk::bits != 0 ? Bits % chunk::bits : chunk::bits; + count += (n == 0 ? msb_chunk_bits : chunk::bits); // If the chunk isn't zero, correct the `count` value and return if (x != 0) { for (; x != 0; count--) diff --git a/tests/cxxrtl/test_value.cc b/tests/cxxrtl/test_value.cc index c553f61121c..4d68372bbd1 100644 --- a/tests/cxxrtl/test_value.cc +++ b/tests/cxxrtl/test_value.cc @@ -36,4 +36,10 @@ int main() cxxrtl::value<64> c = a.sshr(b); assert(c.get() == 0xffffffff8abcdef1u); } -} \ No newline at end of file + + { + // ctlz should work with Bits that are a multiple of chunk size + cxxrtl::value<32> a(0x00040000u); + assert(a.ctlz() == 13); + } +} From 29e0cc6acd4eb1c288cf0742b4bfa978fab3c1da Mon Sep 17 00:00:00 2001 From: Merry Date: Wed, 13 Dec 2023 12:18:13 +0000 Subject: [PATCH 238/240] cxxrtl: Add simple fuzzing tests for value --- tests/cxxrtl/run-test.sh | 1 + tests/cxxrtl/test_value_fuzz.cc | 251 ++++++++++++++++++++++++++++++++ 2 files changed, 252 insertions(+) create mode 100644 tests/cxxrtl/test_value_fuzz.cc diff --git a/tests/cxxrtl/run-test.sh b/tests/cxxrtl/run-test.sh index 473a5a349ae..ff2c35fafe6 100755 --- a/tests/cxxrtl/run-test.sh +++ b/tests/cxxrtl/run-test.sh @@ -10,3 +10,4 @@ run_subtest () { } run_subtest value +run_subtest value_fuzz diff --git a/tests/cxxrtl/test_value_fuzz.cc b/tests/cxxrtl/test_value_fuzz.cc new file mode 100644 index 00000000000..4428e9f6e7f --- /dev/null +++ b/tests/cxxrtl/test_value_fuzz.cc @@ -0,0 +1,251 @@ +#include +#include +#include +#include +#include +#include +#include + +#include "cxxrtl/cxxrtl.h" + +template +T rand_int(T min = std::numeric_limits::min(), T max = std::numeric_limits::max()) +{ + static_assert(std::is_integral::value, "T must be an integral type."); + static_assert(!std::is_same::value && !std::is_same::value, + "Using char with uniform_int_distribution is undefined behavior."); + + static std::mt19937 generator = [] { + std::random_device rd; + std::mt19937 mt{rd()}; + return mt; + }(); + + std::uniform_int_distribution dist(min, max); + return dist(generator); +} + +struct BinaryOperationBase +{ + void tweak_input(uint64_t &a, uint64_t &b) {} +}; + +template +void test_binary_operation_for_bitsize(Operation &op) +{ + constexpr int iteration_count = 10000000; + + constexpr uint64_t mask = std::numeric_limits::max() >> (64 - Bits); + + using chunk_type = typename cxxrtl::value::chunk::type; + constexpr size_t chunk_bits = cxxrtl::value::chunk::bits; + + for (int iteration = 0; iteration < iteration_count; iteration++) { + uint64_t ia = rand_int() >> (64 - Bits); + uint64_t ib = rand_int() >> (64 - Bits); + op.tweak_input(ia, ib); + + cxxrtl::value va, vb; + for (size_t i = 0; i * chunk_bits < Bits; i++) { + va.data[i] = (chunk_type)(ia >> (i * chunk_bits)); + vb.data[i] = (chunk_type)(ib >> (i * chunk_bits)); + } + + uint64_t iresult = op.reference_impl(Bits, ia, ib) & mask; + cxxrtl::value vresult = op.template testing_impl(va, vb); + + for (size_t i = 0; i * chunk_bits < Bits; i++) { + if ((chunk_type)(iresult >> (i * chunk_bits)) != vresult.data[i]) { + std::printf("Test failure:\n"); + std::printf("Bits: %i\n", Bits); + std::printf("a: %016lx\n", ia); + std::printf("b: %016lx\n", ib); + std::printf("iresult: %016lx\n", iresult); + std::printf("vresult: %016lx\n", vresult.template get()); + + std::terminate(); + } + } + } + std::printf("Test passed @ Bits = %i.\n", Bits); +} + +template +void test_binary_operation(Operation &op) +{ + // Test at a variety of bitwidths + test_binary_operation_for_bitsize<8>(op); + test_binary_operation_for_bitsize<32>(op); + test_binary_operation_for_bitsize<42>(op); + test_binary_operation_for_bitsize<63>(op); + test_binary_operation_for_bitsize<64>(op); +} + +template +struct UnaryOperationWrapper : BinaryOperationBase +{ + Operation &op; + + UnaryOperationWrapper(Operation &op) : op(op) {} + + uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b) + { + return op.reference_impl(bits, a); + } + + template + cxxrtl::value testing_impl(cxxrtl::value a, cxxrtl::value b) + { + return op.template testing_impl(a); + } +}; + +template +void test_unary_operation(Operation &op) +{ + UnaryOperationWrapper wrapped(op); + test_binary_operation(wrapped); +} + +struct ShlTest : BinaryOperationBase +{ + ShlTest() + { + std::printf("Randomized tests for value::shl:\n"); + test_binary_operation(*this); + } + + uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b) + { + return b >= 64 ? 0 : a << b; + } + + template + cxxrtl::value testing_impl(cxxrtl::value a, cxxrtl::value b) + { + return a.shl(b); + } + + void tweak_input(uint64_t &, uint64_t &b) + { + b &= 0x7f; + } +} shl; + +struct ShrTest : BinaryOperationBase +{ + ShrTest() + { + std::printf("Randomized tests for value::shr:\n"); + test_binary_operation(*this); + } + + uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b) + { + return b >= 64 ? 0 : a >> b; + } + + template + cxxrtl::value testing_impl(cxxrtl::value a, cxxrtl::value b) + { + return a.shr(b); + } + + void tweak_input(uint64_t &, uint64_t &b) + { + b &= 0x7f; + } +} shr; + +struct SshrTest : BinaryOperationBase +{ + SshrTest() + { + std::printf("Randomized tests for value::sshr:\n"); + test_binary_operation(*this); + } + + uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b) + { + int64_t sa = (int64_t)(a << (64 - bits)); + return sa >> (b >= bits ? 63 : (b + 64 - bits)); + } + + template + cxxrtl::value testing_impl(cxxrtl::value a, cxxrtl::value b) + { + return a.sshr(b); + } + + void tweak_input(uint64_t &, uint64_t &b) + { + b &= 0x7f; + } +} sshr; + +struct AddTest : BinaryOperationBase +{ + AddTest() + { + std::printf("Randomized tests for value::add:\n"); + test_binary_operation(*this); + } + + uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b) + { + return a + b; + } + + template + cxxrtl::value testing_impl(cxxrtl::value a, cxxrtl::value b) + { + return a.add(b); + } +} add; + +struct SubTest : BinaryOperationBase +{ + SubTest() + { + std::printf("Randomized tests for value::sub:\n"); + test_binary_operation(*this); + } + + uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b) + { + return a - b; + } + + template + cxxrtl::value testing_impl(cxxrtl::value a, cxxrtl::value b) + { + return a.sub(b); + } +} sub; + +struct CtlzTest +{ + CtlzTest() + { + std::printf("Randomized tests for value::ctlz:\n"); + test_unary_operation(*this); + } + + uint64_t reference_impl(size_t bits, uint64_t a) + { + if (a == 0) + return bits; + return __builtin_clzl(a) - (64 - bits); + } + + template + cxxrtl::value testing_impl(cxxrtl::value a) + { + size_t result = a.ctlz(); + return cxxrtl::value((cxxrtl::chunk_t)result); + } +} ctlz; + +int main() +{ +} From 1dff3c83d97724ee7d4872404b8df7201773734c Mon Sep 17 00:00:00 2001 From: Merry Date: Wed, 13 Dec 2023 12:27:06 +0000 Subject: [PATCH 239/240] tests/cxxrtl: Add -O2 --- tests/cxxrtl/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/cxxrtl/run-test.sh b/tests/cxxrtl/run-test.sh index ff2c35fafe6..89de71c6b26 100755 --- a/tests/cxxrtl/run-test.sh +++ b/tests/cxxrtl/run-test.sh @@ -5,7 +5,7 @@ set -ex run_subtest () { local subtest=$1; shift - ${CC:-gcc} -std=c++11 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++ + ${CC:-gcc} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++ ./cxxrtl-test-${subtest} } From 39fdde87a782695a98bc3e93cb767086ee23c5cc Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 14 Dec 2023 00:16:03 +0000 Subject: [PATCH 240/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 8a72e3c7049..446682e86e9 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.36+30 +YOSYS_VER := 0.36+40 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo